{"diffoscope-json-version": 1, "source1": "/srv/reproducible-results/rbuild-debian/tmp.hN4AOZ5y2g/b1/python-peachpy_0.0~git20200303.f189ad2-3_amd64.changes", "source2": "/srv/reproducible-results/rbuild-debian/tmp.hN4AOZ5y2g/b2/python-peachpy_0.0~git20200303.f189ad2-3_amd64.changes", "unified_diff": null, "details": [{"source1": "Files", "source2": "Files", "unified_diff": "@@ -1,3 +1,3 @@\n \n- 3c806ff8a6a35d32939767ffe8055848 53916 doc optional python-peachpy-doc_0.0~git20200303.f189ad2-3_all.deb\n- 5ed7290c509d65f75cfe20dc2dd2f3c0 193092 python optional python3-peachpy_0.0~git20200303.f189ad2-3_amd64.deb\n+ c58a7d9e0564818c7747601b73e34b9a 53908 doc optional python-peachpy-doc_0.0~git20200303.f189ad2-3_all.deb\n+ 1aad951440ad297a748720032f664255 193152 python optional python3-peachpy_0.0~git20200303.f189ad2-3_amd64.deb\n"}, {"source1": "python-peachpy-doc_0.0~git20200303.f189ad2-3_all.deb", "source2": "python-peachpy-doc_0.0~git20200303.f189ad2-3_all.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r--   0        0        0        4 2020-06-27 13:11:45.000000 debian-binary\n -rw-r--r--   0        0        0     1216 2020-06-27 13:11:45.000000 control.tar.xz\n--rw-r--r--   0        0        0    52508 2020-06-27 13:11:45.000000 data.tar.xz\n+-rw-r--r--   0        0        0    52500 2020-06-27 13:11:45.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "./usr/share/doc/python3-peachpy/html/peachpy.html", "source2": "./usr/share/doc/python3-peachpy/html/peachpy.html", "unified_diff": "@@ -8674,29 +8674,29 @@\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPBROADCASTMB2Q\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPBROADCASTMB2Q</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPBROADCASTMB2Q\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Broadcast Low Byte of Mask Register to Packed Quadword Values</p>\n <p>Supported forms:</p>\n <ul class=\"simple\">\n-<li><p>VPBROADCASTMB2Q(zmm, k)    [AVX512CD]</p></li>\n <li><p>VPBROADCASTMB2Q(xmm, k)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPBROADCASTMB2Q(ymm, k)    [AVX512VL and AVX512CD]</p></li>\n+<li><p>VPBROADCASTMB2Q(zmm, k)    [AVX512CD]</p></li>\n </ul>\n </dd></dl>\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPBROADCASTMW2D\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPBROADCASTMW2D</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPBROADCASTMW2D\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Broadcast Low Word of Mask Register to Packed Doubleword Values</p>\n <p>Supported forms:</p>\n <ul class=\"simple\">\n-<li><p>VPBROADCASTMW2D(zmm, k)    [AVX512CD]</p></li>\n <li><p>VPBROADCASTMW2D(xmm, k)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPBROADCASTMW2D(ymm, k)    [AVX512VL and AVX512CD]</p></li>\n+<li><p>VPBROADCASTMW2D(zmm, k)    [AVX512CD]</p></li>\n </ul>\n </dd></dl>\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPBROADCASTQ\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPBROADCASTQ</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPBROADCASTQ\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Broadcast Quadword Integer</p>\n@@ -9034,35 +9034,35 @@\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPCONFLICTD\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPCONFLICTD</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPCONFLICTD\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register</p>\n <p>Supported forms:</p>\n <ul class=\"simple\">\n-<li><p>VPCONFLICTD(zmm{k}{z}, m512/m32bcst)    [AVX512CD]</p></li>\n-<li><p>VPCONFLICTD(zmm{k}{z}, zmm)             [AVX512CD]</p></li>\n <li><p>VPCONFLICTD(xmm{k}{z}, m128/m32bcst)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPCONFLICTD(ymm{k}{z}, m256/m32bcst)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPCONFLICTD(xmm{k}{z}, xmm)             [AVX512VL and AVX512CD]</p></li>\n <li><p>VPCONFLICTD(ymm{k}{z}, ymm)             [AVX512VL and AVX512CD]</p></li>\n+<li><p>VPCONFLICTD(zmm{k}{z}, m512/m32bcst)    [AVX512CD]</p></li>\n+<li><p>VPCONFLICTD(zmm{k}{z}, zmm)             [AVX512CD]</p></li>\n </ul>\n </dd></dl>\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPCONFLICTQ\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPCONFLICTQ</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPCONFLICTQ\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register</p>\n <p>Supported forms:</p>\n <ul class=\"simple\">\n-<li><p>VPCONFLICTQ(zmm{k}{z}, m512/m64bcst)    [AVX512CD]</p></li>\n-<li><p>VPCONFLICTQ(zmm{k}{z}, zmm)             [AVX512CD]</p></li>\n <li><p>VPCONFLICTQ(xmm{k}{z}, m128/m64bcst)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPCONFLICTQ(ymm{k}{z}, m256/m64bcst)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPCONFLICTQ(xmm{k}{z}, xmm)             [AVX512VL and AVX512CD]</p></li>\n <li><p>VPCONFLICTQ(ymm{k}{z}, ymm)             [AVX512VL and AVX512CD]</p></li>\n+<li><p>VPCONFLICTQ(zmm{k}{z}, m512/m64bcst)    [AVX512CD]</p></li>\n+<li><p>VPCONFLICTQ(zmm{k}{z}, zmm)             [AVX512CD]</p></li>\n </ul>\n </dd></dl>\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPERM2F128\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPERM2F128</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPERM2F128\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Permute Floating-Point Values</p>\n@@ -9642,35 +9642,35 @@\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPLZCNTD\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPLZCNTD</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPLZCNTD\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Count the Number of Leading Zero Bits for Packed Doubleword Values</p>\n <p>Supported forms:</p>\n <ul class=\"simple\">\n-<li><p>VPLZCNTD(zmm{k}{z}, m512/m32bcst)    [AVX512CD]</p></li>\n-<li><p>VPLZCNTD(zmm{k}{z}, zmm)             [AVX512CD]</p></li>\n <li><p>VPLZCNTD(xmm{k}{z}, m128/m32bcst)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPLZCNTD(ymm{k}{z}, m256/m32bcst)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPLZCNTD(xmm{k}{z}, xmm)             [AVX512VL and AVX512CD]</p></li>\n <li><p>VPLZCNTD(ymm{k}{z}, ymm)             [AVX512VL and AVX512CD]</p></li>\n+<li><p>VPLZCNTD(zmm{k}{z}, m512/m32bcst)    [AVX512CD]</p></li>\n+<li><p>VPLZCNTD(zmm{k}{z}, zmm)             [AVX512CD]</p></li>\n </ul>\n </dd></dl>\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPLZCNTQ\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPLZCNTQ</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPLZCNTQ\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Count the Number of Leading Zero Bits for Packed Quadword Values</p>\n <p>Supported forms:</p>\n <ul class=\"simple\">\n-<li><p>VPLZCNTQ(zmm{k}{z}, m512/m64bcst)    [AVX512CD]</p></li>\n-<li><p>VPLZCNTQ(zmm{k}{z}, zmm)             [AVX512CD]</p></li>\n <li><p>VPLZCNTQ(xmm{k}{z}, m128/m64bcst)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPLZCNTQ(ymm{k}{z}, m256/m64bcst)    [AVX512VL and AVX512CD]</p></li>\n <li><p>VPLZCNTQ(xmm{k}{z}, xmm)             [AVX512VL and AVX512CD]</p></li>\n <li><p>VPLZCNTQ(ymm{k}{z}, ymm)             [AVX512VL and AVX512CD]</p></li>\n+<li><p>VPLZCNTQ(zmm{k}{z}, m512/m64bcst)    [AVX512CD]</p></li>\n+<li><p>VPLZCNTQ(zmm{k}{z}, zmm)             [AVX512CD]</p></li>\n </ul>\n </dd></dl>\n \n <dl class=\"class\">\n <dt id=\"peachpy.x86_64.avx.VPMADD52HUQ\">\n <em class=\"property\">class </em><code class=\"sig-prename descclassname\">peachpy.x86_64.avx.</code><code class=\"sig-name descname\">VPMADD52HUQ</code><span class=\"sig-paren\">(</span><em class=\"sig-param\">*args</em>, <em class=\"sig-param\">**kwargs</em><span class=\"sig-paren\">)</span><a class=\"headerlink\" href=\"#peachpy.x86_64.avx.VPMADD52HUQ\" title=\"Permalink to this definition\">\u00b6</a></dt>\n <dd><p>Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators</p>\n"}]}]}]}, {"source1": "python3-peachpy_0.0~git20200303.f189ad2-3_amd64.deb", "source2": "python3-peachpy_0.0~git20200303.f189ad2-3_amd64.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r--   0        0        0        4 2020-06-27 13:11:45.000000 debian-binary\n -rw-r--r--   0        0        0     3168 2020-06-27 13:11:45.000000 control.tar.xz\n--rw-r--r--   0        0        0   189732 2020-06-27 13:11:45.000000 data.tar.xz\n+-rw-r--r--   0        0        0   189792 2020-06-27 13:11:45.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "./usr/lib/python3/dist-packages/peachpy/x86_64/avx.py", "source2": "./usr/lib/python3/dist-packages/peachpy/x86_64/avx.py", "unified_diff": "@@ -4197,16 +4197,16 @@\n class VEXPANDPD(Instruction):\n     \"\"\"Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory\"\"\"\n \n     def __init__(self, *args, **kwargs):\n         \"\"\"Supported forms:\n \n             * VEXPANDPD(zmm{k}{z}, zmm/m512)    [AVX512F]\n-            * VEXPANDPD(xmm{k}{z}, xmm/m128)    [AVX512VL]\n             * VEXPANDPD(ymm{k}{z}, ymm/m256)    [AVX512F and AVX512VL]\n+            * VEXPANDPD(xmm{k}{z}, xmm/m128)    [AVX512VL]\n         \"\"\"\n \n         origin = kwargs.get(\"origin\")\n         prototype = kwargs.get(\"prototype\")\n         if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n             origin = inspect.stack()\n         super(VEXPANDPD, self).__init__(\"VEXPANDPD\", origin=origin, prototype=prototype)\n@@ -6366,18 +6366,18 @@\n \n     def __init__(self, *args, **kwargs):\n         \"\"\"Supported forms:\n \n             * VFIXUPIMMPS(zmm{k}{z}, zmm, m512/m32bcst, imm8)    [AVX512F]\n             * VFIXUPIMMPS(zmm{k}{z}, zmm, zmm, {sae}, imm8)      [AVX512F]\n             * VFIXUPIMMPS(zmm{k}{z}, zmm, zmm, imm8)             [AVX512F]\n-            * VFIXUPIMMPS(xmm{k}{z}, xmm, m128/m32bcst, imm8)    [AVX512VL]\n-            * VFIXUPIMMPS(xmm{k}{z}, xmm, xmm, imm8)             [AVX512VL]\n             * VFIXUPIMMPS(ymm{k}{z}, ymm, m256/m32bcst, imm8)    [AVX512F and AVX512VL]\n             * VFIXUPIMMPS(ymm{k}{z}, ymm, ymm, imm8)             [AVX512F and AVX512VL]\n+            * VFIXUPIMMPS(xmm{k}{z}, xmm, m128/m32bcst, imm8)    [AVX512VL]\n+            * VFIXUPIMMPS(xmm{k}{z}, xmm, xmm, imm8)             [AVX512VL]\n         \"\"\"\n \n         origin = kwargs.get(\"origin\")\n         prototype = kwargs.get(\"prototype\")\n         if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n             origin = inspect.stack()\n         super(VFIXUPIMMPS, self).__init__(\"VFIXUPIMMPS\", origin=origin, prototype=prototype)\n@@ -19232,20 +19232,20 @@\n \n class VPMADD52LUQ(Instruction):\n     \"\"\"Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators\"\"\"\n \n     def __init__(self, *args, **kwargs):\n         \"\"\"Supported forms:\n \n-            * VPMADD52LUQ(zmm{k}{z}, zmm, m512/m64bcst)    [AVX512IFMA]\n-            * VPMADD52LUQ(zmm{k}{z}, zmm, zmm)             [AVX512IFMA]\n             * VPMADD52LUQ(xmm{k}{z}, xmm, m128/m64bcst)    [AVX512VL and AVX512IFMA]\n             * VPMADD52LUQ(xmm{k}{z}, xmm, xmm)             [AVX512VL and AVX512IFMA]\n             * VPMADD52LUQ(ymm{k}{z}, ymm, m256/m64bcst)    [AVX512VL and AVX512IFMA]\n             * VPMADD52LUQ(ymm{k}{z}, ymm, ymm)             [AVX512VL and AVX512IFMA]\n+            * VPMADD52LUQ(zmm{k}{z}, zmm, m512/m64bcst)    [AVX512IFMA]\n+            * VPMADD52LUQ(zmm{k}{z}, zmm, zmm)             [AVX512IFMA]\n         \"\"\"\n \n         origin = kwargs.get(\"origin\")\n         prototype = kwargs.get(\"prototype\")\n         if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n             origin = inspect.stack()\n         super(VPMADD52LUQ, self).__init__(\"VPMADD52LUQ\", origin=origin, prototype=prototype)\n@@ -19282,20 +19282,20 @@\n \n class VPMADD52HUQ(Instruction):\n     \"\"\"Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators\"\"\"\n \n     def __init__(self, *args, **kwargs):\n         \"\"\"Supported forms:\n \n-            * VPMADD52HUQ(zmm{k}{z}, zmm, m512/m64bcst)    [AVX512IFMA]\n-            * VPMADD52HUQ(zmm{k}{z}, zmm, zmm)             [AVX512IFMA]\n             * VPMADD52HUQ(xmm{k}{z}, xmm, m128/m64bcst)    [AVX512VL and AVX512IFMA]\n             * VPMADD52HUQ(xmm{k}{z}, xmm, xmm)             [AVX512VL and AVX512IFMA]\n             * VPMADD52HUQ(ymm{k}{z}, ymm, m256/m64bcst)    [AVX512VL and AVX512IFMA]\n             * VPMADD52HUQ(ymm{k}{z}, ymm, ymm)             [AVX512VL and AVX512IFMA]\n+            * VPMADD52HUQ(zmm{k}{z}, zmm, m512/m64bcst)    [AVX512IFMA]\n+            * VPMADD52HUQ(zmm{k}{z}, zmm, zmm)             [AVX512IFMA]\n         \"\"\"\n \n         origin = kwargs.get(\"origin\")\n         prototype = kwargs.get(\"prototype\")\n         if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n             origin = inspect.stack()\n         super(VPMADD52HUQ, self).__init__(\"VPMADD52HUQ\", origin=origin, prototype=prototype)\n@@ -26800,18 +26800,18 @@\n         \"\"\"Supported forms:\n \n             * VCVTPS2PD(xmm, xmm/m64)               [AVX]\n             * VCVTPS2PD(ymm, xmm/m128)              [AVX]\n             * VCVTPS2PD(zmm{k}{z}, m256/m32bcst)    [AVX512F]\n             * VCVTPS2PD(zmm{k}{z}, ymm, {sae})      [AVX512F]\n             * VCVTPS2PD(zmm{k}{z}, ymm)             [AVX512F]\n-            * VCVTPS2PD(xmm{k}{z}, m64/m32bcst)     [AVX512F and AVX512VL]\n-            * VCVTPS2PD(xmm{k}{z}, xmm)             [AVX512F and AVX512VL]\n             * VCVTPS2PD(ymm{k}{z}, m128/m32bcst)    [AVX512VL]\n             * VCVTPS2PD(ymm{k}{z}, xmm)             [AVX512VL]\n+            * VCVTPS2PD(xmm{k}{z}, m64/m32bcst)     [AVX512F and AVX512VL]\n+            * VCVTPS2PD(xmm{k}{z}, xmm)             [AVX512F and AVX512VL]\n         \"\"\"\n \n         origin = kwargs.get(\"origin\")\n         prototype = kwargs.get(\"prototype\")\n         if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n             origin = inspect.stack()\n         super(VCVTPS2PD, self).__init__(\"VCVTPS2PD\", origin=origin, prototype=prototype)\n"}, {"source1": "./usr/lib/python3/dist-packages/peachpy/x86_64/generic.py", "source2": "./usr/lib/python3/dist-packages/peachpy/x86_64/generic.py", "unified_diff": "@@ -4954,15 +4954,15 @@\n                 self._implicit_in_regs = {0: 1}\n                 self._implicit_out_regs = {0: 3}\n             elif is_r16(self.operands[0]):\n                 self.go_name = \"IMULW\"\n                 self._gas_name = \"imulw\"\n                 self.encodings.append((0x20, lambda op, rex=False: bytearray([0x66]) + optional_rex(0, op[0], rex) + bytearray([0xF7, 0xE8 | op[0].lcode])))\n                 self._implicit_in_regs = {0: 3}\n-                self._implicit_out_regs = {0: 3, 2: 3}\n+                self._implicit_out_regs = {2: 3, 0: 3}\n             elif is_r32(self.operands[0]):\n                 self.go_name = \"IMULL\"\n                 self._gas_name = \"imull\"\n                 self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex) + bytearray([0xF7, 0xE8 | op[0].lcode])))\n                 self._implicit_in_regs = {0: 7}\n                 self._implicit_out_regs = {0: 7, 2: 7}\n             elif is_r64(self.operands[0]):\n@@ -4978,15 +4978,15 @@\n                 self._implicit_in_regs = {0: 1}\n                 self._implicit_out_regs = {0: 3}\n             elif is_m16(self.operands[0]):\n                 self.go_name = \"IMULW\"\n                 self._gas_name = \"imulw\"\n                 self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: bytearray([0x66]) + optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(5, op[0].address, sib, min_disp)))\n                 self._implicit_in_regs = {0: 3}\n-                self._implicit_out_regs = {0: 3, 2: 3}\n+                self._implicit_out_regs = {2: 3, 0: 3}\n             elif is_m32(self.operands[0]):\n                 self.go_name = \"IMULL\"\n                 self._gas_name = \"imull\"\n                 self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(5, op[0].address, sib, min_disp)))\n                 self._implicit_in_regs = {0: 7}\n                 self._implicit_out_regs = {0: 7, 2: 7}\n             elif is_m64(self.operands[0]):\n@@ -5113,15 +5113,15 @@\n             self._implicit_in_regs = {0: 1}\n             self._implicit_out_regs = {0: 3}\n         elif is_r16(self.operands[0]):\n             self.go_name = \"MULW\"\n             self._gas_name = \"mulw\"\n             self.encodings.append((0x20, lambda op, rex=False: bytearray([0x66]) + optional_rex(0, op[0], rex) + bytearray([0xF7, 0xE0 | op[0].lcode])))\n             self._implicit_in_regs = {0: 3}\n-            self._implicit_out_regs = {0: 3, 2: 3}\n+            self._implicit_out_regs = {2: 3, 0: 3}\n         elif is_r32(self.operands[0]):\n             self.go_name = \"MULL\"\n             self._gas_name = \"mull\"\n             self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex) + bytearray([0xF7, 0xE0 | op[0].lcode])))\n             self._implicit_in_regs = {0: 7}\n             self._implicit_out_regs = {0: 7, 2: 7}\n         elif is_r64(self.operands[0]):\n@@ -5137,15 +5137,15 @@\n             self._implicit_in_regs = {0: 1}\n             self._implicit_out_regs = {0: 3}\n         elif is_m16(self.operands[0]):\n             self.go_name = \"MULW\"\n             self._gas_name = \"mulw\"\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: bytearray([0x66]) + optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(4, op[0].address, sib, min_disp)))\n             self._implicit_in_regs = {0: 3}\n-            self._implicit_out_regs = {0: 3, 2: 3}\n+            self._implicit_out_regs = {2: 3, 0: 3}\n         elif is_m32(self.operands[0]):\n             self.go_name = \"MULL\"\n             self._gas_name = \"mull\"\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(4, op[0].address, sib, min_disp)))\n             self._implicit_in_regs = {0: 7}\n             self._implicit_out_regs = {0: 7, 2: 7}\n         elif is_m64(self.operands[0]):\n@@ -5233,16 +5233,16 @@\n             self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex or is_r8rex(op[0])) + bytearray([0xF6, 0xF8 | op[0].lcode])))\n             self._implicit_in_regs = {0: 3}\n             self._implicit_out_regs = {0: 3}\n         elif is_r16(self.operands[0]):\n             self.go_name = \"IDIVW\"\n             self._gas_name = \"idivw\"\n             self.encodings.append((0x20, lambda op, rex=False: bytearray([0x66]) + optional_rex(0, op[0], rex) + bytearray([0xF7, 0xF8 | op[0].lcode])))\n-            self._implicit_in_regs = {0: 3, 2: 3}\n-            self._implicit_out_regs = {0: 3, 2: 3}\n+            self._implicit_in_regs = {2: 3, 0: 3}\n+            self._implicit_out_regs = {2: 3, 0: 3}\n         elif is_r32(self.operands[0]):\n             self.go_name = \"IDIVL\"\n             self._gas_name = \"idivl\"\n             self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex) + bytearray([0xF7, 0xF8 | op[0].lcode])))\n             self._implicit_in_regs = {0: 7, 2: 7}\n             self._implicit_out_regs = {0: 7, 2: 7}\n         elif is_r64(self.operands[0]):\n@@ -5257,16 +5257,16 @@\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF6]) + modrm_sib_disp(7, op[0].address, sib, min_disp)))\n             self._implicit_in_regs = {0: 3}\n             self._implicit_out_regs = {0: 3}\n         elif is_m16(self.operands[0]):\n             self.go_name = \"IDIVW\"\n             self._gas_name = \"idivw\"\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: bytearray([0x66]) + optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(7, op[0].address, sib, min_disp)))\n-            self._implicit_in_regs = {0: 3, 2: 3}\n-            self._implicit_out_regs = {0: 3, 2: 3}\n+            self._implicit_in_regs = {2: 3, 0: 3}\n+            self._implicit_out_regs = {2: 3, 0: 3}\n         elif is_m32(self.operands[0]):\n             self.go_name = \"IDIVL\"\n             self._gas_name = \"idivl\"\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(7, op[0].address, sib, min_disp)))\n             self._implicit_in_regs = {0: 7, 2: 7}\n             self._implicit_out_regs = {0: 7, 2: 7}\n         elif is_m64(self.operands[0]):\n@@ -5310,16 +5310,16 @@\n             self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex or is_r8rex(op[0])) + bytearray([0xF6, 0xF0 | op[0].lcode])))\n             self._implicit_in_regs = {0: 3}\n             self._implicit_out_regs = {0: 3}\n         elif is_r16(self.operands[0]):\n             self.go_name = \"DIVW\"\n             self._gas_name = \"divw\"\n             self.encodings.append((0x20, lambda op, rex=False: bytearray([0x66]) + optional_rex(0, op[0], rex) + bytearray([0xF7, 0xF0 | op[0].lcode])))\n-            self._implicit_in_regs = {0: 3, 2: 3}\n-            self._implicit_out_regs = {0: 3, 2: 3}\n+            self._implicit_in_regs = {2: 3, 0: 3}\n+            self._implicit_out_regs = {2: 3, 0: 3}\n         elif is_r32(self.operands[0]):\n             self.go_name = \"DIVL\"\n             self._gas_name = \"divl\"\n             self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex) + bytearray([0xF7, 0xF0 | op[0].lcode])))\n             self._implicit_in_regs = {0: 7, 2: 7}\n             self._implicit_out_regs = {0: 7, 2: 7}\n         elif is_r64(self.operands[0]):\n@@ -5334,16 +5334,16 @@\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF6]) + modrm_sib_disp(6, op[0].address, sib, min_disp)))\n             self._implicit_in_regs = {0: 3}\n             self._implicit_out_regs = {0: 3}\n         elif is_m16(self.operands[0]):\n             self.go_name = \"DIVW\"\n             self._gas_name = \"divw\"\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: bytearray([0x66]) + optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(6, op[0].address, sib, min_disp)))\n-            self._implicit_in_regs = {0: 3, 2: 3}\n-            self._implicit_out_regs = {0: 3, 2: 3}\n+            self._implicit_in_regs = {2: 3, 0: 3}\n+            self._implicit_out_regs = {2: 3, 0: 3}\n         elif is_m32(self.operands[0]):\n             self.go_name = \"DIVL\"\n             self._gas_name = \"divl\"\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(6, op[0].address, sib, min_disp)))\n             self._implicit_in_regs = {0: 7, 2: 7}\n             self._implicit_out_regs = {0: 7, 2: 7}\n         elif is_m64(self.operands[0]):\n@@ -10016,16 +10016,16 @@\n             origin = inspect.stack()\n         super(CPUID, self).__init__(\"CPUID\", origin=origin, prototype=prototype)\n         self.operands = tuple(map(check_operand, args))\n         if len(self.operands) != 0:\n             raise SyntaxError(\"Instruction \\\"CPUID\\\" requires 0 operands\")\n         self.go_name = \"CPUID\"\n         self.encodings.append((0x00, lambda op: bytearray([0x0F, 0xA2])))\n-        self._implicit_in_regs = {1: 7, 0: 7}\n-        self._implicit_out_regs = {1: 7, 0: 7, 3: 7, 2: 7}\n+        self._implicit_in_regs = {0: 7, 1: 7}\n+        self._implicit_out_regs = {0: 7, 1: 7, 3: 7, 2: 7}\n         self.isa_extensions = frozenset([peachpy.x86_64.isa.cpuid])\n         if peachpy.stream.active_stream is not None:\n             peachpy.stream.active_stream.add_instruction(self)\n \n \n class RDTSC(Instruction):\n     \"\"\"Read Time-Stamp Counter\"\"\"\n@@ -10066,15 +10066,15 @@\n         if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n             origin = inspect.stack()\n         super(RDTSCP, self).__init__(\"RDTSCP\", origin=origin, prototype=prototype)\n         self.operands = tuple(map(check_operand, args))\n         if len(self.operands) != 0:\n             raise SyntaxError(\"Instruction \\\"RDTSCP\\\" requires 0 operands\")\n         self.encodings.append((0x00, lambda op: bytearray([0x0F, 0x01, 0xF9])))\n-        self._implicit_out_regs = {1: 7, 0: 7, 2: 7}\n+        self._implicit_out_regs = {0: 7, 1: 7, 2: 7}\n         self.isa_extensions = frozenset([peachpy.x86_64.isa.rdtscp])\n         if peachpy.stream.active_stream is not None:\n             peachpy.stream.active_stream.add_instruction(self)\n \n \n class XGETBV(Instruction):\n     \"\"\"Get Value of Extended Control Register\"\"\"\n@@ -10499,15 +10499,15 @@\n         super(CMPXCHG8B, self).__init__(\"CMPXCHG8B\", origin=origin, prototype=prototype)\n         self.operands = tuple(map(check_operand, args))\n         if len(self.operands) != 1:\n             raise SyntaxError(\"Instruction \\\"CMPXCHG8B\\\" requires 1 operands\")\n         if is_m64(self.operands[0]):\n             self.go_name = \"CMPXCHG8B\"\n             self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0x0F, 0xC7]) + modrm_sib_disp(1, op[0].address, sib, min_disp)))\n-            self._implicit_in_regs = {1: 7, 0: 7, 3: 7, 2: 7}\n+            self._implicit_in_regs = {0: 7, 1: 7, 3: 7, 2: 7}\n             self._implicit_out_regs = {0: 7, 2: 7}\n             self.in_regs = (True,)\n             self.out_regs = (False,)\n             self.out_operands = (False,)\n         else:\n             raise SyntaxError(\"Invalid operand types: CMPXCHG8B \" + \", \".join(map(format_operand_type, self.operands)))\n         if peachpy.stream.active_stream is not None:\n@@ -10529,15 +10529,15 @@\n             origin = inspect.stack()\n         super(CMPXCHG16B, self).__init__(\"CMPXCHG16B\", origin=origin, prototype=prototype)\n         self.operands = tuple(map(check_operand, args))\n         if len(self.operands) != 1:\n             raise SyntaxError(\"Instruction \\\"CMPXCHG16B\\\" requires 1 operands\")\n         if is_m128(self.operands[0]):\n             self.encodings.append((0x10, lambda op, sib=False, min_disp=0: rex(1, 0, op[0].address) + bytearray([0x0F, 0xC7]) + modrm_sib_disp(1, op[0].address, sib, min_disp)))\n-            self._implicit_in_regs = {1: 15, 3: 15, 2: 15, 0: 15}\n+            self._implicit_in_regs = {3: 15, 1: 15, 2: 15, 0: 15}\n             self._implicit_out_regs = {2: 15, 0: 15}\n             self.in_regs = (True,)\n             self.out_regs = (False,)\n             self.out_operands = (False,)\n         else:\n             raise SyntaxError(\"Invalid operand types: CMPXCHG16B \" + \", \".join(map(format_operand_type, self.operands)))\n         if peachpy.stream.active_stream is not None:\n"}]}]}]}]}