{"diffoscope-json-version": 1, "source1": "/srv/reproducible-results/rbuild-debian/tmp.2oUjXLWg0N/b1/python-peachpy_0.0~git20200303.f189ad2-2_amd64.changes", "source2": "/srv/reproducible-results/rbuild-debian/tmp.2oUjXLWg0N/b2/python-peachpy_0.0~git20200303.f189ad2-2_amd64.changes", "unified_diff": null, "details": [{"source1": "Files", "source2": "Files", "unified_diff": "@@ -1,3 +1,3 @@\n \n- 3525e21f46169a19ac65bb6cd953a7d5 53852 doc optional python-peachpy-doc_0.0~git20200303.f189ad2-2_all.deb\n- 50048fa5de7417286e6a456c06d61d6b 193036 python optional python3-peachpy_0.0~git20200303.f189ad2-2_amd64.deb\n+ 63c58bd23a296953de250d166b3486f9 53860 doc optional python-peachpy-doc_0.0~git20200303.f189ad2-2_all.deb\n+ 988a0872cfc9b2a68c93533358d70673 193012 python optional python3-peachpy_0.0~git20200303.f189ad2-2_amd64.deb\n"}, {"source1": "python-peachpy-doc_0.0~git20200303.f189ad2-2_all.deb", "source2": "python-peachpy-doc_0.0~git20200303.f189ad2-2_all.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2020-05-01 01:33:46.000000 debian-binary\n -rw-r--r-- 0 0 0 1212 2020-05-01 01:33:46.000000 control.tar.xz\n--rw-r--r-- 0 0 0 52448 2020-05-01 01:33:46.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 52456 2020-05-01 01:33:46.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "./usr/share/doc/python3-peachpy/html/peachpy.html", "source2": "./usr/share/doc/python3-peachpy/html/peachpy.html", "unified_diff": "@@ -8674,29 +8674,29 @@\n \n
\n
\n class peachpy.x86_64.avx.VPBROADCASTMB2Q(*args, **kwargs)\u00b6
\n

Broadcast Low Byte of Mask Register to Packed Quadword Values

\n

Supported forms:

\n \n
\n \n
\n
\n class peachpy.x86_64.avx.VPBROADCASTMW2D(*args, **kwargs)\u00b6
\n

Broadcast Low Word of Mask Register to Packed Doubleword Values

\n

Supported forms:

\n \n
\n \n
\n
\n class peachpy.x86_64.avx.VPBROADCASTQ(*args, **kwargs)\u00b6
\n

Broadcast Quadword Integer

\n@@ -9034,35 +9034,35 @@\n \n
\n
\n class peachpy.x86_64.avx.VPCONFLICTD(*args, **kwargs)\u00b6
\n

Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register

\n

Supported forms:

\n
    \n-

  • VPCONFLICTD(zmm{k}{z}, m512/m32bcst) [AVX512CD]

    • \n-

  • VPCONFLICTD(zmm{k}{z}, zmm) [AVX512CD]

    • \n

  • VPCONFLICTD(xmm{k}{z}, m128/m32bcst) [AVX512VL and AVX512CD]

    • \n

  • VPCONFLICTD(ymm{k}{z}, m256/m32bcst) [AVX512VL and AVX512CD]

    • \n

  • VPCONFLICTD(xmm{k}{z}, xmm) [AVX512VL and AVX512CD]

    • \n

  • VPCONFLICTD(ymm{k}{z}, ymm) [AVX512VL and AVX512CD]

    • \n+

  • VPCONFLICTD(zmm{k}{z}, m512/m32bcst) [AVX512CD]

    • \n+

  • VPCONFLICTD(zmm{k}{z}, zmm) [AVX512CD]

    • \n
\n
\n \n
\n
\n class peachpy.x86_64.avx.VPCONFLICTQ(*args, **kwargs)\u00b6
\n

Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register

\n

Supported forms:

\n
    \n-

  • VPCONFLICTQ(zmm{k}{z}, m512/m64bcst) [AVX512CD]

    • \n-

  • VPCONFLICTQ(zmm{k}{z}, zmm) [AVX512CD]

    • \n

  • VPCONFLICTQ(xmm{k}{z}, m128/m64bcst) [AVX512VL and AVX512CD]

    • \n

  • VPCONFLICTQ(ymm{k}{z}, m256/m64bcst) [AVX512VL and AVX512CD]

    • \n

  • VPCONFLICTQ(xmm{k}{z}, xmm) [AVX512VL and AVX512CD]

    • \n

  • VPCONFLICTQ(ymm{k}{z}, ymm) [AVX512VL and AVX512CD]

    • \n+

  • VPCONFLICTQ(zmm{k}{z}, m512/m64bcst) [AVX512CD]

    • \n+

  • VPCONFLICTQ(zmm{k}{z}, zmm) [AVX512CD]

    • \n
\n
\n \n
\n
\n class peachpy.x86_64.avx.VPERM2F128(*args, **kwargs)\u00b6
\n

Permute Floating-Point Values

\n@@ -9084,17 +9084,17 @@\n \n
\n
\n class peachpy.x86_64.avx.VPERMB(*args, **kwargs)\u00b6
\n

Permute Byte Integers

\n

Supported forms:

\n
    \n+

  • VPERMB(zmm{k}{z}, zmm, zmm/m512) [AVX512VBMI]

    • \n

  • VPERMB(xmm{k}{z}, xmm, xmm/m128) [AVX512VL and AVX512VBMI]

    • \n

  • VPERMB(ymm{k}{z}, ymm, ymm/m256) [AVX512VL and AVX512VBMI]

    • \n-

  • VPERMB(zmm{k}{z}, zmm, zmm/m512) [AVX512VBMI]

    • \n
\n
\n \n
\n
\n class peachpy.x86_64.avx.VPERMD(*args, **kwargs)\u00b6
\n

Permute Doubleword Integers

\n@@ -9110,17 +9110,17 @@\n \n
\n
\n class peachpy.x86_64.avx.VPERMI2B(*args, **kwargs)\u00b6
\n

Full Permute of Bytes From Two Tables Overwriting the Index

\n

Supported forms:

\n
    \n+

  • VPERMI2B(zmm{k}{z}, zmm, zmm/m512) [AVX512VBMI]

    • \n

  • VPERMI2B(xmm{k}{z}, xmm, xmm/m128) [AVX512VL and AVX512VBMI]

    • \n

  • VPERMI2B(ymm{k}{z}, ymm, ymm/m256) [AVX512VL and AVX512VBMI]

    • \n-

  • VPERMI2B(zmm{k}{z}, zmm, zmm/m512) [AVX512VBMI]

    • \n
\n
\n \n
\n
\n class peachpy.x86_64.avx.VPERMI2D(*args, **kwargs)\u00b6
\n

Full Permute of Doublewords From Two Tables Overwriting the Index

\n@@ -9294,17 +9294,17 @@\n \n
\n
\n class peachpy.x86_64.avx.VPERMT2B(*args, **kwargs)\u00b6
\n

Full Permute of Bytes From Two Tables Overwriting a Table

\n

Supported forms:

\n
    \n+

  • VPERMT2B(zmm{k}{z}, zmm, zmm/m512) [AVX512VBMI]

    • \n

  • VPERMT2B(xmm{k}{z}, xmm, xmm/m128) [AVX512VL and AVX512VBMI]

    • \n

  • VPERMT2B(ymm{k}{z}, ymm, ymm/m256) [AVX512VL and AVX512VBMI]

    • \n-

  • VPERMT2B(zmm{k}{z}, zmm, zmm/m512) [AVX512VBMI]

    • \n
\n
\n \n
\n
\n class peachpy.x86_64.avx.VPERMT2D(*args, **kwargs)\u00b6
\n

Full Permute of Doublewords From Two Tables Overwriting a Table

\n@@ -9642,35 +9642,35 @@\n \n
\n
\n class peachpy.x86_64.avx.VPLZCNTD(*args, **kwargs)\u00b6
\n

Count the Number of Leading Zero Bits for Packed Doubleword Values

\n

Supported forms:

\n
    \n-

  • VPLZCNTD(zmm{k}{z}, m512/m32bcst) [AVX512CD]

    • \n-

  • VPLZCNTD(zmm{k}{z}, zmm) [AVX512CD]

    • \n

  • VPLZCNTD(xmm{k}{z}, m128/m32bcst) [AVX512VL and AVX512CD]

    • \n

  • VPLZCNTD(ymm{k}{z}, m256/m32bcst) [AVX512VL and AVX512CD]

    • \n

  • VPLZCNTD(xmm{k}{z}, xmm) [AVX512VL and AVX512CD]

    • \n

  • VPLZCNTD(ymm{k}{z}, ymm) [AVX512VL and AVX512CD]

    • \n+

  • VPLZCNTD(zmm{k}{z}, m512/m32bcst) [AVX512CD]

    • \n+

  • VPLZCNTD(zmm{k}{z}, zmm) [AVX512CD]

    • \n
\n
\n \n
\n
\n class peachpy.x86_64.avx.VPLZCNTQ(*args, **kwargs)\u00b6
\n

Count the Number of Leading Zero Bits for Packed Quadword Values

\n

Supported forms:

\n
    \n-

  • VPLZCNTQ(zmm{k}{z}, m512/m64bcst) [AVX512CD]

    • \n-

  • VPLZCNTQ(zmm{k}{z}, zmm) [AVX512CD]

    • \n

  • VPLZCNTQ(xmm{k}{z}, m128/m64bcst) [AVX512VL and AVX512CD]

    • \n

  • VPLZCNTQ(ymm{k}{z}, m256/m64bcst) [AVX512VL and AVX512CD]

    • \n

  • VPLZCNTQ(xmm{k}{z}, xmm) [AVX512VL and AVX512CD]

    • \n

  • VPLZCNTQ(ymm{k}{z}, ymm) [AVX512VL and AVX512CD]

    • \n+

  • VPLZCNTQ(zmm{k}{z}, m512/m64bcst) [AVX512CD]

    • \n+

  • VPLZCNTQ(zmm{k}{z}, zmm) [AVX512CD]

    • \n
\n
\n \n
\n
\n class peachpy.x86_64.avx.VPMADD52HUQ(*args, **kwargs)\u00b6
\n

Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators

\n@@ -10646,20 +10646,20 @@\n \n
\n
\n class peachpy.x86_64.avx.VPMULTISHIFTQB(*args, **kwargs)\u00b6
\n

Select Packed Unaligned Bytes from Quadword Sources

\n

Supported forms:

\n
    \n+

  • VPMULTISHIFTQB(zmm{k}{z}, zmm, m512/m64bcst) [AVX512VBMI]

    • \n+

  • VPMULTISHIFTQB(zmm{k}{z}, zmm, zmm) [AVX512VBMI]

    • \n

  • VPMULTISHIFTQB(xmm{k}{z}, xmm, m128/m64bcst) [AVX512VL and AVX512VBMI]

    • \n

  • VPMULTISHIFTQB(xmm{k}{z}, xmm, xmm) [AVX512VL and AVX512VBMI]

    • \n

  • VPMULTISHIFTQB(ymm{k}{z}, ymm, m256/m64bcst) [AVX512VL and AVX512VBMI]

    • \n

  • VPMULTISHIFTQB(ymm{k}{z}, ymm, ymm) [AVX512VL and AVX512VBMI]

    • \n-

  • VPMULTISHIFTQB(zmm{k}{z}, zmm, m512/m64bcst) [AVX512VBMI]

    • \n-

  • VPMULTISHIFTQB(zmm{k}{z}, zmm, zmm) [AVX512VBMI]

    • \n
\n
\n \n
\n
\n class peachpy.x86_64.avx.VPMULUDQ(*args, **kwargs)\u00b6
\n

Multiply Packed Unsigned Doubleword Integers

\n"}]}]}]}, {"source1": "python3-peachpy_0.0~git20200303.f189ad2-2_amd64.deb", "source2": "python3-peachpy_0.0~git20200303.f189ad2-2_amd64.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2020-05-01 01:33:46.000000 debian-binary\n--rw-r--r-- 0 0 0 3168 2020-05-01 01:33:46.000000 control.tar.xz\n--rw-r--r-- 0 0 0 189676 2020-05-01 01:33:46.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 3164 2020-05-01 01:33:46.000000 control.tar.xz\n+-rw-r--r-- 0 0 0 189656 2020-05-01 01:33:46.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "./usr/lib/python3/dist-packages/peachpy/x86_64/avx.py", "source2": "./usr/lib/python3/dist-packages/peachpy/x86_64/avx.py", "unified_diff": "@@ -14083,20 +14083,20 @@\n \n class VPCONFLICTD(Instruction):\n \"\"\"Detect Conflicts Within a Vector of Packed Doubleword Values into Dense Memory/Register\"\"\"\n \n def __init__(self, *args, **kwargs):\n \"\"\"Supported forms:\n \n- * VPCONFLICTD(zmm{k}{z}, m512/m32bcst) [AVX512CD]\n- * VPCONFLICTD(zmm{k}{z}, zmm) [AVX512CD]\n * VPCONFLICTD(xmm{k}{z}, m128/m32bcst) [AVX512VL and AVX512CD]\n * VPCONFLICTD(ymm{k}{z}, m256/m32bcst) [AVX512VL and AVX512CD]\n * VPCONFLICTD(xmm{k}{z}, xmm) [AVX512VL and AVX512CD]\n * VPCONFLICTD(ymm{k}{z}, ymm) [AVX512VL and AVX512CD]\n+ * VPCONFLICTD(zmm{k}{z}, m512/m32bcst) [AVX512CD]\n+ * VPCONFLICTD(zmm{k}{z}, zmm) [AVX512CD]\n \"\"\"\n \n origin = kwargs.get(\"origin\")\n prototype = kwargs.get(\"prototype\")\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(VPCONFLICTD, self).__init__(\"VPCONFLICTD\", origin=origin, prototype=prototype)\n@@ -14133,20 +14133,20 @@\n \n class VPCONFLICTQ(Instruction):\n \"\"\"Detect Conflicts Within a Vector of Packed Quadword Values into Dense Memory/Register\"\"\"\n \n def __init__(self, *args, **kwargs):\n \"\"\"Supported forms:\n \n- * VPCONFLICTQ(zmm{k}{z}, m512/m64bcst) [AVX512CD]\n- * VPCONFLICTQ(zmm{k}{z}, zmm) [AVX512CD]\n * VPCONFLICTQ(xmm{k}{z}, m128/m64bcst) [AVX512VL and AVX512CD]\n * VPCONFLICTQ(ymm{k}{z}, m256/m64bcst) [AVX512VL and AVX512CD]\n * VPCONFLICTQ(xmm{k}{z}, xmm) [AVX512VL and AVX512CD]\n * VPCONFLICTQ(ymm{k}{z}, ymm) [AVX512VL and AVX512CD]\n+ * VPCONFLICTQ(zmm{k}{z}, m512/m64bcst) [AVX512CD]\n+ * VPCONFLICTQ(zmm{k}{z}, zmm) [AVX512CD]\n \"\"\"\n \n origin = kwargs.get(\"origin\")\n prototype = kwargs.get(\"prototype\")\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(VPCONFLICTQ, self).__init__(\"VPCONFLICTQ\", origin=origin, prototype=prototype)\n@@ -14183,20 +14183,20 @@\n \n class VPLZCNTD(Instruction):\n \"\"\"Count the Number of Leading Zero Bits for Packed Doubleword Values\"\"\"\n \n def __init__(self, *args, **kwargs):\n \"\"\"Supported forms:\n \n- * VPLZCNTD(zmm{k}{z}, m512/m32bcst) [AVX512CD]\n- * VPLZCNTD(zmm{k}{z}, zmm) [AVX512CD]\n * VPLZCNTD(xmm{k}{z}, m128/m32bcst) [AVX512VL and AVX512CD]\n * VPLZCNTD(ymm{k}{z}, m256/m32bcst) [AVX512VL and AVX512CD]\n * VPLZCNTD(xmm{k}{z}, xmm) [AVX512VL and AVX512CD]\n * VPLZCNTD(ymm{k}{z}, ymm) [AVX512VL and AVX512CD]\n+ * VPLZCNTD(zmm{k}{z}, m512/m32bcst) [AVX512CD]\n+ * VPLZCNTD(zmm{k}{z}, zmm) [AVX512CD]\n \"\"\"\n \n origin = kwargs.get(\"origin\")\n prototype = kwargs.get(\"prototype\")\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(VPLZCNTD, self).__init__(\"VPLZCNTD\", origin=origin, prototype=prototype)\n@@ -14233,20 +14233,20 @@\n \n class VPLZCNTQ(Instruction):\n \"\"\"Count the Number of Leading Zero Bits for Packed Quadword Values\"\"\"\n \n def __init__(self, *args, **kwargs):\n \"\"\"Supported forms:\n \n- * VPLZCNTQ(zmm{k}{z}, m512/m64bcst) [AVX512CD]\n- * VPLZCNTQ(zmm{k}{z}, zmm) [AVX512CD]\n * VPLZCNTQ(xmm{k}{z}, m128/m64bcst) [AVX512VL and AVX512CD]\n * VPLZCNTQ(ymm{k}{z}, m256/m64bcst) [AVX512VL and AVX512CD]\n * VPLZCNTQ(xmm{k}{z}, xmm) [AVX512VL and AVX512CD]\n * VPLZCNTQ(ymm{k}{z}, ymm) [AVX512VL and AVX512CD]\n+ * VPLZCNTQ(zmm{k}{z}, m512/m64bcst) [AVX512CD]\n+ * VPLZCNTQ(zmm{k}{z}, zmm) [AVX512CD]\n \"\"\"\n \n origin = kwargs.get(\"origin\")\n prototype = kwargs.get(\"prototype\")\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(VPLZCNTQ, self).__init__(\"VPLZCNTQ\", origin=origin, prototype=prototype)\n@@ -19232,20 +19232,20 @@\n \n class VPMADD52LUQ(Instruction):\n \"\"\"Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators\"\"\"\n \n def __init__(self, *args, **kwargs):\n \"\"\"Supported forms:\n \n- * VPMADD52LUQ(zmm{k}{z}, zmm, m512/m64bcst) [AVX512IFMA]\n- * VPMADD52LUQ(zmm{k}{z}, zmm, zmm) [AVX512IFMA]\n * VPMADD52LUQ(xmm{k}{z}, xmm, m128/m64bcst) [AVX512VL and AVX512IFMA]\n * VPMADD52LUQ(xmm{k}{z}, xmm, xmm) [AVX512VL and AVX512IFMA]\n * VPMADD52LUQ(ymm{k}{z}, ymm, m256/m64bcst) [AVX512VL and AVX512IFMA]\n * VPMADD52LUQ(ymm{k}{z}, ymm, ymm) [AVX512VL and AVX512IFMA]\n+ * VPMADD52LUQ(zmm{k}{z}, zmm, m512/m64bcst) [AVX512IFMA]\n+ * VPMADD52LUQ(zmm{k}{z}, zmm, zmm) [AVX512IFMA]\n \"\"\"\n \n origin = kwargs.get(\"origin\")\n prototype = kwargs.get(\"prototype\")\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(VPMADD52LUQ, self).__init__(\"VPMADD52LUQ\", origin=origin, prototype=prototype)\n@@ -19282,20 +19282,20 @@\n \n class VPMADD52HUQ(Instruction):\n \"\"\"Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators\"\"\"\n \n def __init__(self, *args, **kwargs):\n \"\"\"Supported forms:\n \n- * VPMADD52HUQ(zmm{k}{z}, zmm, m512/m64bcst) [AVX512IFMA]\n- * VPMADD52HUQ(zmm{k}{z}, zmm, zmm) [AVX512IFMA]\n * VPMADD52HUQ(xmm{k}{z}, xmm, m128/m64bcst) [AVX512VL and AVX512IFMA]\n * VPMADD52HUQ(xmm{k}{z}, xmm, xmm) [AVX512VL and AVX512IFMA]\n * VPMADD52HUQ(ymm{k}{z}, ymm, m256/m64bcst) [AVX512VL and AVX512IFMA]\n * VPMADD52HUQ(ymm{k}{z}, ymm, ymm) [AVX512VL and AVX512IFMA]\n+ * VPMADD52HUQ(zmm{k}{z}, zmm, m512/m64bcst) [AVX512IFMA]\n+ * VPMADD52HUQ(zmm{k}{z}, zmm, zmm) [AVX512IFMA]\n \"\"\"\n \n origin = kwargs.get(\"origin\")\n prototype = kwargs.get(\"prototype\")\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(VPMADD52HUQ, self).__init__(\"VPMADD52HUQ\", origin=origin, prototype=prototype)\n@@ -24211,21 +24211,21 @@\n self.out_operands = (False, False, False)\n self.avx_mode = True\n self.isa_extensions = frozenset([peachpy.x86_64.isa.avx])\n if is_xmm(self.operands[0]) and is_xmm(self.operands[1]) and is_imm(self.operands[2]):\n if not is_imm8(self.operands[2]):\n raise ValueError(\"Argument #2 can not be encoded as imm8\")\n self.encodings.append((0x00, lambda op: bytearray([0xC4, 0xE3 ^ (op[0].hcode << 7) ^ (op[1].hcode << 5), 0x79, 0x61, 0xC0 | op[0].lcode << 3 | op[1].lcode, op[2] & 0xFF])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n self._implicit_out_regs = {1: 7}\n elif is_xmm(self.operands[0]) and is_m128(self.operands[1]) and is_imm(self.operands[2]):\n if not is_imm8(self.operands[2]):\n raise ValueError(\"Argument #2 can not be encoded as imm8\")\n self.encodings.append((0x10, lambda op, sib=False, min_disp=0: vex3(0xC4, 0b11, 0x01, op[0].hcode, op[1].address) + bytearray([0x61]) + modrm_sib_disp(op[0].lcode, op[1].address, sib, min_disp) + bytearray([op[2] & 0xFF])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n self._implicit_out_regs = {1: 7}\n else:\n raise SyntaxError(\"Invalid operand types: VPCMPESTRI \" + \", \".join(map(format_operand_type, self.operands)))\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n@@ -24251,21 +24251,21 @@\n self.out_operands = (False, False, False)\n self.avx_mode = True\n self.isa_extensions = frozenset([peachpy.x86_64.isa.avx])\n if is_xmm(self.operands[0]) and is_xmm(self.operands[1]) and is_imm(self.operands[2]):\n if not is_imm8(self.operands[2]):\n raise ValueError(\"Argument #2 can not be encoded as imm8\")\n self.encodings.append((0x00, lambda op: bytearray([0xC4, 0xE3 ^ (op[0].hcode << 7) ^ (op[1].hcode << 5), 0x79, 0x60, 0xC0 | op[0].lcode << 3 | op[1].lcode, op[2] & 0xFF])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n self._implicit_out_regs = {0: 256}\n elif is_xmm(self.operands[0]) and is_m128(self.operands[1]) and is_imm(self.operands[2]):\n if not is_imm8(self.operands[2]):\n raise ValueError(\"Argument #2 can not be encoded as imm8\")\n self.encodings.append((0x10, lambda op, sib=False, min_disp=0: vex3(0xC4, 0b11, 0x01, op[0].hcode, op[1].address) + bytearray([0x60]) + modrm_sib_disp(op[0].lcode, op[1].address, sib, min_disp) + bytearray([op[2] & 0xFF])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n self._implicit_out_regs = {0: 256}\n else:\n raise SyntaxError(\"Invalid operand types: VPCMPESTRM \" + \", \".join(map(format_operand_type, self.operands)))\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n@@ -28903,17 +28903,17 @@\n \n class VPBROADCASTMB2Q(Instruction):\n \"\"\"Broadcast Low Byte of Mask Register to Packed Quadword Values\"\"\"\n \n def __init__(self, *args, **kwargs):\n \"\"\"Supported forms:\n \n- * VPBROADCASTMB2Q(zmm, k) [AVX512CD]\n * VPBROADCASTMB2Q(xmm, k) [AVX512VL and AVX512CD]\n * VPBROADCASTMB2Q(ymm, k) [AVX512VL and AVX512CD]\n+ * VPBROADCASTMB2Q(zmm, k) [AVX512CD]\n \"\"\"\n \n origin = kwargs.get(\"origin\")\n prototype = kwargs.get(\"prototype\")\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(VPBROADCASTMB2Q, self).__init__(\"VPBROADCASTMB2Q\", origin=origin, prototype=prototype)\n@@ -28941,17 +28941,17 @@\n \n class VPBROADCASTMW2D(Instruction):\n \"\"\"Broadcast Low Word of Mask Register to Packed Doubleword Values\"\"\"\n \n def __init__(self, *args, **kwargs):\n \"\"\"Supported forms:\n \n- * VPBROADCASTMW2D(zmm, k) [AVX512CD]\n * VPBROADCASTMW2D(xmm, k) [AVX512VL and AVX512CD]\n * VPBROADCASTMW2D(ymm, k) [AVX512VL and AVX512CD]\n+ * VPBROADCASTMW2D(zmm, k) [AVX512CD]\n \"\"\"\n \n origin = kwargs.get(\"origin\")\n prototype = kwargs.get(\"prototype\")\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(VPBROADCASTMW2D, self).__init__(\"VPBROADCASTMW2D\", origin=origin, prototype=prototype)\n"}, {"source1": "./usr/lib/python3/dist-packages/peachpy/x86_64/generic.py", "source2": "./usr/lib/python3/dist-packages/peachpy/x86_64/generic.py", "unified_diff": "@@ -4960,15 +4960,15 @@\n self._implicit_in_regs = {0: 3}\n self._implicit_out_regs = {0: 3, 2: 3}\n elif is_r32(self.operands[0]):\n self.go_name = \"IMULL\"\n self._gas_name = \"imull\"\n self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex) + bytearray([0xF7, 0xE8 | op[0].lcode])))\n self._implicit_in_regs = {0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n elif is_r64(self.operands[0]):\n self.go_name = \"IMULQ\"\n self._gas_name = \"imulq\"\n self.encodings.append((0x00, lambda op: bytearray([0x48 | op[0].hcode, 0xF7, 0xE8 | op[0].lcode])))\n self._implicit_in_regs = {0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n elif is_m8(self.operands[0]):\n@@ -4984,15 +4984,15 @@\n self._implicit_in_regs = {0: 3}\n self._implicit_out_regs = {0: 3, 2: 3}\n elif is_m32(self.operands[0]):\n self.go_name = \"IMULL\"\n self._gas_name = \"imull\"\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(5, op[0].address, sib, min_disp)))\n self._implicit_in_regs = {0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n elif is_m64(self.operands[0]):\n self.go_name = \"IMULQ\"\n self._gas_name = \"imulq\"\n self.encodings.append((0x10, lambda op, sib=False, min_disp=0: rex(1, 0, op[0].address) + bytearray([0xF7]) + modrm_sib_disp(5, op[0].address, sib, min_disp)))\n self._implicit_in_regs = {0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n else:\n@@ -5119,15 +5119,15 @@\n self._implicit_in_regs = {0: 3}\n self._implicit_out_regs = {0: 3, 2: 3}\n elif is_r32(self.operands[0]):\n self.go_name = \"MULL\"\n self._gas_name = \"mull\"\n self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex) + bytearray([0xF7, 0xE0 | op[0].lcode])))\n self._implicit_in_regs = {0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n elif is_r64(self.operands[0]):\n self.go_name = \"MULQ\"\n self._gas_name = \"mulq\"\n self.encodings.append((0x00, lambda op: bytearray([0x48 | op[0].hcode, 0xF7, 0xE0 | op[0].lcode])))\n self._implicit_in_regs = {0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n elif is_m8(self.operands[0]):\n@@ -5143,15 +5143,15 @@\n self._implicit_in_regs = {0: 3}\n self._implicit_out_regs = {0: 3, 2: 3}\n elif is_m32(self.operands[0]):\n self.go_name = \"MULL\"\n self._gas_name = \"mull\"\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(4, op[0].address, sib, min_disp)))\n self._implicit_in_regs = {0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n elif is_m64(self.operands[0]):\n self.go_name = \"MULQ\"\n self._gas_name = \"mulq\"\n self.encodings.append((0x10, lambda op, sib=False, min_disp=0: rex(1, 0, op[0].address) + bytearray([0xF7]) + modrm_sib_disp(4, op[0].address, sib, min_disp)))\n self._implicit_in_regs = {0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n else:\n@@ -5239,16 +5239,16 @@\n self.encodings.append((0x20, lambda op, rex=False: bytearray([0x66]) + optional_rex(0, op[0], rex) + bytearray([0xF7, 0xF8 | op[0].lcode])))\n self._implicit_in_regs = {0: 3, 2: 3}\n self._implicit_out_regs = {0: 3, 2: 3}\n elif is_r32(self.operands[0]):\n self.go_name = \"IDIVL\"\n self._gas_name = \"idivl\"\n self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex) + bytearray([0xF7, 0xF8 | op[0].lcode])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n elif is_r64(self.operands[0]):\n self.go_name = \"IDIVQ\"\n self._gas_name = \"idivq\"\n self.encodings.append((0x00, lambda op: bytearray([0x48 | op[0].hcode, 0xF7, 0xF8 | op[0].lcode])))\n self._implicit_in_regs = {2: 15, 0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n elif is_m8(self.operands[0]):\n@@ -5263,16 +5263,16 @@\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: bytearray([0x66]) + optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(7, op[0].address, sib, min_disp)))\n self._implicit_in_regs = {0: 3, 2: 3}\n self._implicit_out_regs = {0: 3, 2: 3}\n elif is_m32(self.operands[0]):\n self.go_name = \"IDIVL\"\n self._gas_name = \"idivl\"\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(7, op[0].address, sib, min_disp)))\n- self._implicit_in_regs = {2: 7, 0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n elif is_m64(self.operands[0]):\n self.go_name = \"IDIVQ\"\n self._gas_name = \"idivq\"\n self.encodings.append((0x10, lambda op, sib=False, min_disp=0: rex(1, 0, op[0].address) + bytearray([0xF7]) + modrm_sib_disp(7, op[0].address, sib, min_disp)))\n self._implicit_in_regs = {2: 15, 0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n else:\n@@ -5316,16 +5316,16 @@\n self.encodings.append((0x20, lambda op, rex=False: bytearray([0x66]) + optional_rex(0, op[0], rex) + bytearray([0xF7, 0xF0 | op[0].lcode])))\n self._implicit_in_regs = {0: 3, 2: 3}\n self._implicit_out_regs = {0: 3, 2: 3}\n elif is_r32(self.operands[0]):\n self.go_name = \"DIVL\"\n self._gas_name = \"divl\"\n self.encodings.append((0x20, lambda op, rex=False: optional_rex(0, op[0], rex) + bytearray([0xF7, 0xF0 | op[0].lcode])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n elif is_r64(self.operands[0]):\n self.go_name = \"DIVQ\"\n self._gas_name = \"divq\"\n self.encodings.append((0x00, lambda op: bytearray([0x48 | op[0].hcode, 0xF7, 0xF0 | op[0].lcode])))\n self._implicit_in_regs = {2: 15, 0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n elif is_m8(self.operands[0]):\n@@ -5340,16 +5340,16 @@\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: bytearray([0x66]) + optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(6, op[0].address, sib, min_disp)))\n self._implicit_in_regs = {0: 3, 2: 3}\n self._implicit_out_regs = {0: 3, 2: 3}\n elif is_m32(self.operands[0]):\n self.go_name = \"DIVL\"\n self._gas_name = \"divl\"\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0xF7]) + modrm_sib_disp(6, op[0].address, sib, min_disp)))\n- self._implicit_in_regs = {2: 7, 0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n elif is_m64(self.operands[0]):\n self.go_name = \"DIVQ\"\n self._gas_name = \"divq\"\n self.encodings.append((0x10, lambda op, sib=False, min_disp=0: rex(1, 0, op[0].address) + bytearray([0xF7]) + modrm_sib_disp(6, op[0].address, sib, min_disp)))\n self._implicit_in_regs = {2: 15, 0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n else:\n@@ -10016,16 +10016,16 @@\n origin = inspect.stack()\n super(CPUID, self).__init__(\"CPUID\", origin=origin, prototype=prototype)\n self.operands = tuple(map(check_operand, args))\n if len(self.operands) != 0:\n raise SyntaxError(\"Instruction \\\"CPUID\\\" requires 0 operands\")\n self.go_name = \"CPUID\"\n self.encodings.append((0x00, lambda op: bytearray([0x0F, 0xA2])))\n- self._implicit_in_regs = {1: 7, 0: 7}\n- self._implicit_out_regs = {1: 7, 2: 7, 3: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 1: 7}\n+ self._implicit_out_regs = {0: 7, 1: 7, 3: 7, 2: 7}\n self.isa_extensions = frozenset([peachpy.x86_64.isa.cpuid])\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n class RDTSC(Instruction):\n \"\"\"Read Time-Stamp Counter\"\"\"\n@@ -10042,15 +10042,15 @@\n origin = inspect.stack()\n super(RDTSC, self).__init__(\"RDTSC\", origin=origin, prototype=prototype)\n self.operands = tuple(map(check_operand, args))\n if len(self.operands) != 0:\n raise SyntaxError(\"Instruction \\\"RDTSC\\\" requires 0 operands\")\n self.go_name = \"RDTSC\"\n self.encodings.append((0x00, lambda op: bytearray([0x0F, 0x31])))\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n self.isa_extensions = frozenset([peachpy.x86_64.isa.rdtsc])\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n class RDTSCP(Instruction):\n \"\"\"Read Time-Stamp Counter and Processor ID\"\"\"\n@@ -10066,15 +10066,15 @@\n if origin is None and prototype is None and peachpy.x86_64.options.get_debug_level() > 0:\n origin = inspect.stack()\n super(RDTSCP, self).__init__(\"RDTSCP\", origin=origin, prototype=prototype)\n self.operands = tuple(map(check_operand, args))\n if len(self.operands) != 0:\n raise SyntaxError(\"Instruction \\\"RDTSCP\\\" requires 0 operands\")\n self.encodings.append((0x00, lambda op: bytearray([0x0F, 0x01, 0xF9])))\n- self._implicit_out_regs = {1: 7, 2: 7, 0: 7}\n+ self._implicit_out_regs = {0: 7, 1: 7, 2: 7}\n self.isa_extensions = frozenset([peachpy.x86_64.isa.rdtscp])\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n class XGETBV(Instruction):\n \"\"\"Get Value of Extended Control Register\"\"\"\n@@ -10091,15 +10091,15 @@\n origin = inspect.stack()\n super(XGETBV, self).__init__(\"XGETBV\", origin=origin, prototype=prototype)\n self.operands = tuple(map(check_operand, args))\n if len(self.operands) != 0:\n raise SyntaxError(\"Instruction \\\"XGETBV\\\" requires 0 operands\")\n self.encodings.append((0x00, lambda op: bytearray([0x0F, 0x01, 0xD0])))\n self._implicit_in_regs = {1: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n class SYSCALL(Instruction):\n \"\"\"Fast System Call\"\"\"\n \n@@ -10115,15 +10115,15 @@\n origin = inspect.stack()\n super(SYSCALL, self).__init__(\"SYSCALL\", origin=origin, prototype=prototype)\n self.operands = tuple(map(check_operand, args))\n if len(self.operands) != 0:\n raise SyntaxError(\"Instruction \\\"SYSCALL\\\" requires 0 operands\")\n self.go_name = \"SYSCALL\"\n self.encodings.append((0x00, lambda op: bytearray([0x0F, 0x05])))\n- self._implicit_out_regs = {11: 15, 1: 15}\n+ self._implicit_out_regs = {1: 15, 11: 15}\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n class STC(Instruction):\n \"\"\"Set Carry Flag\"\"\"\n \n@@ -10499,16 +10499,16 @@\n super(CMPXCHG8B, self).__init__(\"CMPXCHG8B\", origin=origin, prototype=prototype)\n self.operands = tuple(map(check_operand, args))\n if len(self.operands) != 1:\n raise SyntaxError(\"Instruction \\\"CMPXCHG8B\\\" requires 1 operands\")\n if is_m64(self.operands[0]):\n self.go_name = \"CMPXCHG8B\"\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: optional_rex(0, op[0].address, rex) + bytearray([0x0F, 0xC7]) + modrm_sib_disp(1, op[0].address, sib, min_disp)))\n- self._implicit_in_regs = {1: 7, 2: 7, 3: 7, 0: 7}\n- self._implicit_out_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 1: 7, 3: 7, 2: 7}\n+ self._implicit_out_regs = {0: 7, 2: 7}\n self.in_regs = (True,)\n self.out_regs = (False,)\n self.out_operands = (False,)\n else:\n raise SyntaxError(\"Invalid operand types: CMPXCHG8B \" + \", \".join(map(format_operand_type, self.operands)))\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n@@ -10529,15 +10529,15 @@\n origin = inspect.stack()\n super(CMPXCHG16B, self).__init__(\"CMPXCHG16B\", origin=origin, prototype=prototype)\n self.operands = tuple(map(check_operand, args))\n if len(self.operands) != 1:\n raise SyntaxError(\"Instruction \\\"CMPXCHG16B\\\" requires 1 operands\")\n if is_m128(self.operands[0]):\n self.encodings.append((0x10, lambda op, sib=False, min_disp=0: rex(1, 0, op[0].address) + bytearray([0x0F, 0xC7]) + modrm_sib_disp(1, op[0].address, sib, min_disp)))\n- self._implicit_in_regs = {2: 15, 1: 15, 0: 15, 3: 15}\n+ self._implicit_in_regs = {3: 15, 1: 15, 2: 15, 0: 15}\n self._implicit_out_regs = {2: 15, 0: 15}\n self.in_regs = (True,)\n self.out_regs = (False,)\n self.out_operands = (False,)\n else:\n raise SyntaxError(\"Invalid operand types: CMPXCHG16B \" + \", \".join(map(format_operand_type, self.operands)))\n if peachpy.stream.active_stream is not None:\n"}, {"source1": "./usr/lib/python3/dist-packages/peachpy/x86_64/mmxsse.py", "source2": "./usr/lib/python3/dist-packages/peachpy/x86_64/mmxsse.py", "unified_diff": "@@ -8508,21 +8508,21 @@\n self.out_operands = (False, False, False)\n self.avx_mode = False\n self.isa_extensions = frozenset([peachpy.x86_64.isa.sse4_2])\n if is_xmm(self.operands[0]) and is_xmm(self.operands[1]) and is_imm(self.operands[2]):\n if not is_imm8(self.operands[2]):\n raise ValueError(\"Argument #2 can not be encoded as imm8\")\n self.encodings.append((0x20, lambda op, rex=False: bytearray([0x66]) + optional_rex(op[0].hcode, op[1], rex) + bytearray([0x0F, 0x3A, 0x61, 0xC0 | op[0].lcode << 3 | op[1].lcode, op[2] & 0xFF])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n self._implicit_out_regs = {1: 7}\n elif is_xmm(self.operands[0]) and is_m128(self.operands[1]) and is_imm(self.operands[2]):\n if not is_imm8(self.operands[2]):\n raise ValueError(\"Argument #2 can not be encoded as imm8\")\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: bytearray([0x66]) + optional_rex(op[0].hcode, op[1].address, rex) + bytearray([0x0F, 0x3A, 0x61]) + modrm_sib_disp(op[0].lcode, op[1].address, sib, min_disp) + bytearray([op[2] & 0xFF])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n self._implicit_out_regs = {1: 7}\n else:\n raise SyntaxError(\"Invalid operand types: PCMPESTRI \" + \", \".join(map(format_operand_type, self.operands)))\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n@@ -8548,21 +8548,21 @@\n self.out_operands = (False, False, False)\n self.avx_mode = False\n self.isa_extensions = frozenset([peachpy.x86_64.isa.sse4_2])\n if is_xmm(self.operands[0]) and is_xmm(self.operands[1]) and is_imm(self.operands[2]):\n if not is_imm8(self.operands[2]):\n raise ValueError(\"Argument #2 can not be encoded as imm8\")\n self.encodings.append((0x20, lambda op, rex=False: bytearray([0x66]) + optional_rex(op[0].hcode, op[1], rex) + bytearray([0x0F, 0x3A, 0x60, 0xC0 | op[0].lcode << 3 | op[1].lcode, op[2] & 0xFF])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n self._implicit_out_regs = {0: 256}\n elif is_xmm(self.operands[0]) and is_m128(self.operands[1]) and is_imm(self.operands[2]):\n if not is_imm8(self.operands[2]):\n raise ValueError(\"Argument #2 can not be encoded as imm8\")\n self.encodings.append((0x30, lambda op, rex=False, sib=False, min_disp=0: bytearray([0x66]) + optional_rex(op[0].hcode, op[1].address, rex) + bytearray([0x0F, 0x3A, 0x60]) + modrm_sib_disp(op[0].lcode, op[1].address, sib, min_disp) + bytearray([op[2] & 0xFF])))\n- self._implicit_in_regs = {2: 7, 0: 7}\n+ self._implicit_in_regs = {0: 7, 2: 7}\n self._implicit_out_regs = {0: 256}\n else:\n raise SyntaxError(\"Invalid operand types: PCMPESTRM \" + \", \".join(map(format_operand_type, self.operands)))\n if peachpy.stream.active_stream is not None:\n peachpy.stream.active_stream.add_instruction(self)\n \n \n"}]}]}]}]}