{"diffoscope-json-version": 1, "source1": "/srv/reproducible-results/rbuild-debian/r-b-build.XoahZHoZ/b1/yosys_0.52-1_i386.changes", "source2": "/srv/reproducible-results/rbuild-debian/r-b-build.XoahZHoZ/b2/yosys_0.52-1_i386.changes", "unified_diff": null, "details": [{"source1": "Files", "source2": "Files", "unified_diff": "@@ -1,7 +1,7 @@\n \n 86a12c5265ef432030e39fabd96f0f3d 28731224 debug optional yosys-abc-dbgsym_0.52-1_i386.deb\n 0325c6c46e76d6ec3a6e6d0cdc0baa2c 5020116 electronics optional yosys-abc_0.52-1_i386.deb\n 94c2ab20f62ca0ce1870b5de85dbdbe3 91802040 debug optional yosys-dbgsym_0.52-1_i386.deb\n- e953f16e199c314ec3df186763a066f0 136136 electronics optional yosys-dev_0.52-1_i386.deb\n- ad8a3dfaacec8adc2e92db90289bf470 2916440 doc optional yosys-doc_0.52-1_all.deb\n+ 998620d67d3097e8582080ce9d66982f 136260 electronics optional yosys-dev_0.52-1_i386.deb\n+ 71496bd0c7c9f94b968328c1d60220dc 2917060 doc optional yosys-doc_0.52-1_all.deb\n dee5e80930b9a21ea836bd71dbecdabd 6424884 electronics optional yosys_0.52-1_i386.deb\n"}, {"source1": "yosys-dev_0.52-1_i386.deb", "source2": "yosys-dev_0.52-1_i386.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2025-04-11 08:41:09.000000 debian-binary\n -rw-r--r-- 0 0 0 2308 2025-04-11 08:41:09.000000 control.tar.xz\n--rw-r--r-- 0 0 0 133636 2025-04-11 08:41:09.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 133760 2025-04-11 08:41:09.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,11 +1,11 @@\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/bin/\n--rwxr-xr-x 0 root (0) root (0) 3375 2025-04-11 08:41:09.000000 ./usr/bin/yosys-config\n+-rwxr-xr-x 0 root (0) root (0) 3873 2025-04-11 08:41:09.000000 ./usr/bin/yosys-config\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/doc/\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/doc/yosys-dev/\n -rw-r--r-- 0 root (0) root (0) 2826 2025-04-11 08:41:09.000000 ./usr/share/doc/yosys-dev/changelog.Debian.gz\n -rw-r--r-- 0 root (0) root (0) 18593 2025-04-09 05:38:42.000000 ./usr/share/doc/yosys-dev/changelog.gz\n -rw-r--r-- 0 root (0) root (0) 23806 2025-04-11 08:32:04.000000 ./usr/share/doc/yosys-dev/copyright\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/man/\n"}, {"source1": "./usr/bin/yosys-config", "source2": "./usr/bin/yosys-config", "unified_diff": "@@ -4,15 +4,15 @@\n \t{\n \t\techo \"\"\n \t\techo \"Usage: $0 [--exec] [--prefix pf] args..\"\n \t\techo \" $0 --build modname.so cppsources..\"\n \t\techo \"\"\n \t\techo \"Replacement args:\"\n \t\techo \" --cxx g++\"\n-\t\techo \" --cxxflags $( echo '-g -O2 -flto=auto -ffat-lto-objects -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=' | fmt -w60 | sed ':a;N;$!ba;s/\\n/ \\\\\\n /g' )\"\n+\t\techo \" --cxxflags $( echo '-g -O2 -flto=auto -ffat-lto-objects -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=@CXXFLAGS@.52 -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER' | fmt -w60 | sed ':a;N;$!ba;s/\\n/ \\\\\\n /g' )\"\n \t\techo \" --linkflags -rdynamic\"\n \t\techo \" --ldflags (alias of --linkflags)\"\n \t\techo \" --libs -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6\"\n \t\techo \" --ldlibs (alias of --libs)\"\n \t\techo \" --bindir /usr/bin\"\n \t\techo \" --datdir /usr/share/yosys\"\n \t\techo \"\"\n@@ -60,15 +60,15 @@\n \t\tget_prefix=false\n \t\tcontinue\n \tfi\n \tcase \"$opt\" in\n \t\t\"$prefix\"cxx)\n \t\t\ttokens=( \"${tokens[@]}\" g++ ) ;;\n \t\t\"$prefix\"cxxflags)\n-\t\t\ttokens=( \"${tokens[@]}\" -g -O2 -flto=auto -ffat-lto-objects -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER= ) ;;\n+\t\t\ttokens=( \"${tokens[@]}\" -g -O2 -flto=auto -ffat-lto-objects -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=@CXXFLAGS@.52 -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER ) ;;\n \t\t\"$prefix\"linkflags)\n \t\t\ttokens=( \"${tokens[@]}\" -rdynamic ) ;;\n \t\t\"$prefix\"libs)\n \t\t\ttokens=( \"${tokens[@]}\" -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 ) ;;\n \t\t\"$prefix\"ldflags)\n \t\t\ttokens=( \"${tokens[@]}\" -rdynamic ) ;;\n \t\t\"$prefix\"ldlibs)\n"}]}]}]}, {"source1": "yosys-doc_0.52-1_all.deb", "source2": "yosys-doc_0.52-1_all.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2025-04-11 08:41:09.000000 debian-binary\n -rw-r--r-- 0 0 0 888 2025-04-11 08:41:09.000000 control.tar.xz\n--rw-r--r-- 0 0 0 2915360 2025-04-11 08:41:09.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 2915980 2025-04-11 08:41:09.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./control", "source2": "./control", "unified_diff": "@@ -1,13 +1,13 @@\n Package: yosys-doc\n Source: yosys\n Version: 0.52-1\n Architecture: all\n Maintainer: Debian Electronics Team \n-Installed-Size: 3045\n+Installed-Size: 3046\n Suggests: yosys\n Section: doc\n Priority: optional\n Multi-Arch: foreign\n Homepage: https://github.com/YosysHQ/yosys\n Description: Framework for Verilog RTL synthesis (documentation)\n Yosys is a framework for Verilog RTL synthesis. It currently has extensive\n"}, {"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,13 +1,13 @@\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/doc/\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/doc/yosys/\n--rw-r--r-- 0 root (0) root (0) 3060688 2025-04-11 08:41:09.000000 ./usr/share/doc/yosys/yosyshqyosys.pdf\n+-rw-r--r-- 0 root (0) root (0) 3061202 2025-04-11 08:41:09.000000 ./usr/share/doc/yosys/yosyshqyosys.pdf\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/doc/yosys-doc/\n -rw-r--r-- 0 root (0) root (0) 2827 2025-04-11 08:41:09.000000 ./usr/share/doc/yosys-doc/changelog.Debian.gz\n -rw-r--r-- 0 root (0) root (0) 18593 2025-04-09 05:38:42.000000 ./usr/share/doc/yosys-doc/changelog.gz\n -rw-r--r-- 0 root (0) root (0) 23806 2025-04-11 08:32:04.000000 ./usr/share/doc/yosys-doc/copyright\n drwxr-xr-x 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/doc-base/\n -rw-r--r-- 0 root (0) root (0) 245 2023-08-27 13:27:37.000000 ./usr/share/doc-base/yosys-doc.yosys-manual\n lrwxrwxrwx 0 root (0) root (0) 0 2025-04-11 08:41:09.000000 ./usr/share/doc/yosys/manual.pdf -> yosyshqyosys.pdf\n"}, {"source1": "./usr/share/doc/yosys/yosyshqyosys.pdf", "source2": "./usr/share/doc/yosys/yosyshqyosys.pdf", "unified_diff": null, "details": [{"source1": "pdftotext {} -", "source2": "pdftotext {} -", "unified_diff": "@@ -100,32 +100,32 @@\n 4.2 Internal formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155\n 4.2.1 The RTL Intermediate Language (RTLIL) . . . . . . . . . . . . . . . . . . . . . . . . 156\n 4.3 Working with the Yosys codebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162\n 4.3.1 Writing extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162\n 4.3.2 Compiling with Verific library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171\n 4.3.3 Writing a new backend using FunctionalIR . . . . . . . . . . . . . . . . . . . . . . . . 173\n 4.3.4 Contributing to Yosys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186\n-4.3.5 Testing Yosys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186\n+4.3.5 Testing Yosys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187\n 4.4 Techmap by example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187\n-4.4.1 Mapping OR3X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187\n+4.4.1 Mapping OR3X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188\n 4.4.2 Conditional techmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189\n-4.4.3 Scripting in map modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190\n+4.4.3 Scripting in map modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191\n 4.4.4 Handling constant inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192\n-4.4.5 Handling shorted inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193\n+4.4.5 Handling shorted inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194\n 4.4.6 Notes on using techmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195\n-4.5 Notes on Verilog support in Yosys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195\n-4.5.1 Unsupported Verilog-2005 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195\n-4.5.2 Verilog Attributes and non-standard features . . . . . . . . . . . . . . . . . . . . . . 195\n-4.5.3 Non-standard or SystemVerilog features for formal verification . . . . . . . . . . . . . 199\n+4.5 Notes on Verilog support in Yosys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196\n+4.5.1 Unsupported Verilog-2005 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196\n+4.5.2 Verilog Attributes and non-standard features . . . . . . . . . . . . . . . . . . . . . . 196\n+4.5.3 Non-standard or SystemVerilog features for formal verification . . . . . . . . . . . . . 200\n 4.5.4 Supported features from SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . 200\n-4.6 Hashing and associative data structures in Yosys . . . . . . . . . . . . . . . . . . . . . . . . . 200\n-4.6.1 Container classes based on hashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200\n-4.6.2 The hash function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201\n+4.6 Hashing and associative data structures in Yosys . . . . . . . . . . . . . . . . . . . . . . . . . 201\n+4.6.1 Container classes based on hashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201\n+4.6.2 The hash function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202\n 4.6.3 Making a type hashable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202\n-4.6.4 Porting plugins from the legacy interface . . . . . . . . . . . . . . . . . . . . . . . . . 202\n+4.6.4 Porting plugins from the legacy interface . . . . . . . . . . . . . . . . . . . . . . . . . 203\n \n 5\n \n A primer on digital circuit synthesis\n 205\n 5.1 Levels of abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205\n 5.1.1 System level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206\n@@ -198,372 +198,372 @@\n 8\n \n Auxiliary programs\n 225\n 8.1 yosys-config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225\n 8.2 yosys-filterlib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226\n 8.3 yosys-abc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226\n-8.4 yosys-smtbmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226\n+8.4 yosys-smtbmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227\n 8.5 yosys-witness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230\n \n 9\n \n Internal cell library\n-231\n-9.1 Word-level cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231\n-9.1.1 Unary operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231\n-9.1.2 Binary operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237\n-9.1.3 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257\n-9.1.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261\n-9.1.5 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271\n-9.1.6 Finite state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283\n-9.1.7 Coarse arithmetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285\n-9.1.8 Arbitrary logic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293\n-9.1.9 Specify rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295\n+233\n+9.1 Word-level cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233\n+9.1.1 Unary operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233\n+9.1.2 Binary operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239\n+9.1.3 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259\n+9.1.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263\n+9.1.5 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273\n+9.1.6 Finite state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285\n+9.1.7 Coarse arithmetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287\n+9.1.8 Arbitrary logic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295\n+9.1.9 Specify rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297\n iii\n \n \f9.2\n \n 9.3\n \n-9.1.10 Formal verification cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300\n-9.1.11 Debugging cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306\n-9.1.12 Wire cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309\n-Gate-level cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310\n-9.2.1 Combinatorial cells (simple) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311\n-9.2.2 Combinatorial cells (combined) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315\n-9.2.3 Flip-flop cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321\n-9.2.4 Latch cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375\n-9.2.5 Other gate-level cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\n-Cell properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388\n+9.1.10 Formal verification cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302\n+9.1.11 Debugging cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308\n+9.1.12 Wire cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311\n+Gate-level cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312\n+9.2.1 Combinatorial cells (simple) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313\n+9.2.2 Combinatorial cells (combined) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317\n+9.2.3 Flip-flop cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323\n+9.2.4 Latch cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377\n+9.2.5 Other gate-level cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389\n+Cell properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390\n \n 10 Command line reference\n-389\n-10.1 Yosys environment variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390\n-10.2 abc - use ABC for technology mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391\n-10.3 abc9 - use ABC9 for technology mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394\n-10.4 abc9_exe - use ABC9 for technology mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 397\n-10.5 abc9_ops - helper functions for ABC9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399\n-10.6 abc_new - (experimental) use ABC for SC technology mapping (new) . . . . . . . . . . . . . 401\n-10.7 abstract - replace signals with abstract values during formal verification . . . . . . . . . . . . 402\n-10.8 add - add objects to the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403\n-10.9 aigmap - map logic to and-inverter-graph circuit . . . . . . . . . . . . . . . . . . . . . . . . . 404\n-10.10 alumacc - extract ALU and MACC cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404\n-10.11 anlogic_eqn - Anlogic: Calculate equations for luts . . . . . . . . . . . . . . . . . . . . . . . 404\n-10.12 anlogic_fixcarry - Anlogic: fix carry chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405\n-10.13 assertpmux - adds asserts for parallel muxes . . . . . . . . . . . . . . . . . . . . . . . . . . . 405\n-10.14 async2sync - convert async FF inputs to sync circuits . . . . . . . . . . . . . . . . . . . . . . 405\n-10.15 attrmap - renaming attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405\n-10.16 attrmvcp - move or copy attributes from wires to driving cells . . . . . . . . . . . . . . . . . 406\n-10.17 autoname - automatically assign names to objects . . . . . . . . . . . . . . . . . . . . . . . . 407\n-10.18 blackbox - convert modules into blackbox modules . . . . . . . . . . . . . . . . . . . . . . . . 407\n-10.19 bmuxmap - transform $bmux cells to trees of $mux cells . . . . . . . . . . . . . . . . . . . . 407\n-10.20 booth - map $mul cells to Booth multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . 407\n-10.21 box_derive - derive box modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408\n-10.22 bufnorm - (experimental) convert design into buffered-normalized form . . . . . . . . . . . . 408\n-10.23 bugpoint - minimize testcases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410\n-10.24 bwmuxmap - replace $bwmux cells with equivalent logic . . . . . . . . . . . . . . . . . . . . . 411\n-10.25 cd - a shortcut for \u2018select -module \u2019 . . . . . . . . . . . . . . . . . . . . . . . . . . . 411\n-10.26 cellmatch - match cells to their targets in cell library . . . . . . . . . . . . . . . . . . . . . . 412\n-10.27 check - check for obvious problems in the design . . . . . . . . . . . . . . . . . . . . . . . . . 412\n-10.28 chformal - change formal constraints of the design . . . . . . . . . . . . . . . . . . . . . . . . 413\n-10.29 chparam - re-evaluate modules with new parameters . . . . . . . . . . . . . . . . . . . . . . . 414\n-10.30 chtype - change type of cells in the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414\n-10.31 clean - remove unused cells and wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414\n-10.32 clean_zerowidth - clean zero-width connections from the design . . . . . . . . . . . . . . . . 415\n-10.33 clk2fflogic - convert clocked FFs to generic $ff cells . . . . . . . . . . . . . . . . . . . . . . . . 415\n-10.34 clkbufmap - insert clock buffers on clock networks . . . . . . . . . . . . . . . . . . . . . . . . 415\n-10.35 clockgate - extract clock gating out of flip flops . . . . . . . . . . . . . . . . . . . . . . . . . . 416\n-10.36 connect - create or remove connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\n-10.37 connect_rpc - connect to RPC frontend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\n-10.38 connwrappers - match width of input-output port pairs . . . . . . . . . . . . . . . . . . . . . 418\n-10.39 coolrunner2_fixup - insert necessary buffer cells for CoolRunner-II architecture . . . . . . . . 419\n-10.40 coolrunner2_sop - break $sop cells into ANDTERM/ORTERM cells . . . . . . . . . . . . . . 419\n-10.41 copy - copy modules in the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419\n-10.42 cover - print code coverage counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419\n+391\n+10.1 Yosys environment variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392\n+10.2 abc - use ABC for technology mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393\n+10.3 abc9 - use ABC9 for technology mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396\n+10.4 abc9_exe - use ABC9 for technology mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 399\n+10.5 abc9_ops - helper functions for ABC9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401\n+10.6 abc_new - (experimental) use ABC for SC technology mapping (new) . . . . . . . . . . . . . 403\n+10.7 abstract - replace signals with abstract values during formal verification . . . . . . . . . . . . 404\n+10.8 add - add objects to the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405\n+10.9 aigmap - map logic to and-inverter-graph circuit . . . . . . . . . . . . . . . . . . . . . . . . . 406\n+10.10 alumacc - extract ALU and MACC cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406\n+10.11 anlogic_eqn - Anlogic: Calculate equations for luts . . . . . . . . . . . . . . . . . . . . . . . 406\n+10.12 anlogic_fixcarry - Anlogic: fix carry chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407\n+10.13 assertpmux - adds asserts for parallel muxes . . . . . . . . . . . . . . . . . . . . . . . . . . . 407\n+10.14 async2sync - convert async FF inputs to sync circuits . . . . . . . . . . . . . . . . . . . . . . 407\n+10.15 attrmap - renaming attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407\n+10.16 attrmvcp - move or copy attributes from wires to driving cells . . . . . . . . . . . . . . . . . 408\n+10.17 autoname - automatically assign names to objects . . . . . . . . . . . . . . . . . . . . . . . . 409\n+10.18 blackbox - convert modules into blackbox modules . . . . . . . . . . . . . . . . . . . . . . . . 409\n+10.19 bmuxmap - transform $bmux cells to trees of $mux cells . . . . . . . . . . . . . . . . . . . . 409\n+10.20 booth - map $mul cells to Booth multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . 409\n+10.21 box_derive - derive box modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410\n+10.22 bufnorm - (experimental) convert design into buffered-normalized form . . . . . . . . . . . . 410\n+10.23 bugpoint - minimize testcases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412\n+10.24 bwmuxmap - replace $bwmux cells with equivalent logic . . . . . . . . . . . . . . . . . . . . . 413\n+10.25 cd - a shortcut for \u2018select -module \u2019 . . . . . . . . . . . . . . . . . . . . . . . . . . . 413\n+10.26 cellmatch - match cells to their targets in cell library . . . . . . . . . . . . . . . . . . . . . . 414\n+10.27 check - check for obvious problems in the design . . . . . . . . . . . . . . . . . . . . . . . . . 414\n+10.28 chformal - change formal constraints of the design . . . . . . . . . . . . . . . . . . . . . . . . 415\n+10.29 chparam - re-evaluate modules with new parameters . . . . . . . . . . . . . . . . . . . . . . . 416\n+10.30 chtype - change type of cells in the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416\n+10.31 clean - remove unused cells and wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416\n+10.32 clean_zerowidth - clean zero-width connections from the design . . . . . . . . . . . . . . . . 417\n+10.33 clk2fflogic - convert clocked FFs to generic $ff cells . . . . . . . . . . . . . . . . . . . . . . . . 417\n+10.34 clkbufmap - insert clock buffers on clock networks . . . . . . . . . . . . . . . . . . . . . . . . 417\n+10.35 clockgate - extract clock gating out of flip flops . . . . . . . . . . . . . . . . . . . . . . . . . . 418\n+10.36 connect - create or remove connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419\n+10.37 connect_rpc - connect to RPC frontend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419\n+10.38 connwrappers - match width of input-output port pairs . . . . . . . . . . . . . . . . . . . . . 420\n+10.39 coolrunner2_fixup - insert necessary buffer cells for CoolRunner-II architecture . . . . . . . . 421\n+10.40 coolrunner2_sop - break $sop cells into ANDTERM/ORTERM cells . . . . . . . . . . . . . . 421\n+10.41 copy - copy modules in the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421\n+10.42 cover - print code coverage counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421\n \n iv\n \n-\f10.43 cutpoint - adds formal cut points to the design . . . . . . . . . . . . . . . . . . . . . . . . . . 420\n-10.44 debug - run command with debug log messages enabled . . . . . . . . . . . . . . . . . . . . . 420\n-10.45 delete - delete objects in the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421\n-10.46 deminout - demote inout ports to input or output . . . . . . . . . . . . . . . . . . . . . . . . 421\n-10.47 demuxmap - transform $demux cells to $eq + $mux cells . . . . . . . . . . . . . . . . . . . . 421\n-10.48 design - save, restore and reset current design . . . . . . . . . . . . . . . . . . . . . . . . . . . 421\n-10.49 dffinit - set INIT param on FF cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423\n-10.50 dfflegalize - convert FFs to types supported by the target . . . . . . . . . . . . . . . . . . . . 423\n-10.51 dfflibmap - technology mapping of flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424\n-10.52 dffunmap - unmap clock enable and synchronous reset from FFs . . . . . . . . . . . . . . . . 425\n-10.53 dft_tag - create tagging logic for data flow tracking . . . . . . . . . . . . . . . . . . . . . . . 425\n-10.54 dump - print parts of the design in RTLIL format . . . . . . . . . . . . . . . . . . . . . . . . 426\n-10.55 echo - turning echoing back of commands on and off . . . . . . . . . . . . . . . . . . . . . . . 426\n-10.56 edgetypes - list all types of edges in selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 426\n-10.57 efinix_fixcarry - Efinix: fix carry chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427\n-10.58 equiv_add - add a $equiv cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427\n-10.59 equiv_induct - proving $equiv cells using temporal induction . . . . . . . . . . . . . . . . . . 427\n-10.60 equiv_make - prepare a circuit for equivalence checking . . . . . . . . . . . . . . . . . . . . . 428\n-10.61 equiv_mark - mark equivalence checking regions . . . . . . . . . . . . . . . . . . . . . . . . . 428\n-10.62 equiv_miter - extract miter from equiv circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 428\n-10.63 equiv_opt - prove equivalence for optimized circuit . . . . . . . . . . . . . . . . . . . . . . . 429\n-10.64 equiv_purge - purge equivalence checking module . . . . . . . . . . . . . . . . . . . . . . . . 430\n-10.65 equiv_remove - remove $equiv cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430\n-10.66 equiv_simple - try proving simple $equiv instances . . . . . . . . . . . . . . . . . . . . . . . 431\n-10.67 equiv_status - print status of equivalent checking module . . . . . . . . . . . . . . . . . . . . 431\n-10.68 equiv_struct - structural equivalence checking . . . . . . . . . . . . . . . . . . . . . . . . . . 431\n-10.69 eval - evaluate the circuit given an input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432\n-10.70 example_dt - drivertools example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432\n-10.71 exec - execute commands in the operating system shell . . . . . . . . . . . . . . . . . . . . . 433\n-10.72 expose - convert internal signals to module ports . . . . . . . . . . . . . . . . . . . . . . . . . 433\n-10.73 extract - find subcircuits and replace them with cells . . . . . . . . . . . . . . . . . . . . . . 434\n-10.74 extract_counter - Extract GreenPak4 counter cells . . . . . . . . . . . . . . . . . . . . . . . . 436\n-10.75 extract_fa - find and extract full/half adders . . . . . . . . . . . . . . . . . . . . . . . . . . . 436\n-10.76 extract_reduce - converts gate chains into $reduce_* cells . . . . . . . . . . . . . . . . . . . 437\n-10.77 extractinv - extract explicit inverter cells for invertible cell pins . . . . . . . . . . . . . . . . . 437\n-10.78 flatten - flatten design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437\n-10.79 flowmap - pack LUTs with FlowMap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n-10.80 fmcombine - combine two instances of a cell into one . . . . . . . . . . . . . . . . . . . . . . . 439\n-10.81 fminit - set init values/sequences for formal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\n-10.82 formalff - prepare FFs for formal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\n-10.83 freduce - perform functional reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441\n-10.84 fsm - extract and optimize finite state machines . . . . . . . . . . . . . . . . . . . . . . . . . 442\n-10.85 fsm_detect - finding FSMs in design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442\n-10.86 fsm_expand - expand FSM cells by merging logic into it . . . . . . . . . . . . . . . . . . . . 443\n-10.87 fsm_export - exporting FSMs to KISS2 files . . . . . . . . . . . . . . . . . . . . . . . . . . . 443\n-10.88 fsm_extract - extracting FSMs in design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444\n-10.89 fsm_info - print information on finite state machines . . . . . . . . . . . . . . . . . . . . . . 444\n-10.90 fsm_map - mapping FSMs to basic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444\n-10.91 fsm_opt - optimize finite state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444\n-10.92 fsm_recode - recoding finite state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444\n-10.93 fst2tb - generate testbench out of fst file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445\n-10.94 future - resolve future sampled value functions . . . . . . . . . . . . . . . . . . . . . . . . . . 446\n-10.95 gatemate_foldinv - fold inverters into Gatemate LUT trees . . . . . . . . . . . . . . . . . . . 446\n-10.96 glift - create GLIFT models and optimization problems . . . . . . . . . . . . . . . . . . . . . 446\n+\f10.43 cutpoint - adds formal cut points to the design . . . . . . . . . . . . . . . . . . . . . . . . . . 422\n+10.44 debug - run command with debug log messages enabled . . . . . . . . . . . . . . . . . . . . . 422\n+10.45 delete - delete objects in the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423\n+10.46 deminout - demote inout ports to input or output . . . . . . . . . . . . . . . . . . . . . . . . 423\n+10.47 demuxmap - transform $demux cells to $eq + $mux cells . . . . . . . . . . . . . . . . . . . . 423\n+10.48 design - save, restore and reset current design . . . . . . . . . . . . . . . . . . . . . . . . . . . 423\n+10.49 dffinit - set INIT param on FF cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425\n+10.50 dfflegalize - convert FFs to types supported by the target . . . . . . . . . . . . . . . . . . . . 425\n+10.51 dfflibmap - technology mapping of flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426\n+10.52 dffunmap - unmap clock enable and synchronous reset from FFs . . . . . . . . . . . . . . . . 427\n+10.53 dft_tag - create tagging logic for data flow tracking . . . . . . . . . . . . . . . . . . . . . . . 427\n+10.54 dump - print parts of the design in RTLIL format . . . . . . . . . . . . . . . . . . . . . . . . 428\n+10.55 echo - turning echoing back of commands on and off . . . . . . . . . . . . . . . . . . . . . . . 428\n+10.56 edgetypes - list all types of edges in selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 428\n+10.57 efinix_fixcarry - Efinix: fix carry chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429\n+10.58 equiv_add - add a $equiv cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429\n+10.59 equiv_induct - proving $equiv cells using temporal induction . . . . . . . . . . . . . . . . . . 429\n+10.60 equiv_make - prepare a circuit for equivalence checking . . . . . . . . . . . . . . . . . . . . . 430\n+10.61 equiv_mark - mark equivalence checking regions . . . . . . . . . . . . . . . . . . . . . . . . . 430\n+10.62 equiv_miter - extract miter from equiv circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 430\n+10.63 equiv_opt - prove equivalence for optimized circuit . . . . . . . . . . . . . . . . . . . . . . . 431\n+10.64 equiv_purge - purge equivalence checking module . . . . . . . . . . . . . . . . . . . . . . . . 432\n+10.65 equiv_remove - remove $equiv cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432\n+10.66 equiv_simple - try proving simple $equiv instances . . . . . . . . . . . . . . . . . . . . . . . 433\n+10.67 equiv_status - print status of equivalent checking module . . . . . . . . . . . . . . . . . . . . 433\n+10.68 equiv_struct - structural equivalence checking . . . . . . . . . . . . . . . . . . . . . . . . . . 433\n+10.69 eval - evaluate the circuit given an input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434\n+10.70 example_dt - drivertools example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434\n+10.71 exec - execute commands in the operating system shell . . . . . . . . . . . . . . . . . . . . . 435\n+10.72 expose - convert internal signals to module ports . . . . . . . . . . . . . . . . . . . . . . . . . 435\n+10.73 extract - find subcircuits and replace them with cells . . . . . . . . . . . . . . . . . . . . . . 436\n+10.74 extract_counter - Extract GreenPak4 counter cells . . . . . . . . . . . . . . . . . . . . . . . . 438\n+10.75 extract_fa - find and extract full/half adders . . . . . . . . . . . . . . . . . . . . . . . . . . . 438\n+10.76 extract_reduce - converts gate chains into $reduce_* cells . . . . . . . . . . . . . . . . . . . 439\n+10.77 extractinv - extract explicit inverter cells for invertible cell pins . . . . . . . . . . . . . . . . . 439\n+10.78 flatten - flatten design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\n+10.79 flowmap - pack LUTs with FlowMap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\n+10.80 fmcombine - combine two instances of a cell into one . . . . . . . . . . . . . . . . . . . . . . . 441\n+10.81 fminit - set init values/sequences for formal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442\n+10.82 formalff - prepare FFs for formal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442\n+10.83 freduce - perform functional reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443\n+10.84 fsm - extract and optimize finite state machines . . . . . . . . . . . . . . . . . . . . . . . . . 444\n+10.85 fsm_detect - finding FSMs in design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444\n+10.86 fsm_expand - expand FSM cells by merging logic into it . . . . . . . . . . . . . . . . . . . . 445\n+10.87 fsm_export - exporting FSMs to KISS2 files . . . . . . . . . . . . . . . . . . . . . . . . . . . 445\n+10.88 fsm_extract - extracting FSMs in design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446\n+10.89 fsm_info - print information on finite state machines . . . . . . . . . . . . . . . . . . . . . . 446\n+10.90 fsm_map - mapping FSMs to basic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446\n+10.91 fsm_opt - optimize finite state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446\n+10.92 fsm_recode - recoding finite state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446\n+10.93 fst2tb - generate testbench out of fst file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447\n+10.94 future - resolve future sampled value functions . . . . . . . . . . . . . . . . . . . . . . . . . . 448\n+10.95 gatemate_foldinv - fold inverters into Gatemate LUT trees . . . . . . . . . . . . . . . . . . . 448\n+10.96 glift - create GLIFT models and optimization problems . . . . . . . . . . . . . . . . . . . . . 448\n \n v\n \n-\f10.97 greenpak4_dffinv - merge greenpak4 inverters and DFF/latches . . . . . . . . . . . . . . . . 448\n-10.98 help - display help messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448\n-10.99 hierarchy - check, expand and clean up design hierarchy . . . . . . . . . . . . . . . . . . . . . 448\n-10.100hilomap - technology mapping of constant hi- and/or lo-drivers . . . . . . . . . . . . . . . . . 450\n-10.101history - show last interactive commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450\n-10.102ice40_braminit - iCE40: perform SB_RAM40_4K initialization from file . . . . . . . . . . . 450\n-10.103ice40_dsp - iCE40: map multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451\n-10.104ice40_opt - iCE40: perform simple optimizations . . . . . . . . . . . . . . . . . . . . . . . . . 451\n-10.105ice40_wrapcarry - iCE40: wrap carries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451\n-10.106insbuf - insert buffer cells for connected wires . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n-10.107internal_stats - print internal statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n-10.108iopadmap - technology mapping of i/o pads (or buffers) . . . . . . . . . . . . . . . . . . . . . 452\n-10.109jny - write design and metadata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n-10.110json - write design in JSON format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n-10.111keep_hierarchy - selectively add the keep_hierarchy attribute . . . . . . . . . . . . . . . . . 454\n-10.112lattice_gsr - Lattice: handle GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\n-10.113libcache - control caching of technology library data parsed from liberty files . . . . . . . . . 455\n-10.114license - print license terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455\n-10.115log - print text and log files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\n-10.116logger - set logger properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\n-10.117ls - list modules or objects in modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457\n-10.118ltp - print longest topological path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457\n-10.119lut2mux - convert $lut to $_MUX_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n-10.120maccmap - mapping macc cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n-10.121memory - translate memories to basic cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n-10.122memory_bmux2rom - convert muxes to ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n-10.123memory_bram - map memories to block rams . . . . . . . . . . . . . . . . . . . . . . . . . . 459\n-10.124memory_collect - creating multi-port memory cells . . . . . . . . . . . . . . . . . . . . . . . 461\n-10.125memory_dff - merge input/output DFFs into memory read ports . . . . . . . . . . . . . . . 461\n-10.126memory_libmap - map memories to cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461\n-10.127memory_map - translate multiport memories to basic cells . . . . . . . . . . . . . . . . . . . 462\n-10.128memory_memx - emulate vlog sim behavior for mem ports . . . . . . . . . . . . . . . . . . . 462\n-10.129memory_narrow - split up wide memory ports . . . . . . . . . . . . . . . . . . . . . . . . . . 463\n-10.130memory_nordff - extract read port FFs from memories . . . . . . . . . . . . . . . . . . . . . 463\n-10.131memory_share - consolidate memory ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463\n-10.132memory_unpack - unpack multi-port memory cells . . . . . . . . . . . . . . . . . . . . . . . 463\n-10.133microchip_dffopt - MICROCHIP: optimize FF control signal usage . . . . . . . . . . . . . . 464\n-10.134microchip_dsp - MICROCHIP: pack resources into DSPs . . . . . . . . . . . . . . . . . . . . 464\n-10.135miter - automatically create a miter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464\n-10.136mutate - generate or apply design mutations . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\n-10.137muxcover - cover trees of MUX cells with wider MUXes . . . . . . . . . . . . . . . . . . . . . 467\n-10.138muxpack - $mux/$pmux cascades to $pmux . . . . . . . . . . . . . . . . . . . . . . . . . . . 467\n-10.139nlutmap - map to LUTs of different sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n-10.140nx_carry - NanoXplore: create carry cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n-10.141onehot - optimize $eq cells for onehot signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n-10.142opt - perform simple optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n-10.143opt_clean - remove unused cells and wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n-10.144opt_demorgan - Optimize reductions with DeMorgan equivalents . . . . . . . . . . . . . . . 469\n-10.145opt_dff - perform DFF optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n-10.146opt_expr - perform const folding and simple expression rewriting . . . . . . . . . . . . . . . 470\n-10.147opt_ffinv - push inverters through FFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471\n-10.148opt_lut - optimize LUT cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471\n-10.149opt_lut_ins - discard unused LUT inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471\n-10.150opt_mem - optimize memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472\n+\f10.97 greenpak4_dffinv - merge greenpak4 inverters and DFF/latches . . . . . . . . . . . . . . . . 450\n+10.98 help - display help messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450\n+10.99 hierarchy - check, expand and clean up design hierarchy . . . . . . . . . . . . . . . . . . . . . 450\n+10.100hilomap - technology mapping of constant hi- and/or lo-drivers . . . . . . . . . . . . . . . . . 452\n+10.101history - show last interactive commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n+10.102ice40_braminit - iCE40: perform SB_RAM40_4K initialization from file . . . . . . . . . . . 452\n+10.103ice40_dsp - iCE40: map multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n+10.104ice40_opt - iCE40: perform simple optimizations . . . . . . . . . . . . . . . . . . . . . . . . . 453\n+10.105ice40_wrapcarry - iCE40: wrap carries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453\n+10.106insbuf - insert buffer cells for connected wires . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\n+10.107internal_stats - print internal statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\n+10.108iopadmap - technology mapping of i/o pads (or buffers) . . . . . . . . . . . . . . . . . . . . . 454\n+10.109jny - write design and metadata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455\n+10.110json - write design in JSON format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455\n+10.111keep_hierarchy - selectively add the keep_hierarchy attribute . . . . . . . . . . . . . . . . . 456\n+10.112lattice_gsr - Lattice: handle GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\n+10.113libcache - control caching of technology library data parsed from liberty files . . . . . . . . . 457\n+10.114license - print license terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457\n+10.115log - print text and log files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n+10.116logger - set logger properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458\n+10.117ls - list modules or objects in modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459\n+10.118ltp - print longest topological path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459\n+10.119lut2mux - convert $lut to $_MUX_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n+10.120maccmap - mapping macc cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n+10.121memory - translate memories to basic cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n+10.122memory_bmux2rom - convert muxes to ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n+10.123memory_bram - map memories to block rams . . . . . . . . . . . . . . . . . . . . . . . . . . 461\n+10.124memory_collect - creating multi-port memory cells . . . . . . . . . . . . . . . . . . . . . . . 463\n+10.125memory_dff - merge input/output DFFs into memory read ports . . . . . . . . . . . . . . . 463\n+10.126memory_libmap - map memories to cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463\n+10.127memory_map - translate multiport memories to basic cells . . . . . . . . . . . . . . . . . . . 464\n+10.128memory_memx - emulate vlog sim behavior for mem ports . . . . . . . . . . . . . . . . . . . 464\n+10.129memory_narrow - split up wide memory ports . . . . . . . . . . . . . . . . . . . . . . . . . . 465\n+10.130memory_nordff - extract read port FFs from memories . . . . . . . . . . . . . . . . . . . . . 465\n+10.131memory_share - consolidate memory ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\n+10.132memory_unpack - unpack multi-port memory cells . . . . . . . . . . . . . . . . . . . . . . . 465\n+10.133microchip_dffopt - MICROCHIP: optimize FF control signal usage . . . . . . . . . . . . . . 466\n+10.134microchip_dsp - MICROCHIP: pack resources into DSPs . . . . . . . . . . . . . . . . . . . . 466\n+10.135miter - automatically create a miter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466\n+10.136mutate - generate or apply design mutations . . . . . . . . . . . . . . . . . . . . . . . . . . . 467\n+10.137muxcover - cover trees of MUX cells with wider MUXes . . . . . . . . . . . . . . . . . . . . . 469\n+10.138muxpack - $mux/$pmux cascades to $pmux . . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n+10.139nlutmap - map to LUTs of different sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n+10.140nx_carry - NanoXplore: create carry cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n+10.141onehot - optimize $eq cells for onehot signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n+10.142opt - perform simple optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470\n+10.143opt_clean - remove unused cells and wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471\n+10.144opt_demorgan - Optimize reductions with DeMorgan equivalents . . . . . . . . . . . . . . . 471\n+10.145opt_dff - perform DFF optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472\n+10.146opt_expr - perform const folding and simple expression rewriting . . . . . . . . . . . . . . . 472\n+10.147opt_ffinv - push inverters through FFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473\n+10.148opt_lut - optimize LUT cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473\n+10.149opt_lut_ins - discard unused LUT inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473\n+10.150opt_mem - optimize memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474\n \n vi\n \n-\f10.151opt_mem_feedback - convert memory read-to-write port feedback paths to write enables . . 472\n-10.152opt_mem_priority - remove priority relations between write ports that can never collide . . 472\n-10.153opt_mem_widen - optimize memories where all ports are wide . . . . . . . . . . . . . . . . . 473\n-10.154opt_merge - consolidate identical cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473\n-10.155opt_muxtree - eliminate dead trees in multiplexer trees . . . . . . . . . . . . . . . . . . . . . 473\n-10.156opt_reduce - simplify large MUXes and AND/OR gates . . . . . . . . . . . . . . . . . . . . . 473\n-10.157opt_share - merge mutually exclusive cells of the same type that share an input signal . . . 474\n-10.158paramap - renaming cell parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474\n-10.159peepopt - collection of peephole optimizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\n-10.160plugin - load and list loaded plugins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\n-10.161pmux2shiftx - transform $pmux cells to $shiftx cells . . . . . . . . . . . . . . . . . . . . . . . 476\n-10.162pmuxtree - transform $pmux cells to trees of $mux cells . . . . . . . . . . . . . . . . . . . . . 476\n-10.163portarcs - derive port arcs for propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . 476\n-10.164portlist - list (top-level) ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477\n-10.165prep - generic synthesis script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477\n-10.166printattrs - print attributes of selected objects . . . . . . . . . . . . . . . . . . . . . . . . . . 478\n-10.167proc - translate processes to netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479\n-10.168proc_arst - detect asynchronous resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479\n-10.169proc_clean - remove empty parts of processes . . . . . . . . . . . . . . . . . . . . . . . . . . 480\n-10.170proc_dff - extract flip-flops from processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480\n-10.171proc_dlatch - extract latches from processes . . . . . . . . . . . . . . . . . . . . . . . . . . . 480\n-10.172proc_init - convert initial block to init attributes . . . . . . . . . . . . . . . . . . . . . . . . 480\n-10.173proc_memwr - extract memory writes from processes . . . . . . . . . . . . . . . . . . . . . . 481\n-10.174proc_mux - convert decision trees to multiplexers . . . . . . . . . . . . . . . . . . . . . . . . 481\n-10.175proc_prune - remove redundant assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n-10.176proc_rmdead - eliminate dead trees in decision trees . . . . . . . . . . . . . . . . . . . . . . . 481\n-10.177proc_rom - convert switches to ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n-10.178qbfsat - solve a 2QBF-SAT problem in the circuit . . . . . . . . . . . . . . . . . . . . . . . . 482\n-10.179ql_bram_merge - Infers QuickLogic k6n10f BRAM pairs that can operate independently . . 483\n-10.180ql_bram_types - Change TDP36K type to subtypes . . . . . . . . . . . . . . . . . . . . . . . 483\n-10.181ql_dsp_io_regs - change types of QL_DSP2 depending on configuration . . . . . . . . . . . 483\n-10.182ql_dsp_macc - infer QuickLogic multiplier-accumulator DSP cells . . . . . . . . . . . . . . . 484\n-10.183ql_dsp_simd - merge QuickLogic K6N10f DSP pairs to operate in SIMD mode . . . . . . . . 484\n-10.184ql_ioff - Infer I/O FFs for qlf_k6n10f architecture . . . . . . . . . . . . . . . . . . . . . . . . 484\n-10.185read - load HDL designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n-10.186read_aiger - read AIGER file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485\n-10.187read_blif - read BLIF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\n-10.188read_json - read JSON file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\n-10.189read_liberty - read cells from liberty file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\n-10.190read_rtlil - read modules from RTLIL file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487\n-10.191read_verilog - read modules from Verilog file . . . . . . . . . . . . . . . . . . . . . . . . . . . 488\n-10.192read_verilog_file_list - parse a Verilog file list . . . . . . . . . . . . . . . . . . . . . . . . . . 491\n-10.193read_xaiger2 - (experimental) read XAIGER file . . . . . . . . . . . . . . . . . . . . . . . . . 491\n-10.194recover_names - Execute a lossy mapping command and recover original netnames . . . . . 492\n-10.195rename - rename object in the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492\n-10.196rmports - remove module ports with no connections . . . . . . . . . . . . . . . . . . . . . . . 493\n-10.197sat - solve a SAT problem in the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493\n-10.198scatter - add additional intermediate nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497\n-10.199scc - detect strongly connected components (logic loops) . . . . . . . . . . . . . . . . . . . . 497\n-10.200scratchpad - get/set values in the scratchpad . . . . . . . . . . . . . . . . . . . . . . . . . . . 498\n-10.201script - execute commands from file or wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498\n-10.202select - modify and view the list of selected objects . . . . . . . . . . . . . . . . . . . . . . . . 499\n-10.203setattr - set/unset attributes on objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503\n-10.204setenv - set an environment variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504\n+\f10.151opt_mem_feedback - convert memory read-to-write port feedback paths to write enables . . 474\n+10.152opt_mem_priority - remove priority relations between write ports that can never collide . . 474\n+10.153opt_mem_widen - optimize memories where all ports are wide . . . . . . . . . . . . . . . . . 475\n+10.154opt_merge - consolidate identical cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\n+10.155opt_muxtree - eliminate dead trees in multiplexer trees . . . . . . . . . . . . . . . . . . . . . 475\n+10.156opt_reduce - simplify large MUXes and AND/OR gates . . . . . . . . . . . . . . . . . . . . . 475\n+10.157opt_share - merge mutually exclusive cells of the same type that share an input signal . . . 476\n+10.158paramap - renaming cell parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476\n+10.159peepopt - collection of peephole optimizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477\n+10.160plugin - load and list loaded plugins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477\n+10.161pmux2shiftx - transform $pmux cells to $shiftx cells . . . . . . . . . . . . . . . . . . . . . . . 478\n+10.162pmuxtree - transform $pmux cells to trees of $mux cells . . . . . . . . . . . . . . . . . . . . . 478\n+10.163portarcs - derive port arcs for propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . 478\n+10.164portlist - list (top-level) ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479\n+10.165prep - generic synthesis script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479\n+10.166printattrs - print attributes of selected objects . . . . . . . . . . . . . . . . . . . . . . . . . . 480\n+10.167proc - translate processes to netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n+10.168proc_arst - detect asynchronous resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\n+10.169proc_clean - remove empty parts of processes . . . . . . . . . . . . . . . . . . . . . . . . . . 482\n+10.170proc_dff - extract flip-flops from processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482\n+10.171proc_dlatch - extract latches from processes . . . . . . . . . . . . . . . . . . . . . . . . . . . 482\n+10.172proc_init - convert initial block to init attributes . . . . . . . . . . . . . . . . . . . . . . . . 482\n+10.173proc_memwr - extract memory writes from processes . . . . . . . . . . . . . . . . . . . . . . 483\n+10.174proc_mux - convert decision trees to multiplexers . . . . . . . . . . . . . . . . . . . . . . . . 483\n+10.175proc_prune - remove redundant assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n+10.176proc_rmdead - eliminate dead trees in decision trees . . . . . . . . . . . . . . . . . . . . . . . 483\n+10.177proc_rom - convert switches to ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n+10.178qbfsat - solve a 2QBF-SAT problem in the circuit . . . . . . . . . . . . . . . . . . . . . . . . 484\n+10.179ql_bram_merge - Infers QuickLogic k6n10f BRAM pairs that can operate independently . . 485\n+10.180ql_bram_types - Change TDP36K type to subtypes . . . . . . . . . . . . . . . . . . . . . . . 485\n+10.181ql_dsp_io_regs - change types of QL_DSP2 depending on configuration . . . . . . . . . . . 485\n+10.182ql_dsp_macc - infer QuickLogic multiplier-accumulator DSP cells . . . . . . . . . . . . . . . 486\n+10.183ql_dsp_simd - merge QuickLogic K6N10f DSP pairs to operate in SIMD mode . . . . . . . . 486\n+10.184ql_ioff - Infer I/O FFs for qlf_k6n10f architecture . . . . . . . . . . . . . . . . . . . . . . . . 486\n+10.185read - load HDL designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\n+10.186read_aiger - read AIGER file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487\n+10.187read_blif - read BLIF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488\n+10.188read_json - read JSON file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488\n+10.189read_liberty - read cells from liberty file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488\n+10.190read_rtlil - read modules from RTLIL file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489\n+10.191read_verilog - read modules from Verilog file . . . . . . . . . . . . . . . . . . . . . . . . . . . 490\n+10.192read_verilog_file_list - parse a Verilog file list . . . . . . . . . . . . . . . . . . . . . . . . . . 493\n+10.193read_xaiger2 - (experimental) read XAIGER file . . . . . . . . . . . . . . . . . . . . . . . . . 493\n+10.194recover_names - Execute a lossy mapping command and recover original netnames . . . . . 494\n+10.195rename - rename object in the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494\n+10.196rmports - remove module ports with no connections . . . . . . . . . . . . . . . . . . . . . . . 495\n+10.197sat - solve a SAT problem in the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495\n+10.198scatter - add additional intermediate nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499\n+10.199scc - detect strongly connected components (logic loops) . . . . . . . . . . . . . . . . . . . . 499\n+10.200scratchpad - get/set values in the scratchpad . . . . . . . . . . . . . . . . . . . . . . . . . . . 500\n+10.201script - execute commands from file or wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500\n+10.202select - modify and view the list of selected objects . . . . . . . . . . . . . . . . . . . . . . . . 501\n+10.203setattr - set/unset attributes on objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505\n+10.204setenv - set an environment variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506\n \n vii\n \n-\f10.205setparam - set/unset parameters on objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504\n-10.206setundef - replace undef values with defined constants . . . . . . . . . . . . . . . . . . . . . . 504\n-10.207share - perform sat-based resource sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505\n-10.208shell - enter interactive command mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505\n-10.209show - generate schematics using graphviz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506\n-10.210shregmap - map shift registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\n-10.211sim - simulate the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509\n-10.212simplemap - mapping simple coarse-grain cells . . . . . . . . . . . . . . . . . . . . . . . . . . 511\n-10.213splice - create explicit splicing cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512\n-10.214splitcells - split up multi-bit cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512\n-10.215splitnets - split up multi-bit nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513\n-10.216sta - perform static timing analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513\n-10.217stat - print some statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513\n-10.218submod - moving part of a module to a new submodule . . . . . . . . . . . . . . . . . . . . . 514\n-10.219supercover - add hi/lo cover cells for each wire bit . . . . . . . . . . . . . . . . . . . . . . . . 515\n-10.220synth - generic synthesis script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\n-10.221synth_achronix - synthesis for Achronix Speedster22i FPGAs. . . . . . . . . . . . . . . . . . 517\n-10.222synth_anlogic - synthesis for Anlogic FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . 518\n-10.223synth_coolrunner2 - synthesis for Xilinx Coolrunner-II CPLDs . . . . . . . . . . . . . . . . . 520\n-10.224synth_easic - synthesis for eASIC platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522\n-10.225synth_ecp5 - synthesis for ECP5 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523\n-10.226synth_efinix - synthesis for Efinix FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527\n-10.227synth_fabulous - FABulous synthesis script . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528\n-10.228synth_gatemate - synthesis for Cologne Chip GateMate FPGAs . . . . . . . . . . . . . . . . 532\n-10.229synth_gowin - synthesis for Gowin FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535\n-10.230synth_greenpak4 - synthesis for GreenPAK4 FPGAs . . . . . . . . . . . . . . . . . . . . . . 537\n-10.231synth_ice40 - synthesis for iCE40 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539\n-10.232synth_intel - synthesis for Intel (Altera) FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . 542\n-10.233synth_intel_alm - synthesis for ALM-based Intel (Altera) FPGAs. . . . . . . . . . . . . . . . 545\n-10.234synth_lattice - synthesis for Lattice FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . 547\n-10.235synth_microchip - synthesis for Microchip FPGAs . . . . . . . . . . . . . . . . . . . . . . . . 551\n-10.236synth_nanoxplore - synthesis for NanoXplore FPGAs . . . . . . . . . . . . . . . . . . . . . . 554\n-10.237synth_nexus - synthesis for Lattice Nexus FPGAs . . . . . . . . . . . . . . . . . . . . . . . . 557\n-10.238synth_quicklogic - Synthesis for QuickLogic FPGAs . . . . . . . . . . . . . . . . . . . . . . . 560\n-10.239synth_sf2 - synthesis for SmartFusion2 and IGLOO2 FPGAs . . . . . . . . . . . . . . . . . . 563\n-10.240synth_xilinx - synthesis for Xilinx FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565\n-10.241synthprop - synthesize SVA properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569\n-10.242tcl - execute a TCL script file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569\n-10.243techmap - generic technology mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570\n-10.244tee - redirect command output to file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573\n-10.245test_abcloop - automatically test handling of loops in abc command . . . . . . . . . . . . . . 573\n-10.246test_autotb - generate simple test benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574\n-10.247test_cell - automatically test the implementation of a cell type . . . . . . . . . . . . . . . . . 574\n-10.248test_generic - test the generic compute graph . . . . . . . . . . . . . . . . . . . . . . . . . . 576\n-10.249test_pmgen - test pass for pmgen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\n-10.250torder - print cells in topological order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\n-10.251trace - redirect command output to file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577\n-10.252tribuf - infer tri-state buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577\n-10.253uniquify - create unique copies of modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577\n-10.254verific - load Verilog and VHDL designs using Verific . . . . . . . . . . . . . . . . . . . . . . 578\n-10.255verilog_defaults - set default options for read_verilog . . . . . . . . . . . . . . . . . . . . . . 580\n-10.256verilog_defines - define and undefine verilog defines . . . . . . . . . . . . . . . . . . . . . . . 580\n-10.257viz - visualize data flow graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581\n-10.258wbflip - flip the whitebox attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582\n+\f10.205setparam - set/unset parameters on objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506\n+10.206setundef - replace undef values with defined constants . . . . . . . . . . . . . . . . . . . . . . 506\n+10.207share - perform sat-based resource sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507\n+10.208shell - enter interactive command mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507\n+10.209show - generate schematics using graphviz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\n+10.210shregmap - map shift registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510\n+10.211sim - simulate the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511\n+10.212simplemap - mapping simple coarse-grain cells . . . . . . . . . . . . . . . . . . . . . . . . . . 513\n+10.213splice - create explicit splicing cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514\n+10.214splitcells - split up multi-bit cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514\n+10.215splitnets - split up multi-bit nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\n+10.216sta - perform static timing analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\n+10.217stat - print some statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\n+10.218submod - moving part of a module to a new submodule . . . . . . . . . . . . . . . . . . . . . 516\n+10.219supercover - add hi/lo cover cells for each wire bit . . . . . . . . . . . . . . . . . . . . . . . . 517\n+10.220synth - generic synthesis script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517\n+10.221synth_achronix - synthesis for Achronix Speedster22i FPGAs. . . . . . . . . . . . . . . . . . 519\n+10.222synth_anlogic - synthesis for Anlogic FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . 520\n+10.223synth_coolrunner2 - synthesis for Xilinx Coolrunner-II CPLDs . . . . . . . . . . . . . . . . . 522\n+10.224synth_easic - synthesis for eASIC platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524\n+10.225synth_ecp5 - synthesis for ECP5 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525\n+10.226synth_efinix - synthesis for Efinix FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529\n+10.227synth_fabulous - FABulous synthesis script . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530\n+10.228synth_gatemate - synthesis for Cologne Chip GateMate FPGAs . . . . . . . . . . . . . . . . 534\n+10.229synth_gowin - synthesis for Gowin FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537\n+10.230synth_greenpak4 - synthesis for GreenPAK4 FPGAs . . . . . . . . . . . . . . . . . . . . . . 539\n+10.231synth_ice40 - synthesis for iCE40 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541\n+10.232synth_intel - synthesis for Intel (Altera) FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . 544\n+10.233synth_intel_alm - synthesis for ALM-based Intel (Altera) FPGAs. . . . . . . . . . . . . . . . 547\n+10.234synth_lattice - synthesis for Lattice FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . 549\n+10.235synth_microchip - synthesis for Microchip FPGAs . . . . . . . . . . . . . . . . . . . . . . . . 553\n+10.236synth_nanoxplore - synthesis for NanoXplore FPGAs . . . . . . . . . . . . . . . . . . . . . . 556\n+10.237synth_nexus - synthesis for Lattice Nexus FPGAs . . . . . . . . . . . . . . . . . . . . . . . . 559\n+10.238synth_quicklogic - Synthesis for QuickLogic FPGAs . . . . . . . . . . . . . . . . . . . . . . . 562\n+10.239synth_sf2 - synthesis for SmartFusion2 and IGLOO2 FPGAs . . . . . . . . . . . . . . . . . . 565\n+10.240synth_xilinx - synthesis for Xilinx FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567\n+10.241synthprop - synthesize SVA properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571\n+10.242tcl - execute a TCL script file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571\n+10.243techmap - generic technology mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572\n+10.244tee - redirect command output to file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575\n+10.245test_abcloop - automatically test handling of loops in abc command . . . . . . . . . . . . . . 575\n+10.246test_autotb - generate simple test benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\n+10.247test_cell - automatically test the implementation of a cell type . . . . . . . . . . . . . . . . . 576\n+10.248test_generic - test the generic compute graph . . . . . . . . . . . . . . . . . . . . . . . . . . 578\n+10.249test_pmgen - test pass for pmgen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578\n+10.250torder - print cells in topological order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578\n+10.251trace - redirect command output to file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579\n+10.252tribuf - infer tri-state buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579\n+10.253uniquify - create unique copies of modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579\n+10.254verific - load Verilog and VHDL designs using Verific . . . . . . . . . . . . . . . . . . . . . . 580\n+10.255verilog_defaults - set default options for read_verilog . . . . . . . . . . . . . . . . . . . . . . 582\n+10.256verilog_defines - define and undefine verilog defines . . . . . . . . . . . . . . . . . . . . . . . 582\n+10.257viz - visualize data flow graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583\n+10.258wbflip - flip the whitebox attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584\n \n viii\n \n-\f10.259wrapcell - wrap individual cells into new modules . . . . . . . . . . . . . . . . . . . . . . . . 582\n-10.260wreduce - reduce the word size of operations if possible . . . . . . . . . . . . . . . . . . . . . 583\n-10.261write_aiger - write design to AIGER file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583\n-10.262write_aiger2 - (experimental) write design to AIGER file . . . . . . . . . . . . . . . . . . . . 584\n-10.263write_blif - write design to BLIF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584\n-10.264write_btor - write design to BTOR file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586\n-10.265write_cxxrtl - convert design to C++ RTL simulation . . . . . . . . . . . . . . . . . . . . . . 586\n-10.266write_edif - write design to EDIF netlist file . . . . . . . . . . . . . . . . . . . . . . . . . . . 591\n-10.267write_file - write a text to a file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592\n-10.268write_firrtl - write design to a FIRRTL file . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592\n-10.269write_functional_cxx - convert design to C++ using the functional backend . . . . . . . . . 592\n-10.270write_functional_rosette - Generate Rosette compatible Racket from Functional IR . . . . . 593\n-10.271write_functional_smt2 - Generate SMT-LIB from Functional IR . . . . . . . . . . . . . . . . 593\n-10.272write_intersynth - write design to InterSynth netlist file . . . . . . . . . . . . . . . . . . . . . 593\n-10.273write_jny - generate design metadata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593\n-10.274write_json - write design to a JSON file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594\n-10.275write_rtlil - write design to RTLIL file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599\n-10.276write_simplec - convert design to simple C code . . . . . . . . . . . . . . . . . . . . . . . . . 599\n-10.277write_smt2 - write design to SMT-LIBv2 file . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\n-10.278write_smv - write design to SMV file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603\n-10.279write_spice - write design to SPICE netlist file . . . . . . . . . . . . . . . . . . . . . . . . . . 603\n-10.280write_table - write design as connectivity table . . . . . . . . . . . . . . . . . . . . . . . . . 604\n-10.281write_verilog - write design to Verilog file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604\n-10.282write_xaiger - write design to XAIGER file . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606\n-10.283write_xaiger2 - (experimental) write module to XAIGER file . . . . . . . . . . . . . . . . . . 606\n-10.284xilinx_dffopt - Xilinx: optimize FF control signal usage . . . . . . . . . . . . . . . . . . . . . 607\n-10.285xilinx_dsp - Xilinx: pack resources into DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . 607\n-10.286xilinx_srl - Xilinx shift register extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608\n-10.287xprop - formal x propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608\n-10.288zinit - add inverters so all FF are zero-initialized . . . . . . . . . . . . . . . . . . . . . . . . . 609\n+\f10.259wrapcell - wrap individual cells into new modules . . . . . . . . . . . . . . . . . . . . . . . . 584\n+10.260wreduce - reduce the word size of operations if possible . . . . . . . . . . . . . . . . . . . . . 585\n+10.261write_aiger - write design to AIGER file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585\n+10.262write_aiger2 - (experimental) write design to AIGER file . . . . . . . . . . . . . . . . . . . . 586\n+10.263write_blif - write design to BLIF file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586\n+10.264write_btor - write design to BTOR file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588\n+10.265write_cxxrtl - convert design to C++ RTL simulation . . . . . . . . . . . . . . . . . . . . . . 588\n+10.266write_edif - write design to EDIF netlist file . . . . . . . . . . . . . . . . . . . . . . . . . . . 593\n+10.267write_file - write a text to a file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594\n+10.268write_firrtl - write design to a FIRRTL file . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594\n+10.269write_functional_cxx - convert design to C++ using the functional backend . . . . . . . . . 594\n+10.270write_functional_rosette - Generate Rosette compatible Racket from Functional IR . . . . . 595\n+10.271write_functional_smt2 - Generate SMT-LIB from Functional IR . . . . . . . . . . . . . . . . 595\n+10.272write_intersynth - write design to InterSynth netlist file . . . . . . . . . . . . . . . . . . . . . 595\n+10.273write_jny - generate design metadata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595\n+10.274write_json - write design to a JSON file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596\n+10.275write_rtlil - write design to RTLIL file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601\n+10.276write_simplec - convert design to simple C code . . . . . . . . . . . . . . . . . . . . . . . . . 601\n+10.277write_smt2 - write design to SMT-LIBv2 file . . . . . . . . . . . . . . . . . . . . . . . . . . . 602\n+10.278write_smv - write design to SMV file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605\n+10.279write_spice - write design to SPICE netlist file . . . . . . . . . . . . . . . . . . . . . . . . . . 605\n+10.280write_table - write design as connectivity table . . . . . . . . . . . . . . . . . . . . . . . . . 606\n+10.281write_verilog - write design to Verilog file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606\n+10.282write_xaiger - write design to XAIGER file . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608\n+10.283write_xaiger2 - (experimental) write module to XAIGER file . . . . . . . . . . . . . . . . . . 608\n+10.284xilinx_dffopt - Xilinx: optimize FF control signal usage . . . . . . . . . . . . . . . . . . . . . 609\n+10.285xilinx_dsp - Xilinx: pack resources into DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . 609\n+10.286xilinx_srl - Xilinx shift register extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610\n+10.287xprop - formal x propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610\n+10.288zinit - add inverters so all FF are zero-initialized . . . . . . . . . . . . . . . . . . . . . . . . . 611\n Bibliography\n \n-611\n+613\n \n Property Index\n \n-613\n+615\n \n Internal cell reference\n \n-615\n+617\n \n Command Reference\n \n-619\n+621\n \n Tag Index\n \n-623\n+625\n \n ix\n \n \fx\n \n \fYosysHQ Yosys, Version 0.52\n \n@@ -15519,15 +15519,20 @@\n \n To find the compile options used for a given Yosys build, call yosys-config --cxxflags. This documentation was built with the following compile options:\n --cxxflags\n \n -g -O2 -flto=auto -ffat-lto-objects \\\n -fstack-protector-strong -Wformat -Werror=format-security \\\n -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP \\\n--D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\n+-D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=@CXXFLAGS@.52 \\\n+-DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 \\\n+-std=c++17 -O3 -DYOSYS_ENABLE_READLINE \\\n+-DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB \\\n+-DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 \\\n+-DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER\n \n \u00f2 Note\n The YosysHQ specific extensions are only available with the TabbyCAD suite.\n \n Required Verific features\n The following features, along with their corresponding Yosys build parameters, are required for the YosysVerific patch:\n \u2022 RTL elaboration with\n@@ -15539,24 +15544,23 @@\n database/DBCompileFlags.h:\n DB_PRESERVE_INITIAL_VALUE\n \n \u00f2 Note\n Yosys+Verific builds may compile without these features, but we provide no guarantees and cannot offer\n support if they are disabled or the Yosys-Verific patch is not used.\n \n-Optional Verific features\n-The following Verific features are available with TabbyCAD and can be enabled in Yosys builds:\n-\u2022 EDIF support with ENABLE_VERIFIC_EDIF, and\n-\n 172\n \n Chapter 4. Yosys internals\n \n \fYosysHQ Yosys, Version 0.52\n \n+Optional Verific features\n+The following Verific features are available with TabbyCAD and can be enabled in Yosys builds:\n+\u2022 EDIF support with ENABLE_VERIFIC_EDIF, and\n \u2022 Liberty file support with ENABLE_VERIFIC_LIBERTY.\n Partially supported builds\n This section describes Yosys+Verific configurations which we have confirmed as working in the past, however\n they are not a part of our regular tests so we cannot guarantee they are still functional.\n To be able to compile Yosys with Verific, the Verific library must have support for at least one HDL language\n with RTL elaboration enabled. The following table lists a series of build configurations which are possible,\n but only provide a limited subset of features. Please note that support is limited without YosysHQ specific\n@@ -15621,24 +15625,24 @@\n intermediate representation called FunctionalIR which maps more directly on those targets.\n FunctionalIR represents the design as a function (inputs, current_state) -> (outputs, next_state).\n This function is broken down into a series of assignments to variables. Each assignment is a simple operation,\n such as an addition. Complex operations are broken up into multiple steps. For example, an RTLIL addition\n will be translated into a sign/zero extension of the inputs, followed by an addition.\n Like SSA form, each variable is assigned to exactly once. We can thus treat variables and assignments\n as equivalent and, since this is a graph-like representation, those variables are also called \u201cnodes\u201d. Unlike\n-RTLIL\u2019s cells and wires representation, this representation is strictly ordered (topologically sorted) with\n-definitions preceding their use.\n-Every node has a \u201csort\u201d (the FunctionalIR term for what might otherwise be called a \u201ctype\u201d). The sorts\n-available are\n 4.3. Working with the Yosys codebase\n \n 173\n \n \fYosysHQ Yosys, Version 0.52\n \n+RTLIL\u2019s cells and wires representation, this representation is strictly ordered (topologically sorted) with\n+definitions preceding their use.\n+Every node has a \u201csort\u201d (the FunctionalIR term for what might otherwise be called a \u201ctype\u201d). The sorts\n+available are\n \u2022 bit[n] for an n-bit bitvector, and\n \u2022 memory[n,m] for an immutable array of 2**n values of sort bit[m].\n In terms of actual code, Yosys provides a class Functional::IR that represents a design in FunctionalIR.\n Functional::IR::from_module generates an instance from an RTLIL module. The entire design is stored\n as a whole in an internal data structure. To access the design, the Functional::Node class provides a\n reference to a particular node in the design. The Functional::IR class supports the syntax for(auto node\n : ir) to iterate over every node.\n@@ -15669,25 +15673,24 @@\n Utility classes\n functional.h also provides utility classes that are independent of the main FunctionalIR representation but\n are likely to be useful for backends.\n Functional::Writer provides a simple formatting class that wraps a std::ostream and provides the following methods:\n \u2022 writer << value wraps os << value.\n \u2022 writer.print(fmt, value0, value1, value2, ...) replaces {0}, {1}, {2}, etc in the string fmt\n with value0, value1, value2, resp. Each value is formatted using os << value. It is also possible to\n-write {} to refer to one past the last index, i.e. {1} {} {} {7} {} is equivalent to {1} {2} {3} {7}\n-{8}.\n-\u2022 writer.print_with(fn, fmt, value0, value1, value2, ...) functions much the same as print\n-but it uses os << fn(value) to print each value and falls back to os << value if fn(value) is not\n-\n 174\n \n Chapter 4. Yosys internals\n \n \fYosysHQ Yosys, Version 0.52\n \n+write {} to refer to one past the last index, i.e. {1} {} {} {7} {} is equivalent to {1} {2} {3} {7}\n+{8}.\n+\u2022 writer.print_with(fn, fmt, value0, value1, value2, ...) functions much the same as print\n+but it uses os << fn(value) to print each value and falls back to os << value if fn(value) is not\n legal.\n Functional::Scope keeps track of variable names in a target language. It is used to translate between\n different sets of legal characters and to avoid accidentally re-defining identifiers. Users should derive a class\n from Scope and supply the following:\n \u2022 Scope takes a template argument that specifies a type that\u2019s used to uniquely distinguish variables.\n Typically this would be int (if variables are used for Functional::IR nodes) or IdString.\n \u2022 The derived class should provide a constructor that calls reserve for every reserved word in the target\n@@ -15715,28 +15718,28 @@\n \u2022 writer.push() and writer.pop() are used to automatically close s-expressions. writer.pop() closes\n all s-expressions opened since the last call to writer.push().\n \u2022 writer.comment(string) writes a comment on a separate-line. writer.comment(string, true)\n appends a comment to the last printed s-expression.\n \u2022 writer.flush() flushes any buffering and should be called before any direct access to the underlying\n std::ostream. It does not close unclosed parentheses.\n \u2022 The destructor calls flush but also closes all unclosed parentheses.\n-Example: A minimal functional backend\n-At its most basic, there are three steps we need to accomplish for a minimal functional backend.\n-First, we need to convert our design into FunctionalIR. This is most easily done by calling the\n-Functional::IR::from_module() static method with our top-level module, or iterating over and converting\n-each of the modules in our design. Second, we need to handle each of the Functional::Nodes in our design.\n-Iterating over the Functional::IR includes reading the module inputs and current state, but not writing\n-the results. So our final step is to handle the outputs and next state.\n \n 4.3. Working with the Yosys codebase\n \n 175\n \n \fYosysHQ Yosys, Version 0.52\n \n+Example: A minimal functional backend\n+At its most basic, there are three steps we need to accomplish for a minimal functional backend.\n+First, we need to convert our design into FunctionalIR. This is most easily done by calling the\n+Functional::IR::from_module() static method with our top-level module, or iterating over and converting\n+each of the modules in our design. Second, we need to handle each of the Functional::Nodes in our design.\n+Iterating over the Functional::IR includes reading the module inputs and current state, but not writing\n+the results. So our final step is to handle the outputs and next state.\n In order to add an output command to Yosys, we implement the Yosys::Backend class and provide an\n instance of it:\n Listing 4.8: Example source code for a minimal functional backend,\n dummy.cc\n # include \"kernel/functional.h\"\n # include \"kernel/yosys.h\"\n USING_YOSYS_NAMESPACE\n@@ -15758,40 +15761,42 @@\n auto ir = Functional::IR::from_module(module);\n *f << \"module \" << module->name.c_str() << \"\\n\";\n // write node functions\n for (auto node : ir)\n *f << \" assign \" << id2cstr(node.name())\n << \" = \" << node.to_string() << \"\\n\";\n *f << \"\\n\";\n-\n-\";\n-\n // write outputs and next state\n for (auto output : ir.outputs())\n *f << \" \" << id2cstr(output->kind)\n << \" \" << id2cstr(output->name)\n << \" = \" << id2cstr(output->value().name()) << \"\\n\";\n for (auto state : ir.states())\n *f << \" \" << id2cstr(state->kind)\n+(continues on next page)\n+\n+176\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n+(continued from previous page)\n+\n << \" \" << id2cstr(state->name)\n << \" = \" << id2cstr(state->next_value().name()) << \"\\n\n \n+\";\n+\n \u02d3\u2192\n \n }\n }\n } FunctionalDummyBackend;\n PRIVATE_NAMESPACE_END\n-\n-176\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n Because we are using the Backend class, our \"functional_dummy\" is registered as the\n write_functional_dummy command. The execute method is the part that runs when the user calls\n the command, handling any options, preparing the output file for writing, and iterating over selected\n modules in the design. Since we don\u2019t have any options here, we set argidx = 1 and call the extra_args()\n method. This method will read the command arguments, raising an error if there are any unexpected ones.\n It will also assign the pointer f to the output file, or stdout if none is given.\n \u00f2 Note\n@@ -15816,28 +15821,27 @@\n write_functional_smt2 output. As a result, the SMT-LIB functional backend can be used as a starting point for implementing a Rosette backend.\n Full code listings for the initial SMT-LIB backend and the converted Rosette backend are included in the\n Yosys source repository under backends/functional as smtlib.cc and smtlib_rosette.cc respectively.\n Note that the Rosette language is an extension of the Racket language; this guide tends to refer to Racket\n when talking about the underlying semantics/syntax of the language.\n The major changes from the SMT-LIB backend are as follows:\n \u2022 all of the Smt prefixes in names are replaced with Smtr to mean smtlib_rosette;\n+4.3. Working with the Yosys codebase\n+\n+177\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n \u2022 syntax is adjusted for Racket;\n \u2022 data structures for input/output/state are changed from using declare-datatype with statically typed\n fields, to using struct with no static typing;\n \u2022 the transfer function also loses its static typing;\n \u2022 sign/zero extension in Rosette use the output width instead of the number of extra bits, gaining static\n typing;\n \u2022 the single scope is traded for a global scope with local scope for each struct;\n-\n-4.3. Working with the Yosys codebase\n-\n-177\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n \u2022 initial state is provided as a constant value instead of a set of assertions;\n \u2022 and the -provides option is introduced to more easily use generated code within Rosette based applications.\n Scope\n Our first addition to the minimal backend above is that for both SMT-LIB and Rosette backends, we are\n now targetting real languages which bring with them their own sets of constraints with what we can use\n as identifiers. This is where the Functional::Scope class described above comes in; by using this class\n we can safely rename our identifiers in the generated output without worrying about collisions or illegal\n@@ -15867,37 +15871,32 @@\n }\n };\n For the reserved keywords we trade the SMT-LIB specification for Racket to prevent parts of our design\n from accidentally being treated as Racket code. We also no longer need to reserve pair, first, and second.\n In write_functional_smt2 these are used for combining the (inputs, current_state) and (outputs,\n next_state) into a single variable. Racket provides this functionality natively with cons, which we will see\n later.\n-Listing 4.10: diff of reserved_keywords list\n-const char *reserved_keywords[] = {\n-- // reserved keywords from the smtlib spec\n-- ...\n-+ // reserved keywords from the racket spec\n-+ ...\n--\n-\n-// reserved for our own purposes\n-\"pair\", \"Pair\", \"first\", \"second\",\n-(continues on next page)\n \n 178\n \n Chapter 4. Yosys internals\n \n \fYosysHQ Yosys, Version 0.52\n \n-(continued from previous page)\n-\n+Listing 4.10: diff of reserved_keywords list\n+const char *reserved_keywords[] = {\n+- // reserved keywords from the smtlib spec\n+- ...\n++ // reserved keywords from the racket spec\n++ ...\n +\n };\n \n+// reserved for our own purposes\n+\"pair\", \"Pair\", \"first\", \"second\",\n \"inputs\", \"state\",\n \"inputs\", \"state\", \"name\",\n nullptr\n \n \u00f2 Note\n We skip over the actual list of reserved keywords from both the smtlib and racket specifications to save\n on space in this document.\n@@ -15924,49 +15923,42 @@\n }\n Struct\n As we saw in the minimal backend above, the Functional::IR class tracks the set of inputs, the set of outputs, and the set of \u201cstate\u201d variables. The SMT-LIB backend maps each of these sets into its own SmtStruct,\n with each variable getting a corresponding field in the struct and a specified Sort. write_functional_smt2\n then defines each of these structs as a new datatype, with each element being strongly-typed.\n In Rosette, rather than defining new datatypes for our structs, we use the native struct. We also only\n declare each field by name because Racket provides less static typing. For ease of use, we provide the\n-expected type for each field as comments.\n-Listing 4.12: diff of write_definition method\n--\n-\n-void write_definition(SExprWriter &w) {\n-w.open(list(\"declare-datatype\", name));\n-w.open(list());\n-w.open(list(name));\n-for(const auto &field : fields)\n-(continues on next page)\n \n 4.3. Working with the Yosys codebase\n \n 179\n \n \fYosysHQ Yosys, Version 0.52\n \n-(continued from previous page)\n-\n+expected type for each field as comments.\n+Listing 4.12: diff of write_definition method\n +\n +\n +\n +\n +\n +\n +\n +\n +\n +\n +\n +\n +\n \n-}\n-\n+void write_definition(SExprWriter &w) {\n+w.open(list(\"declare-datatype\", name));\n+w.open(list());\n+w.open(list(name));\n+for(const auto &field : fields)\n w << list(field.accessor, field.sort.to_sexpr());\n w.close(3);\n vector field_list;\n for(const auto &field : fields) {\n field_list.emplace_back(field.name);\n }\n w.push();\n@@ -15974,14 +15966,15 @@\n if (field_names.size()) {\n for (const auto &field : fields) {\n auto bv_type = field.sort.to_sexpr();\n w.comment(field.name + \" \" + bv_type.to_string());\n }\n }\n w.pop();\n+}\n \n Each field is added to the SmtStruct with the insert method, which also reserves a unique name (or accessor)\n within the Scope. These accessors combine the struct name and field name and are globally unique, being\n used in the access method for reading values from the input/current state.\n Listing 4.13: Struct::access() method\n SExpr access(SExpr record, IdString name) {\n size_t i = field_names.at(name);\n@@ -16001,33 +15994,38 @@\n \u02d3\u2192scope(), name(name) {}\n +\n void insert(IdString field_name, SmtrSort sort) {\n field_names(field_name);\n auto accessor = scope.unique_name(\"\\\\\" + name + \"_\" + RTLIL::unescape_\n \u02d3\u2192id(field_name));\n fields.emplace_back(Field{sort, accessor});\n+(continues on next page)\n+\n+180\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n+(continued from previous page)\n+\n +\n-auto base_name = local_scope.unique_name(field_name);\n +\n-auto accessor = name + \"-\" + base_name;\n +\n-global_scope.reserve(accessor);\n +\n-fields.emplace_back(Field{sort, accessor, base_name});\n+\n }\n \n+auto base_name = local_scope.unique_name(field_name);\n+auto accessor = name + \"-\" + base_name;\n+global_scope.reserve(accessor);\n+fields.emplace_back(Field{sort, accessor, base_name});\n+\n Finally, SmtStruct also provides a write_value template method which calls a provided function on each\n element in the struct. This is used later for assigning values to the output/next state pair. The only change\n-\n-180\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n here is to remove the check for zero-argument constructors since this is not necessary with Rosette structs.\n Listing 4.15: diff of write_value method\n template void write_value(SExprWriter &w, Fn fn) {\n if(field_names.empty()) {\n // Zero-argument constructors in SMTLIB must not be called as\u2423\n \u02d3\u2192functions.\n w << name;\n@@ -16065,63 +16063,71 @@\n SExpr logical_shift_right(Node, Node a, Node b) override { return list(\"bvlshr\",\n \u02d3\u2192 n(a), extend(n(b), b.width(), a.width())); }\n SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list(\n \u02d3\u2192\"bvashr\", n(a), extend(n(b), b.width(), a.width())); }\n SExpr mux(Node, Node a, Node b, Node s) override { return list(\"ite\", to_\n \u02d3\u2192bool(n(s)), n(b), n(a)); }\n SExpr constant(Node, RTLIL::Const const &value) override { return smt_\n-\u02d3\u2192const(value); }\n-SExpr memory_read(Node, Node mem, Node addr) override { return list(\"select\",\u2423\n-\u02d3\u2192n(mem), n(addr)); }\n-SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list(\n-\u02d3\u2192\"store\", n(mem), n(addr), n(data)); }\n-+\n-SExpr mux(Node, Node a, Node b, Node s) override { return list(\"if\", to_\n-\u02d3\u2192bool(n(s)), n(b), n(a)); }\n-+\n-SExpr constant(Node, RTLIL::Const const& value) override { return list(\"bv\",\u2423\n-\u02d3\u2192smt_const(value), value.size()); }\n \u02d3\u2192\n \n (continues on next page)\n \n 4.3. Working with the Yosys codebase\n \n 181\n \n \fYosysHQ Yosys, Version 0.52\n \n (continued from previous page)\n \n+const(value); }\n+SExpr memory_read(Node, Node mem, Node addr) override { return list(\"select\",\u2423\n+\u02d3\u2192n(mem), n(addr)); }\n+SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list(\n+\u02d3\u2192\"store\", n(mem), n(addr), n(data)); }\n++\n+SExpr mux(Node, Node a, Node b, Node s) override { return list(\"if\", to_\n+\u02d3\u2192bool(n(s)), n(b), n(a)); }\n++\n+SExpr constant(Node, RTLIL::Const const& value) override { return list(\"bv\",\u2423\n+\u02d3\u2192smt_const(value), value.size()); }\n +\n-\n SExpr memory_read(Node, Node mem, Node addr) override { return list(\"list-ref-bv\n-\", n(mem), n(addr)); }\n+\u02d3\u2192\", n(mem), n(addr)); }\n +\n SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list(\n \u02d3\u2192\"list-set-bv\", n(mem), n(addr), n(data)); }\n \u02d3\u2192\n \n+-\n+\n However there are some differences in the two formats with regards to how booleans are handled, with\n Rosette providing built-in functions for conversion.\n Listing 4.17: portion of Functional::AbstractVisitor implementation diff showing differences\n++\n++\n+\n SExpr from_bool(SExpr &&arg) {\n return list(\"ite\", std::move(arg), \"#b1\", \"#b0\");\n return list(\"bool->bitvector\", std::move(arg));\n }\n SExpr to_bool(SExpr &&arg) {\n return list(\"=\", std::move(arg), \"#b1\");\n return list(\"bitvector->bool\", std::move(arg));\n }\n \n-+\n-+\n-\n Of note here is the rare instance of the Rosette implementation gaining static typing rather than losing it.\n Where SMT_LIB calls zero/sign extension with the number of extra bits needed (given by out_width a.width()), Rosette instead specifies the type of the output (given by list(\"bitvector\", out_width)).\n+\n+182\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n Listing 4.18: zero/sign extension implementation diff\n -\n \n SExpr zero_extend(Node, Node a, int out_width) override { return list(list(\"_\",\n \"zero_extend\", out_width - a.width()), n(a)); }\n SExpr sign_extend(Node, Node a, int out_width) override { return list(list(\"_\",\n \u02d3\u2192\"sign_extend\", out_width - a.width()), n(a)); }\n@@ -16138,55 +16144,44 @@\n backend. These are all handled by the SmtModule class, with the mapping from RTLIL module to FunctionalIR happening in the constructor. Each of the three SmtStructs; inputs, outputs, and state; are also\n created in the constructor, with each value in the corresponding lists in the IR being inserted.\n Listing 4.19: SmtModule constructor\n SmtModule(Module *module)\n : ir(Functional::IR::from_module(module))\n , scope()\n , name(scope.unique_name(module->name))\n-(continues on next page)\n-\n-182\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-(continued from previous page)\n-\n , input_struct(scope.unique_name(module->name.str() + \"_Inputs\"), scope)\n , output_struct(scope.unique_name(module->name.str() + \"_Outputs\"),\u2423\n-\n-scope)\n-\n-\u02d3\u2192\n-\n-{\n-\n-}\n-\n+\u02d3\u2192scope)\n , state_struct(scope.unique_name(module->name.str() + \"_State\"), scope)\n+{\n scope.reserve(name + \"-initial\");\n for (auto input : ir.inputs())\n input_struct.insert(input->name, input->sort);\n for (auto output : ir.outputs())\n output_struct.insert(output->name, output->sort);\n for (auto state : ir.states())\n state_struct.insert(state->name, state->sort);\n-\n+}\n Since Racket uses the - to access struct fields, the SmtrModule instead uses an underscore for the name of\n the initial state.\n Listing 4.20: diff of Module constructor\n +\n \n scope.reserve(name + \"-initial\");\n scope.reserve(name + \"_initial\");\n \n The write method is then responsible for writing the FunctionalIR to the output file, formatted for the\n corresponding backend. SmtModule::write() breaks the output file down into four parts: defining the\n three structs, declaring the pair datatype, defining the transfer function (inputs, current_state) ->\n+4.3. Working with the Yosys codebase\n+\n+183\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n (outputs, next_state) with write_eval, and declaring the initial state with write_initial. The only\n change for the SmtrModule is that the pair declaration isn\u2019t needed.\n Listing 4.21: diff of Module::write() method\n void write(std::ostream &out)\n {\n SExprWriter w(out);\n input_struct.write_definition(w);\n@@ -16201,21 +16196,14 @@\n write_eval(w);\n write_initial(w);\n }\n The write_eval method is where the FunctionalIR nodes, outputs, and next state are handled. Just\n as with the minimal backend, we iterate over the nodes with for(auto n : ir), and then use the\n Struct::write_value() method for the output_struct and state_struct to iterate over the outputs\n and next state respectively.\n-\n-4.3. Working with the Yosys codebase\n-\n-183\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n Listing 4.22:\n iterating\n SmtModule::write_eval()\n \n over\n \n FunctionalIR\n@@ -16234,19 +16222,26 @@\n The main differences between our two backends here are syntactical. First we change the define-fun for\n the Racket style define which drops the explicitly typed inputs/outputs. And then we change the final\n result from a pair to the native cons which acts in much the same way, returning both the outputs and\n the next_state in a single variable.\n Listing 4.23: diff of Module::write_eval() transfer function declaration\n +\n \n+184\n+\n w.open(list(\"define-fun\", name,\n list(list(\"inputs\", input_struct.name),\n list(\"state\", state_struct.name)),\n list(\"Pair\", output_struct.name, state_struct.name)));\n w.open(list(\"define\", list(name, \"inputs\", \"state\")));\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n Listing\n 4.24:\n diff\n Module::write_eval()\n \n of\n \n@@ -16268,41 +16263,27 @@\n \n For the write_initial method, the SMT-LIB backend uses declare-const and asserts which must always\n hold true. For Rosette we instead define the initial state as any other variable that can be used by external\n code. This variable, [name]_initial, can then be used in the [name] function call; allowing the Rosette\n code to be used in the generation of the next_state, whereas the SMT-LIB code can only verify that a\n given next_state is correct.\n Listing 4.25: diff of Module::write_initial() method\n-\n-+\n-+\n-+\n-+\n-\n void write_initial(SExprWriter &w)\n {\n std::string initial = name + \"-initial\";\n w << list(\"declare-const\", initial, state_struct.name);\n++\n w.push();\n++\n auto initial = name + \"_initial\";\n++\n w.open(list(\"define\", initial));\n++\n w.open(list(state_struct.name));\n for (auto state : ir.states()) {\n-(continues on next page)\n-\n-184\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-(continued from previous page)\n-\n--\n-\n if(state->sort.is_signal())\n w << list(\"assert\", list(\"=\", state_struct.\n \u02d3\u2192access(initial, state->name), smt_const(state->initial_value_signal())));\n else if(state->sort.is_memory()) {\n +\n if (state->sort.is_signal())\n +\n@@ -16326,14 +16307,20 @@\n w.close();\n }\n }\n +\n w.pop();\n }\n \n+4.3. Working with the Yosys codebase\n+\n+185\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n Backend\n The final part is the Backend itself, with much of the same boiler plate as the minimal backend. The main\n difference is that we use the Module to perform the actual processing.\n Listing 4.26: The FunctionalSmtBackend\n struct FunctionalSmtBackend : public Backend {\n FunctionalSmtBackend() : Backend(\"functional_smt2\", \"Generate SMT-LIB from\u2423\n \u02d3\u2192Functional IR\") {}\n@@ -16343,33 +16330,23 @@\n {\n log_header(design, \"Executing Functional SMT Backend.\\n\");\n \n \u02d3\u2192\n \n size_t argidx = 1;\n extra_args(f, filename, args, argidx, design);\n-\n-}\n-\n for (auto module : design->selected_modules()) {\n log(\"Processing module `%s`.\\n\", module->name.c_str());\n SmtModule smt(module);\n smt.write(*f);\n }\n-(continues on next page)\n-\n-4.3. Working with the Yosys codebase\n-\n-185\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-(continued from previous page)\n \n+}\n } FunctionalSmtBackend;\n+\n There are two additions here for Rosette. The first is that the output file needs to start with the #lang\n definition which tells the compiler/interpreter that we want to use the Rosette language module. The second\n is that the write_functional_rosette command takes an optional argument, -provides. If this argument\n is given, then the output file gets an additional line declaring that everything in the file should be exported\n for use; allowing the file to be treated as a Racket package with structs and mapping function available for\n use externally.\n Listing 4.27: relevant portion of diff of Backend::execute()\n@@ -16384,14 +16361,21 @@\n *f << \"(provide (all-defined-out))\\n\";\n }\n \n 4.3.4 Contributing to Yosys\n \u00f2 Note\n For information on making a pull request on github, refer to our CONTRIBUTING.md file.\n Coding Style\n+\n+186\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n Formatting of code\n \u2022 Yosys code is using tabs for indentation. Tabs are 8 characters.\n \u2022 A continuation of a statement in the following line is indented by two additional tabs.\n \u2022 Lines are as long as you want them to be. A good rule of thumb is to break lines at about column 150.\n \u2022 Opening braces can be put on the same or next line as the statement opening the block (if, switch,\n for, while, do). Put the opening brace on its own line for larger blocks, especially blocks that contains\n blank lines.\n@@ -16401,21 +16385,14 @@\n In general Yosys uses int instead of size_t. To avoid compiler warnings for implicit type casts, always use\n GetSize(foobar) instead of foobar.size(). (GetSize() is defined in kernel/yosys.h)\n Use range-based for loops whenever applicable.\n \n 4.3.5 Testing Yosys\n v Todo\n more about the included test suite and how to add tests\n-\n-186\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n Automatic testing\n The Yosys Git repo has automatic testing of builds and running of the included test suite on both Ubuntu\n and macOS, as well as across range of compiler versions. For up to date information, including OS versions,\n refer to the git actions page.\n v Todo\n are unit tests currently working\n \n@@ -16426,14 +16403,20 @@\n \u2022 Verilog parameters are used extensively to customize the internal cell types.\n \u2022 Additional special parameters are used by techmap to communicate meta-data to the map files.\n \u2022 Special wires are used to instruct techmap how to handle a module in the map file.\n \u2022 Generate blocks and recursion are powerful tools for writing map files.\n Code examples used in this document are included in the Yosys code base under docs/source/\n code_examples/techmap.\n \n+4.4. Techmap by example\n+\n+187\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n 4.4.1 Mapping OR3X1\n v Todo\n add/expand supporting text\n \n \u00f2 Note\n This is a simple example for demonstration only. Techmap shouldn\u2019t be used to implement basic logic\n optimization.\n@@ -16443,24 +16426,14 @@\n parameter A_SIGNED = 0;\n parameter A_WIDTH = 0;\n parameter Y_WIDTH = 0;\n input [A_WIDTH-1:0] A;\n output [Y_WIDTH-1:0] Y;\n function integer min;\n input integer a, b;\n-(continues on next page)\n-\n-4.4. Techmap by example\n-\n-187\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-(continued from previous page)\n-\n begin\n if (a < b)\n min = a;\n else\n min = b;\n end\n endfunction\n@@ -16478,14 +16451,24 @@\n assign Y = ybuf;\n end\n if (A_WIDTH == 3) begin\n wire ybuf;\n OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));\n assign Y = ybuf;\n end\n+(continues on next page)\n+\n+188\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n+(continued from previous page)\n+\n if (A_WIDTH > 3) begin\n localparam next_stage_sz = (A_WIDTH+2) / 3;\n wire [next_stage_sz-1:0] next_stage;\n for (i = 0; i < next_stage_sz; i = i+1) begin\n localparam bits = min(A_WIDTH - 3*i, 3);\n assign next_stage[i] = |A[3*i +: bits];\n end\n@@ -16502,16 +16485,14 @@\n \n A[3]\n \n A[4]\n \n A[5]\n \n-188\n-\n A\n B\n C\n \n A\n B\n C\n@@ -16522,33 +16503,29 @@\n Y\n \n $6.genblk0.genblk4.g\n OR3X1\n \n Y\n \n-A[6]\n-\n A\n B\n C\n \n $8.genblk0.genblk4.g\n OR3X1\n \n Y\n \n+A[6]\n+\n Y\n \n $1.genblk0.genblk5.next_stage[2]\n \n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n Listing 4.29: red_or3x1_test.ys\n read_verilog red_or3x1_test.v\n hierarchy -check -top test\n techmap -map red_or3x1_map.v;;\n splitnets -ports\n show -prefix red_or3x1 -format dot -notitle -lib red_or3x1_cells.v\n Listing 4.30: red_or3x1_test.v\n@@ -16560,27 +16537,31 @@\n \n 4.4.2 Conditional techmap\n \u2022 In some cases only cells with certain properties should be substituted.\n \u2022 The special wire _TECHMAP_FAIL_ can be used to disable a module in the map file for a certain set of\n parameters.\n \u2022 The wire _TECHMAP_FAIL_ must be set to a constant value. If it is non-zero then the module is disabled\n for this set of parameters.\n+4.4. Techmap by example\n+\n+189\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n \u2022 Example use-cases:\n \u2013 coarse-grain cell types that only operate on certain bit widths\n \u2013 memory resources for different memory geometries (width, depth, ports, etc.)\n Example:\n \n B\n \n A\n \n C\n \n-4.4. Techmap by example\n-\n A\n \n $1.g\n MYMUL\n \n B\n \n@@ -16588,23 +16569,19 @@\n B\n \n $2\n $mul\n \n Y\n \n-Y\n-\n Y1\n \n-Y2\n-\n-189\n+Y\n \n-\fYosysHQ Yosys, Version 0.52\n+Y2\n \n Listing 4.31: sym_mul_map.v\n module \\$mul (A, B, Y);\n parameter A_SIGNED = 0;\n parameter B_SIGNED = 0;\n parameter A_WIDTH = 1;\n parameter B_WIDTH = 1;\n@@ -16618,14 +16595,21 @@\n Listing 4.32: sym_mul_test.v\n module test(A, B, C, Y1, Y2);\n input\n [7:0] A, B, C;\n output [7:0] Y1 = A * B;\n output [15:0] Y2 = A * C;\n endmodule\n+\n+190\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n Listing 4.33: sym_mul_test.ys\n read_verilog sym_mul_test.v\n hierarchy -check -top test\n techmap -map sym_mul_map.v;;\n show -prefix sym_mul -format dot -notitle -lib sym_mul_cells.v\n \n 4.4.3 Scripting in map modules\n@@ -16635,21 +16619,14 @@\n that is executed as script. Then the wire is removed. Repeat.\n \u2022 You can even call techmap recursively!\n \u2022 Example use-cases:\n \u2013 Using always blocks in map module: call proc\n \u2013 Perform expensive optimizations (such as freduce ) on cells where this is known to work well.\n \u2013 Interacting with custom commands.\n \u00f2 Note\n-\n-190\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n PROTIP:\n Commands such as shell , show -pause, and dump can be used in the _TECHMAP_DO_* scripts for debugging map modules.\n Example:\n \n 2'00\n 2'00\n \n@@ -16666,19 +16643,19 @@\n S\n \n B\n \n $15\n $mux\n \n-Y\n-\n A[0]\n \n+Y\n A\n+\n 0:0 - 1:1\n \n B\n \n $10\n $add\n \n@@ -16695,14 +16672,20 @@\n \n Y\n \n Y\n \n A[1]\n \n+4.4. Techmap by example\n+\n+191\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n Listing 4.34: mymul_map.v\n module MYMUL(A, B, Y);\n parameter WIDTH = 1;\n input [WIDTH-1:0] A, B;\n output reg [WIDTH-1:0] Y;\n wire [1023:0] _TECHMAP_DO_ = \"proc; clean\";\n integer i;\n@@ -16717,24 +16700,14 @@\n module test(A, B, Y);\n input [1:0] A, B;\n output [1:0] Y = A * B;\n endmodule\n Listing 4.36: mymul_test.ys\n read_verilog mymul_test.v\n hierarchy -check -top test\n-(continues on next page)\n-\n-4.4. Techmap by example\n-\n-191\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-(continued from previous page)\n-\n techmap -map sym_mul_map.v \\\n -map mymul_map.v;;\n rename test test_mapped\n read_verilog mymul_test.v\n miter -equiv test test_mapped miter\n flatten miter\n sat -verify -prove trigger 0 miter\n@@ -16744,14 +16717,21 @@\n 4.4.4 Handling constant inputs\n \u2022 The special parameters _TECHMAP_CONSTMSK__ and _TECHMAP_CONSTVAL__\n can be used to handle constant input values to cells.\n \u2022 The former contains 1-bits for all constant input bits on the port.\n \u2022 The latter contains the constant bits or undef (x) for non-constant bits.\n \u2022 Example use-cases:\n \u2013 Converting arithmetic (for example multiply to shift).\n+\n+192\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n \u2013 Identify constant addresses or enable bits in memory interfaces.\n Example:\n \n 4:0 - 7:3\n A\n A\n 8'00000110\n@@ -16770,24 +16750,14 @@\n X\n \n Listing 4.37: mulshift_map.v\n module MYMUL(A, B, Y);\n parameter WIDTH = 1;\n input [WIDTH-1:0] A, B;\n output reg [WIDTH-1:0] Y;\n-(continues on next page)\n-\n-192\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-(continued from previous page)\n-\n parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;\n parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;\n reg _TECHMAP_FAIL_;\n wire [1023:0] _TECHMAP_DO_ = \"proc; clean\";\n integer i;\n always @* begin\n _TECHMAP_FAIL_ <= 1;\n@@ -16801,14 +16771,24 @@\n Y <= A << i;\n end\n end\n end\n endmodule\n Listing 4.38: mulshift_test.v\n module test (A, X, Y);\n+(continues on next page)\n+\n+4.4. Techmap by example\n+\n+193\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n+(continued from previous page)\n+\n input [7:0] A;\n output [7:0] X = A * 8'd 6;\n output [7:0] Y = A * 8'd 8;\n endmodule\n Listing 4.39: mulshift_test.ys\n read_verilog mulshift_test.v\n hierarchy -check -top test\n@@ -16829,31 +16809,26 @@\n \n in\n \n the\n \n \u2022 The numbers 0-3 are reserved for 0, 1, x, and z respectively.\n \u2022 Example use-cases:\n-\n-4.4. Techmap by example\n-\n-193\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n \u2013 Detecting shared clock or control signals in memory interfaces.\n \u2013 In some cases this can be used for for optimization.\n Example:\n \n B\n \n A\n \n 1\n \n+194\n+\n A\n B\n \n A\n B\n \n $1\n@@ -16866,14 +16841,18 @@\n $5\n $shl\n \n Y\n \n Y\n \n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n Listing 4.40: addshift_map.v\n module \\$add (A, B, Y);\n parameter A_SIGNED = 0;\n parameter B_SIGNED = 0;\n parameter A_WIDTH = 1;\n parameter B_WIDTH = 1;\n parameter Y_WIDTH = 1;\n@@ -16887,24 +16866,14 @@\n _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;\n assign Y = A << 1;\n endmodule\n Listing 4.41: addshift_test.v\n module test (A, B, X, Y);\n input [7:0] A, B;\n output [7:0] X = A + B;\n-(continues on next page)\n-\n-194\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-(continued from previous page)\n-\n output [7:0] Y = A + A;\n endmodule\n Listing 4.42: addshift_test.ys\n read_verilog addshift_test.v\n hierarchy -check -top test\n techmap -map addshift_map.v;;\n show -prefix addshift -format dot -notitle\n@@ -16914,14 +16883,20 @@\n \u2022 You can use the $__-prefix for internal cell types to avoid collisions with the user-namespace. But\n always use two underscores or the internal consistency checker will trigger on these cells.\n \u2022 Techmap has two major use cases:\n \u2013 Creating good logic-level representation of arithmetic functions. This also means using dedicated\n hardware resources such as half- and full-adder cells in ASICS or dedicated carry logic in FPGAs.\n \u2013 Mapping of coarse-grain resources such as block memory or DSP cells.\n \n+4.4. Techmap by example\n+\n+195\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n 4.5 Notes on Verilog support in Yosys\n v Todo\n how much of this is specific to the read_verilog and should be in The Verilog and AST frontends?\n \n 4.5.1 Unsupported Verilog-2005 Features\n The following Verilog-2005 features are not supported by Yosys and there are currently no plans to add\n support for them:\n@@ -16933,21 +16908,14 @@\n 4.5.2 Verilog Attributes and non-standard features\n \u2022 The full_case attribute on case statements is supported (also the non-standard // synopsys\n full_case directive)\n \u2022 The parallel_case attribute on case statements is supported (also the non-standard // synopsys\n parallel_case directive)\n \u2022 The // synopsys translate_off and // synopsys translate_on directives are also supported (but\n the use of ` `ifdef .. `endif ` is strongly recommended instead).\n-\n-4.5. Notes on Verilog support in Yosys\n-\n-195\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n \u2022 The nomem2reg attribute on modules or arrays prohibits the automatic early conversion of arrays to\n separate registers. This is potentially dangerous. Usually the front-end has good reasons for converting\n an array to a list of registers. Prohibiting this step will likely result in incorrect synthesis results.\n \u2022 The mem2reg attribute on modules or arrays forces the early conversion of arrays to separate registers.\n \u2022 The nomeminit attribute on modules or arrays prohibits the creation of initialized memories. This\n effectively puts mem2reg on all memories that are written to in an initial block and are not ROMs.\n \u2022 The nolatches attribute on modules or always-blocks prohibits the generation of logic-loops for latches.\n@@ -16962,14 +16930,21 @@\n \u2022 The onehot attribute on wires mark them as one-hot state register. This is used for example for\n memory port sharing and set by the fsm_map pass.\n \u2022 The blackbox attribute on modules is used to mark empty stub modules that have the same ports\n as the real thing but do not contain information on the internal configuration. This modules are only\n used by the synthesis passes to identify input and output ports of cells. The Verilog backend also\n does not output blackbox modules on default. read_verilog , unless called with -noblackbox will\n automatically set the blackbox attribute on any empty module it reads.\n+\n+196\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n \u2022 The noblackbox attribute set on an empty module prevents read_verilog from automatically setting\n the blackbox attribute on the module.\n \u2022 The whitebox attribute on modules triggers the same behavior as blackbox, but is for whitebox\n modules, i.e. library modules that contain a behavioral model of the cell type.\n \u2022 The lib_whitebox attribute overwrites whitebox when read_verilog is run in -lib mode. Otherwise\n it\u2019s automatically removed.\n \u2022 The dynports attribute is used by the Verilog front-end to mark modules that have ports with a width\n@@ -16984,21 +16959,14 @@\n \u2022 The keep_hierarchy attribute on cells and modules keeps the flatten command from flattening the\n indicated cells and modules.\n \u2022 The gate_cost_equivalent attribute on a module can be used to specify the estimated cost of the\n module as a number of basic gate instances. See the help message of command keep_hierarchy which\n interprets this attribute.\n \u2022 The init attribute on wires is set by the frontend when a register is initialized \u201cFPGA-style\u201d with\n reg foo = val. It can be used during synthesis to add the necessary reset logic.\n-\n-196\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n \u2022 The top attribute on a module marks this module as the top of the design hierarchy. The hierarchy\n command sets this attribute when called with -top. Other commands, such as flatten and various\n backends use this attribute to determine the top module.\n \u2022 The src attribute is set on cells and wires created by to the string :\n by the HDL front-end and is then carried through the synthesis. When entities are combined, a new\n |-separated string is created that contains all the strings from the original entities.\n \u2022 The defaultvalue attribute is used to store default values for module inputs. The attribute is attached\n@@ -17014,14 +16982,21 @@\n by the clkbufmap pass.\n \u2022 The clkbuf_inv attribute can be set on an output port of a module with the value set to the name\n of an input port of that module. When the clkbufmap would otherwise insert a clock buffer on this\n output, it will instead try inserting the clock buffer on the input port (this is used to implement clock\n inverter cells that clock buffer insertion will \u201csee through\u201d).\n \u2022 The clkbuf_inhibit is the default attribute to set on a wire to prevent automatic clock buffer insertion\n by clkbufmap . This behaviour can be overridden by providing a custom selection to clkbufmap .\n+\n+4.5. Notes on Verilog support in Yosys\n+\n+197\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n \u2022 The invertible_pin attribute can be set on a port to mark it as invertible via a cell parameter. The\n name of the inversion parameter is specified as the value of this attribute. The value of the inversion\n parameter must be of the same width as the port, with 1 indicating an inverted bit and 0 indicating a\n non-inverted bit.\n \u2022 The iopad_external_pin attribute on a blackbox module\u2019s port marks it as the external-facing pin\n of an I/O pad, and prevents iopadmap from inserting another pad cell on it.\n \u2022 The module attribute abc9_lut is an integer attribute indicating to abc9 that this module describes\n@@ -17034,21 +17009,14 @@\n \u2022 The module attribute abc9_flop is a boolean marking the module as a flip-flop. This allows abc9 to\n analyse its contents in order to perform sequential synthesis.\n \u2022 The frontend sets attributes always_comb, always_latch and always_ff on processes derived from\n SystemVerilog style always blocks according to the type of the always. These are checked for correctness\n in proc_dlatch.\n \u2022 The cell attribute wildcard_port_conns represents wildcard port connections (SystemVerilog .*).\n These are resolved to concrete connections to matching wires in hierarchy .\n-\n-4.5. Notes on Verilog support in Yosys\n-\n-197\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n \u2022 In addition to the (* ... *) attribute syntax, Yosys supports the non-standard {* ... *} attribute\n syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset by\n adding an empty {* *} statement.)\n \u2022 In module parameter and port declarations, and cell port and parameter lists, a trailing comma is\n ignored. This simplifies writing Verilog code generators a bit in some cases.\n \u2022 Modules can be declared with module mod_name(...); (with three dots instead of a list of module\n ports). With this syntax it is sufficient to simply declare a module port as \u2018input\u2019 or \u2018output\u2019 in the\n@@ -17066,14 +17034,24 @@\n or function is unused in this case and can be used to specify a behavioral model of the cell type for\n simulation. For example:\n module my_add3(A, B, C, Y);\n parameter WIDTH = 8;\n input [WIDTH-1:0] A, B, C;\n output [WIDTH-1:0] Y;\n ...\n+(continues on next page)\n+\n+198\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n+(continued from previous page)\n+\n endmodule\n module top;\n ...\n (* via_celltype = \"my_add3 Y\" *)\n (* via_celltype_defparam_WIDTH = 32 *)\n function [31:0] add3;\n input [31:0] A, B, C;\n@@ -17087,21 +17065,14 @@\n type identifier.\n \u2022 Various enum_value_{value} attributes are added to wires of an enumerated type to give a map of\n possible enum items to their values.\n \u2022 The enum_base_type attribute is added to enum items to indicate which enum they belong to (enums\n \u2013 anonymous and otherwise \u2013 are automatically named with an auto-incrementing counter). Note that\n enums are currently not strongly typed.\n \u2022 A limited subset of DPI-C functions is supported. The plugin mechanism (see help plugin) can\n-\n-198\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n be used to load .so files with implementations of DPI-C routines. As a non-standard extension it is\n possible to specify a plugin alias using the : syntax. For example:\n module dpitest;\n import \"DPI-C\" function foo:round = real my_round (real);\n parameter real r = my_round(12.345);\n endmodule\n $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'\n@@ -17116,14 +17087,21 @@\n to enable this functionality. (By default these blocks are ignored.)\n \u2022 The reprocess_after internal attribute is used by the Verilog frontend to mark cells with bindings\n which might depend on the specified instantiated module. Modules with such cells will be reprocessed\n during the hierarchy pass once the referenced module definition(s) become available.\n \u2022 The smtlib2_module attribute can be set on a blackbox module to specify a formal model directly\n using SMT-LIB 2. For such a module, the smtlib2_comb_expr attribute can be used on output ports\n to define their value using an SMT-LIB 2 expression. For example:\n+\n+4.5. Notes on Verilog support in Yosys\n+\n+199\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n (* blackbox *)\n (* smtlib2_module *)\n module submod(a, b);\n input [7:0] a;\n (* smtlib2_comb_expr = \"(bvnot a)\" *)\n output [7:0] b;\n endmodule\n@@ -17137,21 +17115,14 @@\n \u2022 The system function $anyseq evaluates to any value, possibly a different value in each cycle. This is\n equivalent to declaring a reg as rand, but also works outside of checkers. (Yosys also supports rand\n variables outside checkers.)\n \u2022 The system functions $allconst and $allseq can be used to construct formal exist-forall problems.\n Assumptions only hold if the trace satisfies the assumption for all $allconst/$allseq values. For\n assertions and cover statements it is sufficient if just one $allconst/$allseq value triggers the property\n (similar to $anyconst/$anyseq).\n-\n-4.5. Notes on Verilog support in Yosys\n-\n-199\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n \u2022 Wires/registers declared using the anyconst/anyseq/allconst/allseq attribute (for example (*\n anyconst *) reg [7:0] foobar;) will behave as if driven by a $anyconst/$anyseq/$allconst/\n $allseq function.\n \u2022 The SystemVerilog tasks $past, $stable, $rose and $fell are supported in any clocked block.\n \u2022 The syntax @($global_clock) can be used to create FFs that have no explicit clock input ($ff\n cells). The same can be achieved by using @(posedge ) or @(negedge ) when\n is marked with the (* gclk *) Verilog attribute.\n@@ -17167,14 +17138,21 @@\n \u2022 Declaring free variables with rand and rand const is supported.\n \u2022 Checkers without a port list that do not need to be instantiated (but instead behave like a named\n block) are supported.\n \u2022 SystemVerilog packages are supported. Once a SystemVerilog file is read into a design with\n read_verilog , all its packages are available to SystemVerilog files being read into the same design\n afterwards.\n \u2022 typedefs are supported (including inside packages)\n+\n+200\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n \u2013 type casts are currently not supported\n \u2022 enums are supported (including inside packages)\n \u2013 but are currently not strongly typed\n \u2022 packed structs and unions are supported\n \u2013 arrays of packed structs/unions are currently not supported\n \u2013 structure literals are currently not supported\n \u2022 multidimensional arrays are supported\n@@ -17185,20 +17163,14 @@\n \u2022 Assignments within expressions are supported.\n \n 4.6 Hashing and associative data structures in Yosys\n 4.6.1 Container classes based on hashing\n Yosys uses dict and pool as main container classes. dict is essentially a replacement\n for std::unordered_map and pool is a replacement for std::unordered_set. The main\n characteristics are:\n-200\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n \u2022 dict and pool are about 2x faster than the std containers\n (though this claim hasn\u2019t been verified for over 10 years)\n \u2022 references to elements in a dict or pool are invalidated by\n insert and remove operations (similar to std::vector on push_back()).\n \u2022 some iterators are invalidated by erase(). specifically, iterators\n that have not passed the erased element yet are invalidated. (erase() itself returns valid iterator\n to the next element.)\n@@ -17213,22 +17185,33 @@\n \u2022 dict and pool will have the same order of iteration across\n all compilers, standard libraries and architectures.\n In addition to dict and pool there is also an idict that creates a bijective map from K to\n the integers. For example:\n idict si;\n log(\"%d\\n\", si(\"hello\"));\n log(\"%d\\n\", si(\"world\"));\n+\n+// will print 42\n+// will print 43\n+(continues on next page)\n+\n+4.6. Hashing and associative data structures in Yosys\n+\n+201\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n+(continued from previous page)\n+\n log(\"%d\\n\", si.at(\"world\"));\n log(\"%d\\n\", si.at(\"dummy\"));\n log(\"%s\\n\", si[42].c_str()));\n log(\"%s\\n\", si[43].c_str()));\n log(\"%s\\n\", si[44].c_str()));\n \n-// will print 42\n-// will print 43\n // will print 43\n // will throw exception\n // will print hello\n // will print world\n // will throw exception\n \n It is not possible to remove elements from an idict.\n@@ -17245,20 +17228,14 @@\n patterns within Yosys. In general, a good hash function typically folds values into a state accumulator with\n a mathematical function that is fast to compute and has some beneficial properties. One of these is the\n avalanche property, which demands that a small change such as flipping a bit or incrementing by one in the\n input produces a large, unpredictable change in the output. Additionally, the bit independence criterion\n states that any pair of output bits should change independently when any single input bit is inverted. These\n properties are important for avoiding hash collision on data patterns like the hash of a sequence not colliding\n with its permutation, not losing from the state the information added by hashing preceding elements, etc.\n-4.6. Hashing and associative data structures in Yosys\n-\n-201\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n DJB2 lacks these properties. Instead, since Yosys hashes large numbers of data structures composed of\n incrementing integer IDs, Yosys abuses the predictability of DJB2 to get lower hash collisions, with regular\n nature of the hashes surviving through the interaction with the \u201cmodulo prime\u201d operations in the associative\n data structures. For example, some most common objects in Yosys are interned IdStrings of incrementing\n indices or SigBits with bit offsets into wire (represented by its unique IdString name) as the typical case.\n This is what makes DJB2 a local optimum. Additionally, the ADD version of DJB2 (like above but with\n addition instead of XOR) is used to this end for some types, abandoning the general pattern of folding values\n@@ -17274,14 +17251,21 @@\n By default it pulls the Hasher h through a Hasher\n T::hash_into(Hasher h) method. That\u2019s the method you have to implement to make a record (class\n or struct) type easily hashable with Yosys hashlib associative data structures.\n hash_ops is specialized for built-in types like int or bool and treats pointers the same as integers, so it\n doesn\u2019t dereference pointers. Since many RTLIL data structures like RTLIL::Wire carry their own unique\n index Hasher::hash_t hashidx_;, there are specializations for hash_ops and others in kernel/\n hashlib.h that actually dereference the pointers and call hash_into on the instances pointed to.\n+\n+202\n+\n+Chapter 4. Yosys internals\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n hash_ops is also specialized for simple compound types like std::pair by calling hash_into in\n sequence on its members. For flexible size containers like std::vector the size of the container is hashed\n first. That is also how implementing hashing for a custom record data type should be - unless there is strong\n reason to do otherwise, call h.eat(m) on the Hasher h you have received for each member in sequence and\n return h;.\n The hash_ops::hash(obj) method is not indended to be called when context of implementing\n the hashing for a record or other compound type.\n@@ -17300,24 +17284,14 @@\n unsigned int T::hash() const {\n return mkhash(a, b);\n }\n # elif YS_HASHING_VERSION == 1\n Hasher T::hash_into(Hasher h) const {\n h.eat(a);\n h.eat(b);\n-(continues on next page)\n-\n-202\n-\n-Chapter 4. Yosys internals\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-(continued from previous page)\n-\n return h;\n }\n Hasher T::hash() const {\n Hasher h;\n h.eat(*this);\n return h;\n }\n@@ -18415,15 +18389,20 @@\n Replacement args:\n --cxx\n g++\n --cxxflags\n -g -O2 -flto=auto -ffat-lto-objects \\\n -fstack-protector-strong -Wformat -Werror=format-security \\\n -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP \\\n--D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\n+-D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=@CXXFLAGS@.52 \\\n+-DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 \\\n+-std=c++17 -O3 -DYOSYS_ENABLE_READLINE \\\n+-DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB \\\n+-DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 \\\n+-DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER\n --linkflags\n -rdynamic\n --ldflags\n (alias of --linkflags)\n --libs\n -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6\n --ldlibs\n@@ -18435,25 +18414,25 @@\n All other args are passed through as they are.\n Use --exec to call a command instead of generating output. Example usage:\n ./yosys-config --exec --cxx --cxxflags --ldflags -o plugin.so -shared plugin.cc --libs\n The above command can be abbreviated as:\n ./yosys-config --build plugin.so plugin.cc\n Use --prefix to change the prefix for the special args from '--' to\n something else. Example:\n-./yosys-config --prefix @ bindir: @bindir\n-The args --bindir and --datdir can be directly followed by a slash and\n-additional text. Example:\n (continues on next page)\n \n 225\n \n \fYosysHQ Yosys, Version 0.52\n \n (continued from previous page)\n \n+./yosys-config --prefix @ bindir: @bindir\n+The args --bindir and --datdir can be directly followed by a slash and\n+additional text. Example:\n ./yosys-config --datdir/simlib.v\n \n 8.2 yosys-filterlib\n v Todo\n how does a filterlib rules-file work?\n The yosys-filterlib tool is a small utility that can be used to strip or extract information from a Liberty\n file. This can be useful for removing sensitive or proprietary information such as timing or other trade\n@@ -18489,29 +18468,25 @@\n -T type\n specify output type (blif_mv (default), blif_mvs, blif, or none)\n -x\n equivalent to '-t none -T none'\n -b\n running in bridge mode\n \n-8.4 yosys-smtbmc\n-The yosys-smtbmc tool is a utility used by SBY for interacting with smt solvers.\n-yosys-smtbmc [options] \n--h, --help\n-show this message\n-(continues on next page)\n-\n 226\n \n Chapter 8. Auxiliary programs\n \n \fYosysHQ Yosys, Version 0.52\n \n-(continued from previous page)\n-\n+8.4 yosys-smtbmc\n+The yosys-smtbmc tool is a utility used by SBY for interacting with smt solvers.\n+yosys-smtbmc [options] \n+-h, --help\n+show this message\n -t \n -t :\n -t ::\n default: skip_steps=0, step_size=1, num_steps=20\n -g\n \n -i\n@@ -18539,30 +18514,30 @@\n the AIGER witness file does not include the status and\n properties lines.\n --yw \n read a Yosys witness.\n --btorwit \n read a BTOR witness.\n --noinfo\n-only run the core proof, do not collect and print any\n-additional information (e.g. which assert failed)\n---presat\n-check if the design with assumptions but without assertions\n-is SAT before checking if assertions are UNSAT. This will\n-detect if there are contradicting assumptions. In some cases\n (continues on next page)\n \n 8.4. yosys-smtbmc\n \n 227\n \n \fYosysHQ Yosys, Version 0.52\n \n (continued from previous page)\n \n+only run the core proof, do not collect and print any\n+additional information (e.g. which assert failed)\n+--presat\n+check if the design with assumptions but without assertions\n+is SAT before checking if assertions are UNSAT. This will\n+detect if there are contradicting assumptions. In some cases\n this will also help to \"warm up\" the solver, potentially\n yielding a speedup.\n --final-only\n only check final constraints, assume base case\n --assume-skipped \n assume asserts in skipped steps in BMC.\n no assumptions are created for skipped steps\n@@ -18588,30 +18563,30 @@\n file and only dump object below in design hierarchy.\n --noinit\n do not assume initial conditions in state 0\n --dump-all\n when using -g or -i, create a dump file for each\n step. The character '%' is replaced in all dump\n filenames with the step number.\n---append \n-add time steps at the end of the trace\n-when creating a counter example (this additional time\n-steps will still be constrained by assumptions)\n---binary\n-dump anyconst values as raw bit strings\n (continues on next page)\n \n 228\n \n Chapter 8. Auxiliary programs\n \n \fYosysHQ Yosys, Version 0.52\n \n (continued from previous page)\n \n+--append \n+add time steps at the end of the trace\n+when creating a counter example (this additional time\n+steps will still be constrained by assumptions)\n+--binary\n+dump anyconst values as raw bit strings\n --keep-going\n continue BMC after the first failed assertion and report\n further failed assertions. To output multiple traces\n covering all found failed assertions, the character '%' is\n replaced in all dump filenames with an increasing number.\n In cover mode, don't stop when a cover trace contains a failed\n assertion.\n@@ -18638,29 +18613,30 @@\n --timeout \n set the solver timeout to the specified value (in seconds).\n --logic \n use the specified SMT2 logic (e.g. QF_AUFBV)\n --dummy \n if solver is \"dummy\", read solver output from that file\n otherwise: write solver output to that file\n---smt2-option