{"diffoscope-json-version": 1, "source1": "/srv/reproducible-results/rbuild-debian/r-b-build.s8cIxkN4/b1/yosys_0.52-2_arm64.changes", "source2": "/srv/reproducible-results/rbuild-debian/r-b-build.s8cIxkN4/b2/yosys_0.52-2_arm64.changes", "unified_diff": null, "details": [{"source1": "Files", "source2": "Files", "unified_diff": "@@ -1,7 +1,7 @@\n \n  cc58ad4d0dd9c1154d23cd9481deaa8a 28658780 debug optional yosys-abc-dbgsym_0.52-2_arm64.deb\n  6e1ef3ece5cf566e1c7dd85217c069a0 4374380 electronics optional yosys-abc_0.52-2_arm64.deb\n  7bf67feff5251d616723fa376c3b9c9e 89838704 debug optional yosys-dbgsym_0.52-2_arm64.deb\n  db5292a30a762d1da687f6e8e6846ab5 136256 electronics optional yosys-dev_0.52-2_arm64.deb\n- 8d726db0d1b62dcab385e2d0f70ac1df 2915268 doc optional yosys-doc_0.52-2_all.deb\n+ 4453b5af5874561e9f9ef72e3347ca5d 2915592 doc optional yosys-doc_0.52-2_all.deb\n  66fc1b5429db24c3b7a25b76682413f0 5358264 electronics optional yosys_0.52-2_arm64.deb\n"}, {"source1": "yosys-doc_0.52-2_all.deb", "source2": "yosys-doc_0.52-2_all.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r--   0        0        0        4 2025-05-04 16:37:33.000000 debian-binary\n -rw-r--r--   0        0        0      888 2025-05-04 16:37:33.000000 control.tar.xz\n--rw-r--r--   0        0        0  2914188 2025-05-04 16:37:33.000000 data.tar.xz\n+-rw-r--r--   0        0        0  2914512 2025-05-04 16:37:33.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,13 +1,13 @@\n drwxr-xr-x   0 root         (0) root         (0)        0 2025-05-04 16:37:33.000000 ./\n drwxr-xr-x   0 root         (0) root         (0)        0 2025-05-04 16:37:33.000000 ./usr/\n drwxr-xr-x   0 root         (0) root         (0)        0 2025-05-04 16:37:33.000000 ./usr/share/\n drwxr-xr-x   0 root         (0) root         (0)        0 2025-05-04 16:37:33.000000 ./usr/share/doc/\n drwxr-xr-x   0 root         (0) root         (0)        0 2025-05-04 16:37:33.000000 ./usr/share/doc/yosys/\n--rw-r--r--   0 root         (0) root         (0)  3059965 2025-05-04 16:37:33.000000 ./usr/share/doc/yosys/yosyshqyosys.pdf\n+-rw-r--r--   0 root         (0) root         (0)  3059892 2025-05-04 16:37:33.000000 ./usr/share/doc/yosys/yosyshqyosys.pdf\n drwxr-xr-x   0 root         (0) root         (0)        0 2025-05-04 16:37:33.000000 ./usr/share/doc/yosys-doc/\n -rw-r--r--   0 root         (0) root         (0)     2906 2025-05-04 16:37:33.000000 ./usr/share/doc/yosys-doc/changelog.Debian.gz\n -rw-r--r--   0 root         (0) root         (0)    18593 2025-04-09 05:38:42.000000 ./usr/share/doc/yosys-doc/changelog.gz\n -rw-r--r--   0 root         (0) root         (0)    23698 2025-04-11 09:16:27.000000 ./usr/share/doc/yosys-doc/copyright\n drwxr-xr-x   0 root         (0) root         (0)        0 2025-05-04 16:37:33.000000 ./usr/share/doc-base/\n -rw-r--r--   0 root         (0) root         (0)      245 2023-08-27 13:27:37.000000 ./usr/share/doc-base/yosys-doc.yosys-manual\n lrwxrwxrwx   0 root         (0) root         (0)        0 2025-05-04 16:37:33.000000 ./usr/share/doc/yosys/manual.pdf -> yosyshqyosys.pdf\n"}, {"source1": "./usr/share/doc/yosys/yosyshqyosys.pdf", "source2": "./usr/share/doc/yosys/yosyshqyosys.pdf", "unified_diff": null, "details": [{"source1": "pdftotext {} -", "source2": "pdftotext {} -", "unified_diff": "@@ -541,27 +541,27 @@\n 10.286xilinx_srl - Xilinx shift register extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610\n 10.287xprop - formal x propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610\n 10.288zinit - add inverters so all FF are zero-initialized . . . . . . . . . . . . . . . . . . . . . . . . . 611\n Bibliography\n \n 613\n \n-Internal cell reference\n+Property Index\n \n 615\n \n-Property Index\n+Internal cell reference\n \n-619\n+617\n \n-Tag Index\n+Command Reference\n \n 621\n \n-Command Reference\n+Tag Index\n \n 625\n \n ix\n \n \fx\n \n@@ -43531,14 +43531,127 @@\n interconnect synthesis for heterogeneous coarse-grain reconfigurable logic. In FDL Proceeding of\n the 2012 Forum on Specification and Design Languages, 194\u2013201. 2012.\n \n 614\n \n Bibliography\n \n+\fPROPERTY INDEX\n+\n+is_\n+is_evaluable, 390\n+$alu, 287\n+$fa, 288\n+$lcu, 289\n+$macc, 290\n+$macc_v2, 293\n+$add, 240\n+$and, 241\n+$bweqx, 242\n+$div, 242\n+$divfloor, 243\n+$eq, 244\n+$eqx, 244\n+$ge, 245\n+$gt, 245\n+$le, 246\n+$logic_and, 247\n+$logic_or, 247\n+$lt, 248\n+$mod, 248\n+$modfloor, 249\n+$mul, 250\n+$ne, 251\n+$nex, 251\n+$or, 252\n+$pow, 252\n+$shift, 253\n+$shiftx, 254\n+$shl, 255\n+$shr, 255\n+$sshl, 256\n+$sshr, 256\n+$sub, 257\n+$xnor, 258\n+$xor, 258\n+$_ANDNOT_, 317\n+$_AOI3_, 318\n+$_AOI4_, 318\n+$_MUX16_, 319\n+$_MUX4_, 320\n+$_MUX8_, 320\n+\n+$_NMUX_, 321\n+$_OAI3_, 321\n+$_OAI4_, 322\n+$_ORNOT_, 323\n+$_AND_, 313\n+$_BUF_, 313\n+$_MUX_, 314\n+$_NAND_, 314\n+$_NOR_, 314\n+$_NOT_, 315\n+$_OR_, 315\n+$_XNOR_, 316\n+$_XOR_, 316\n+$allconst, 302\n+$allseq, 302\n+$anyconst, 302\n+$anyseq, 303\n+$assert, 304\n+$assume, 304\n+$cover, 304\n+$equiv, 305\n+$fair, 305\n+$initstate, 306\n+$live, 306\n+$_TBUF_, 389\n+$lut, 295\n+$sop, 296\n+$bmux, 259\n+$bwmux, 260\n+$demux, 260\n+$mux, 261\n+$pmux, 261\n+$tribuf, 262\n+$specify2, 297\n+$specify3, 298\n+$specrule, 301\n+$buf, 234\n+$logic_not, 234\n+$neg, 235\n+$not, 235\n+$pos, 236\n+$reduce_and, 236\n+\n+615\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n+$reduce_bool, 237\n+$reduce_or, 237\n+$reduce_xnor, 238\n+$reduce_xor, 238\n+$concat, 311\n+$slice, 312\n+\n+xx-aware, 390\n+$bweqx, 242\n+$eqx, 244\n+$nex, 251\n+x-output, 390\n+$div, 242\n+$mod, 248\n+$shiftx, 254\n+$pmux, 261\n+\n+616\n+\n+Property Index\n+\n \fINTERNAL CELL REFERENCE\n \n Internal cell\n $alu, 287\n $fa, 288\n $lcu, 289\n $macc, 290\n@@ -43619,15 +43732,15 @@\n $sop, 296\n $mem, 276\n $mem_v2, 278\n $meminit, 281\n $meminit_v2, 282\n $memrd, 282\n \n-615\n+617\n \n \fYosysHQ Yosys, Version 0.52\n \n $memrd_v2, 283\n $memwr, 283\n $memwr_v2, 284\n $bmux, 259\n@@ -43677,15 +43790,15 @@\n $_DFFE_PN0P_, 337\n $_DFFE_PN1N_, 337\n $_DFFE_PN1P_, 337\n $_DFFE_PN_, 338\n $_DFFE_PP0N_, 338\n $_DFFE_PP0P_, 339\n $_DFFE_PP1N_, 339\n-616\n+618\n \n $_DFFE_PP1P_, 340\n $_DFFE_PP_, 340\n $_DFFSRE_NNNN_, 340\n $_DFFSRE_NNNP_, 341\n $_DFFSRE_NNPN_, 342\n $_DFFSRE_NNPP_, 342\n@@ -43800,134 +43913,334 @@\n $reduce_bool, 237\n $reduce_or, 237\n $reduce_xnor, 238\n $reduce_xor, 238\n $concat, 311\n $slice, 312\n \n-617\n+619\n \n \fYosysHQ Yosys, Version 0.52\n \n-618\n+620\n \n Internal cell reference\n \n-\fPROPERTY INDEX\n+\fCOMMAND REFERENCE\n \n-is_\n-is_evaluable, 390\n-$alu, 287\n-$fa, 288\n-$lcu, 289\n-$macc, 290\n-$macc_v2, 293\n-$add, 240\n-$and, 241\n-$bweqx, 242\n-$div, 242\n-$divfloor, 243\n-$eq, 244\n-$eqx, 244\n-$ge, 245\n-$gt, 245\n-$le, 246\n-$logic_and, 247\n-$logic_or, 247\n-$lt, 248\n-$mod, 248\n-$modfloor, 249\n-$mul, 250\n-$ne, 251\n-$nex, 251\n-$or, 252\n-$pow, 252\n-$shift, 253\n-$shiftx, 254\n-$shl, 255\n-$shr, 255\n-$sshl, 256\n-$sshr, 256\n-$sub, 257\n-$xnor, 258\n-$xor, 258\n-$_ANDNOT_, 317\n-$_AOI3_, 318\n-$_AOI4_, 318\n-$_MUX16_, 319\n-$_MUX4_, 320\n-$_MUX8_, 320\n+Command\n+abc, 393\n+abc9, 396\n+abc9_exe, 399\n+abc9_ops, 401\n+abc_new, 403\n+abstract, 404\n+add, 405\n+aigmap, 406\n+alumacc, 406\n+anlogic_eqn, 406\n+anlogic_fixcarry, 407\n+assertpmux, 407\n+async2sync, 407\n+attrmap, 407\n+attrmvcp, 408\n+autoname, 409\n+blackbox, 409\n+bmuxmap, 409\n+booth, 409\n+box_derive, 410\n+bufnorm, 410\n+bugpoint, 412\n+bwmuxmap, 413\n+cd, 413\n+cellmatch, 414\n+check, 414\n+chformal, 415\n+chparam, 416\n+chtype, 416\n+clean, 416\n+clean_zerowidth, 417\n+clk2fflogic, 417\n+clkbufmap, 417\n+clockgate, 418\n+connect, 419\n+connect_rpc, 419\n+connwrappers, 420\n+coolrunner2_fixup, 421\n+coolrunner2_sop, 421\n+copy, 421\n+cover, 421\n \n-$_NMUX_, 321\n-$_OAI3_, 321\n-$_OAI4_, 322\n-$_ORNOT_, 323\n-$_AND_, 313\n-$_BUF_, 313\n-$_MUX_, 314\n-$_NAND_, 314\n-$_NOR_, 314\n-$_NOT_, 315\n-$_OR_, 315\n-$_XNOR_, 316\n-$_XOR_, 316\n-$allconst, 302\n-$allseq, 302\n-$anyconst, 302\n-$anyseq, 303\n-$assert, 304\n-$assume, 304\n-$cover, 304\n-$equiv, 305\n-$fair, 305\n-$initstate, 306\n-$live, 306\n-$_TBUF_, 389\n-$lut, 295\n-$sop, 296\n-$bmux, 259\n-$bwmux, 260\n-$demux, 260\n-$mux, 261\n-$pmux, 261\n-$tribuf, 262\n-$specify2, 297\n-$specify3, 298\n-$specrule, 301\n-$buf, 234\n-$logic_not, 234\n-$neg, 235\n-$not, 235\n-$pos, 236\n-$reduce_and, 236\n+cutpoint, 422\n+debug, 422\n+delete, 423\n+deminout, 423\n+demuxmap, 423\n+design, 423\n+dffinit, 425\n+dfflegalize, 425\n+dfflibmap, 426\n+dffunmap, 427\n+dft_tag, 427\n+dump, 428\n+echo, 428\n+edgetypes, 428\n+efinix_fixcarry, 429\n+equiv_add, 429\n+equiv_induct, 429\n+equiv_make, 430\n+equiv_mark, 430\n+equiv_miter, 430\n+equiv_opt, 431\n+equiv_purge, 432\n+equiv_remove, 432\n+equiv_simple, 433\n+equiv_status, 433\n+equiv_struct, 433\n+eval, 434\n+example_dt, 434\n+exec, 435\n+expose, 435\n+extract, 436\n+extract_counter, 438\n+extract_fa, 438\n+extract_reduce, 439\n+extractinv, 439\n+flatten, 439\n+flowmap, 440\n+fmcombine, 441\n+fminit, 442\n+formalff, 442\n+freduce, 443\n+fsm, 444\n \n-619\n+621\n \n \fYosysHQ Yosys, Version 0.52\n \n-$reduce_bool, 237\n-$reduce_or, 237\n-$reduce_xnor, 238\n-$reduce_xor, 238\n-$concat, 311\n-$slice, 312\n+fsm_detect, 444\n+fsm_expand, 445\n+fsm_export, 445\n+fsm_extract, 446\n+fsm_info, 446\n+fsm_map, 446\n+fsm_opt, 446\n+fsm_recode, 446\n+fst2tb, 447\n+future, 448\n+gatemate_foldinv, 448\n+glift, 448\n+greenpak4_dffinv, 450\n+help, 450\n+hierarchy, 450\n+hilomap, 452\n+history, 452\n+ice40_braminit, 452\n+ice40_dsp, 453\n+ice40_opt, 453\n+ice40_wrapcarry, 453\n+insbuf, 454\n+internal_stats, 454\n+iopadmap, 454\n+jny, 455\n+json, 455\n+keep_hierarchy, 456\n+lattice_gsr, 456\n+libcache, 457\n+license, 457\n+log, 458\n+logger, 458\n+ls, 459\n+ltp, 459\n+lut2mux, 460\n+maccmap, 460\n+memory, 460\n+memory_bmux2rom, 460\n+memory_bram, 461\n+memory_collect, 463\n+memory_dff, 463\n+memory_libmap, 463\n+memory_map, 464\n+memory_memx, 464\n+memory_narrow, 465\n+memory_nordff, 465\n+memory_share, 465\n+memory_unpack, 465\n+microchip_dffopt, 466\n+microchip_dsp, 466\n+miter, 466\n+mutate, 467\n+muxcover, 469\n+muxpack, 469\n+622\n \n-xx-aware, 390\n-$bweqx, 242\n-$eqx, 244\n-$nex, 251\n-x-output, 390\n-$div, 242\n-$mod, 248\n-$shiftx, 254\n-$pmux, 261\n+nlutmap, 470\n+nx_carry, 470\n+onehot, 470\n+opt, 470\n+opt_clean, 471\n+opt_demorgan, 471\n+opt_dff, 472\n+opt_expr, 472\n+opt_ffinv, 473\n+opt_lut, 473\n+opt_lut_ins, 473\n+opt_mem, 474\n+opt_mem_feedback, 474\n+opt_mem_priority, 474\n+opt_mem_widen, 475\n+opt_merge, 475\n+opt_muxtree, 475\n+opt_reduce, 475\n+opt_share, 476\n+paramap, 476\n+peepopt, 477\n+plugin, 477\n+pmux2shiftx, 478\n+pmuxtree, 478\n+portarcs, 478\n+portlist, 479\n+prep, 479\n+printattrs, 480\n+proc, 481\n+proc_arst, 481\n+proc_clean, 482\n+proc_dff, 482\n+proc_dlatch, 482\n+proc_init, 482\n+proc_memwr, 483\n+proc_mux, 483\n+proc_prune, 483\n+proc_rmdead, 483\n+proc_rom, 483\n+qbfsat, 484\n+ql_bram_merge, 485\n+ql_bram_types, 485\n+ql_dsp_io_regs, 485\n+ql_dsp_macc, 486\n+ql_dsp_simd, 486\n+ql_ioff, 486\n+read, 486\n+read_aiger, 487\n+read_blif, 488\n+read_json, 488\n+read_liberty, 488\n+read_rtlil, 489\n+read_verilog, 490\n+read_verilog_file_list, 493\n+Command Reference\n \n-620\n+\fYosysHQ Yosys, Version 0.52\n \n-Property Index\n+read_xaiger2, 493\n+recover_names, 494\n+rename, 494\n+rmports, 495\n+sat, 495\n+scatter, 499\n+scc, 499\n+scratchpad, 500\n+script, 500\n+select, 501\n+setattr, 505\n+setenv, 506\n+setparam, 506\n+setundef, 506\n+share, 507\n+shell, 507\n+show, 508\n+shregmap, 510\n+sim, 511\n+simplemap, 513\n+splice, 514\n+splitcells, 514\n+splitnets, 515\n+sta, 515\n+stat, 515\n+submod, 516\n+supercover, 517\n+synth, 517\n+synth_achronix, 519\n+synth_anlogic, 520\n+synth_coolrunner2, 522\n+synth_easic, 524\n+synth_ecp5, 525\n+synth_efinix, 529\n+synth_fabulous, 530\n+synth_gatemate, 534\n+synth_gowin, 537\n+synth_greenpak4, 539\n+synth_ice40, 541\n+synth_intel, 544\n+synth_intel_alm, 547\n+synth_lattice, 549\n+synth_microchip, 553\n+synth_nanoxplore, 556\n+synth_nexus, 559\n+synth_quicklogic, 562\n+synth_sf2, 565\n+synth_xilinx, 567\n+synthprop, 571\n+tcl, 571\n+techmap, 572\n+tee, 575\n+test_abcloop, 575\n+test_autotb, 576\n+Command Reference\n+\n+test_cell, 576\n+test_generic, 578\n+test_pmgen, 578\n+torder, 578\n+trace, 579\n+tribuf, 579\n+uniquify, 579\n+verific, 580\n+verilog_defaults, 582\n+verilog_defines, 582\n+viz, 583\n+wbflip, 584\n+wrapcell, 584\n+wreduce, 585\n+write_aiger, 585\n+write_aiger2, 586\n+write_blif, 586\n+write_btor, 588\n+write_cxxrtl, 588\n+write_edif, 593\n+write_file, 594\n+write_firrtl, 594\n+write_functional_cxx, 594\n+write_functional_rosette, 595\n+write_functional_smt2, 595\n+write_intersynth, 595\n+write_jny, 595\n+write_json, 596\n+write_rtlil, 601\n+write_simplec, 601\n+write_smt2, 602\n+write_smv, 605\n+write_spice, 605\n+write_table, 606\n+write_verilog, 606\n+write_xaiger, 608\n+write_xaiger2, 608\n+xilinx_dffopt, 609\n+xilinx_dsp, 609\n+xilinx_srl, 610\n+xprop, 610\n+zinit, 611\n+\n+623\n+\n+\fYosysHQ Yosys, Version 0.52\n+\n+624\n+\n+Command Reference\n \n \fTAG INDEX\n \n abc (cmd/abc), 393\n abc9 (cmd/abc9 ), 396\n abc9_exe (cmd/abc9_exe), 399\n abc9_ops (cmd/abc9_ops), 401\n@@ -44009,15 +44322,15 @@\n fmcombine (cmd/fmcombine), 441\n fminit (cmd/fminit), 442\n formalff (cmd/formalff ), 442\n freduce (cmd/freduce), 443\n fsm (cmd/fsm), 444\n fsm_detect (cmd/fsm_detect), 444\n \n-621\n+625\n \n \fYosysHQ Yosys, Version 0.52\n \n fsm_expand (cmd/fsm_expand), 445\n fsm_export (cmd/fsm_export), 445\n fsm_extract (cmd/fsm_extract), 446\n fsm_info (cmd/fsm_info), 446\n@@ -44067,15 +44380,15 @@\n microchip_dffopt (cmd/microchip_dffopt), 466\n microchip_dsp (cmd/microchip_dsp), 466\n miter (cmd/miter), 466\n mutate (cmd/mutate), 467\n muxcover (cmd/muxcover), 469\n muxpack (cmd/muxpack), 469\n nlutmap (cmd/nlutmap), 470\n-622\n+626\n \n nx_carry (cmd/nx_carry), 470\n onehot (cmd/onehot), 470\n opt (cmd/opt), 470\n opt_clean (cmd/opt_clean), 471\n opt_demorgan (cmd/opt_demorgan), 471\n opt_dff (cmd/opt_dff ), 472\n@@ -44230,323 +44543,10 @@\n write_xaiger2 (cmd/write_xaiger2 ), 608\n xilinx_dffopt (cmd/xilinx_dffopt), 609\n xilinx_dsp (cmd/xilinx_dsp), 609\n xilinx_srl (cmd/xilinx_srl), 610\n xprop (cmd/xprop), 610\n zinit (cmd/zinit), 611\n \n-623\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-624\n-\n-Tag Index\n-\n-\fCOMMAND REFERENCE\n-\n-Command\n-abc, 393\n-abc9, 396\n-abc9_exe, 399\n-abc9_ops, 401\n-abc_new, 403\n-abstract, 404\n-add, 405\n-aigmap, 406\n-alumacc, 406\n-anlogic_eqn, 406\n-anlogic_fixcarry, 407\n-assertpmux, 407\n-async2sync, 407\n-attrmap, 407\n-attrmvcp, 408\n-autoname, 409\n-blackbox, 409\n-bmuxmap, 409\n-booth, 409\n-box_derive, 410\n-bufnorm, 410\n-bugpoint, 412\n-bwmuxmap, 413\n-cd, 413\n-cellmatch, 414\n-check, 414\n-chformal, 415\n-chparam, 416\n-chtype, 416\n-clean, 416\n-clean_zerowidth, 417\n-clk2fflogic, 417\n-clkbufmap, 417\n-clockgate, 418\n-connect, 419\n-connect_rpc, 419\n-connwrappers, 420\n-coolrunner2_fixup, 421\n-coolrunner2_sop, 421\n-copy, 421\n-cover, 421\n-\n-cutpoint, 422\n-debug, 422\n-delete, 423\n-deminout, 423\n-demuxmap, 423\n-design, 423\n-dffinit, 425\n-dfflegalize, 425\n-dfflibmap, 426\n-dffunmap, 427\n-dft_tag, 427\n-dump, 428\n-echo, 428\n-edgetypes, 428\n-efinix_fixcarry, 429\n-equiv_add, 429\n-equiv_induct, 429\n-equiv_make, 430\n-equiv_mark, 430\n-equiv_miter, 430\n-equiv_opt, 431\n-equiv_purge, 432\n-equiv_remove, 432\n-equiv_simple, 433\n-equiv_status, 433\n-equiv_struct, 433\n-eval, 434\n-example_dt, 434\n-exec, 435\n-expose, 435\n-extract, 436\n-extract_counter, 438\n-extract_fa, 438\n-extract_reduce, 439\n-extractinv, 439\n-flatten, 439\n-flowmap, 440\n-fmcombine, 441\n-fminit, 442\n-formalff, 442\n-freduce, 443\n-fsm, 444\n-\n-625\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-fsm_detect, 444\n-fsm_expand, 445\n-fsm_export, 445\n-fsm_extract, 446\n-fsm_info, 446\n-fsm_map, 446\n-fsm_opt, 446\n-fsm_recode, 446\n-fst2tb, 447\n-future, 448\n-gatemate_foldinv, 448\n-glift, 448\n-greenpak4_dffinv, 450\n-help, 450\n-hierarchy, 450\n-hilomap, 452\n-history, 452\n-ice40_braminit, 452\n-ice40_dsp, 453\n-ice40_opt, 453\n-ice40_wrapcarry, 453\n-insbuf, 454\n-internal_stats, 454\n-iopadmap, 454\n-jny, 455\n-json, 455\n-keep_hierarchy, 456\n-lattice_gsr, 456\n-libcache, 457\n-license, 457\n-log, 458\n-logger, 458\n-ls, 459\n-ltp, 459\n-lut2mux, 460\n-maccmap, 460\n-memory, 460\n-memory_bmux2rom, 460\n-memory_bram, 461\n-memory_collect, 463\n-memory_dff, 463\n-memory_libmap, 463\n-memory_map, 464\n-memory_memx, 464\n-memory_narrow, 465\n-memory_nordff, 465\n-memory_share, 465\n-memory_unpack, 465\n-microchip_dffopt, 466\n-microchip_dsp, 466\n-miter, 466\n-mutate, 467\n-muxcover, 469\n-muxpack, 469\n-626\n-\n-nlutmap, 470\n-nx_carry, 470\n-onehot, 470\n-opt, 470\n-opt_clean, 471\n-opt_demorgan, 471\n-opt_dff, 472\n-opt_expr, 472\n-opt_ffinv, 473\n-opt_lut, 473\n-opt_lut_ins, 473\n-opt_mem, 474\n-opt_mem_feedback, 474\n-opt_mem_priority, 474\n-opt_mem_widen, 475\n-opt_merge, 475\n-opt_muxtree, 475\n-opt_reduce, 475\n-opt_share, 476\n-paramap, 476\n-peepopt, 477\n-plugin, 477\n-pmux2shiftx, 478\n-pmuxtree, 478\n-portarcs, 478\n-portlist, 479\n-prep, 479\n-printattrs, 480\n-proc, 481\n-proc_arst, 481\n-proc_clean, 482\n-proc_dff, 482\n-proc_dlatch, 482\n-proc_init, 482\n-proc_memwr, 483\n-proc_mux, 483\n-proc_prune, 483\n-proc_rmdead, 483\n-proc_rom, 483\n-qbfsat, 484\n-ql_bram_merge, 485\n-ql_bram_types, 485\n-ql_dsp_io_regs, 485\n-ql_dsp_macc, 486\n-ql_dsp_simd, 486\n-ql_ioff, 486\n-read, 486\n-read_aiger, 487\n-read_blif, 488\n-read_json, 488\n-read_liberty, 488\n-read_rtlil, 489\n-read_verilog, 490\n-read_verilog_file_list, 493\n-Command Reference\n-\n-\fYosysHQ Yosys, Version 0.52\n-\n-read_xaiger2, 493\n-recover_names, 494\n-rename, 494\n-rmports, 495\n-sat, 495\n-scatter, 499\n-scc, 499\n-scratchpad, 500\n-script, 500\n-select, 501\n-setattr, 505\n-setenv, 506\n-setparam, 506\n-setundef, 506\n-share, 507\n-shell, 507\n-show, 508\n-shregmap, 510\n-sim, 511\n-simplemap, 513\n-splice, 514\n-splitcells, 514\n-splitnets, 515\n-sta, 515\n-stat, 515\n-submod, 516\n-supercover, 517\n-synth, 517\n-synth_achronix, 519\n-synth_anlogic, 520\n-synth_coolrunner2, 522\n-synth_easic, 524\n-synth_ecp5, 525\n-synth_efinix, 529\n-synth_fabulous, 530\n-synth_gatemate, 534\n-synth_gowin, 537\n-synth_greenpak4, 539\n-synth_ice40, 541\n-synth_intel, 544\n-synth_intel_alm, 547\n-synth_lattice, 549\n-synth_microchip, 553\n-synth_nanoxplore, 556\n-synth_nexus, 559\n-synth_quicklogic, 562\n-synth_sf2, 565\n-synth_xilinx, 567\n-synthprop, 571\n-tcl, 571\n-techmap, 572\n-tee, 575\n-test_abcloop, 575\n-test_autotb, 576\n-Command Reference\n-\n-test_cell, 576\n-test_generic, 578\n-test_pmgen, 578\n-torder, 578\n-trace, 579\n-tribuf, 579\n-uniquify, 579\n-verific, 580\n-verilog_defaults, 582\n-verilog_defines, 582\n-viz, 583\n-wbflip, 584\n-wrapcell, 584\n-wreduce, 585\n-write_aiger, 585\n-write_aiger2, 586\n-write_blif, 586\n-write_btor, 588\n-write_cxxrtl, 588\n-write_edif, 593\n-write_file, 594\n-write_firrtl, 594\n-write_functional_cxx, 594\n-write_functional_rosette, 595\n-write_functional_smt2, 595\n-write_intersynth, 595\n-write_jny, 595\n-write_json, 596\n-write_rtlil, 601\n-write_simplec, 601\n-write_smt2, 602\n-write_smv, 605\n-write_spice, 605\n-write_table, 606\n-write_verilog, 606\n-write_xaiger, 608\n-write_xaiger2, 608\n-xilinx_dffopt, 609\n-xilinx_dsp, 609\n-xilinx_srl, 610\n-xprop, 610\n-zinit, 611\n-\n 627\n \n \f\n"}]}]}]}]}]}