Diff of the two buildlogs: -- --- b1/build.log 2025-04-28 15:32:04.973826157 +0000 +++ b2/build.log 2025-04-28 18:01:24.515641207 +0000 @@ -1,6 +1,6 @@ I: pbuilder: network access will be disabled during build -I: Current time: Mon Apr 28 00:31:20 -12 2025 -I: pbuilder-time-stamp: 1745843480 +I: Current time: Tue Apr 29 05:38:35 +14 2025 +I: pbuilder-time-stamp: 1745854715 I: Building the build Environment I: extracting base tarball [/var/cache/pbuilder/unstable-reproducible-base.tgz] I: copying local configuration @@ -42,52 +42,84 @@ dpkg-source: info: applying 0031-Set-pythonpath-for-usage-docs.patch I: Not using root during the build. I: Installing the build-deps -I: user script /srv/workspace/pbuilder/7386/tmp/hooks/D02_print_environment starting +I: user script /srv/workspace/pbuilder/8277/tmp/hooks/D01_modify_environment starting +debug: Running on virt32b. +I: Changing host+domainname to test build reproducibility +I: Adding a custom variable just for the fun of it... +I: Changing /bin/sh to bash +'/bin/sh' -> '/bin/bash' +lrwxrwxrwx 1 root root 9 Apr 28 15:38 /bin/sh -> /bin/bash +I: Setting pbuilder2's login shell to /bin/bash +I: Setting pbuilder2's GECOS to second user,second room,second work-phone,second home-phone,second other +I: user script /srv/workspace/pbuilder/8277/tmp/hooks/D01_modify_environment finished +I: user script /srv/workspace/pbuilder/8277/tmp/hooks/D02_print_environment starting I: set - BUILDDIR='/build/reproducible-path' - BUILDUSERGECOS='first user,first room,first work-phone,first home-phone,first other' - BUILDUSERNAME='pbuilder1' - BUILD_ARCH='armhf' - DEBIAN_FRONTEND='noninteractive' - DEB_BUILD_OPTIONS='buildinfo=+all reproducible=+all parallel=3 ' - DISTRIBUTION='unstable' - HOME='/root' - HOST_ARCH='armhf' + BASH=/bin/sh + BASHOPTS=checkwinsize:cmdhist:complete_fullquote:extquote:force_fignore:globasciiranges:globskipdots:hostcomplete:interactive_comments:patsub_replacement:progcomp:promptvars:sourcepath + BASH_ALIASES=() + BASH_ARGC=() + BASH_ARGV=() + BASH_CMDS=() + BASH_LINENO=([0]="12" [1]="0") + BASH_LOADABLES_PATH=/usr/local/lib/bash:/usr/lib/bash:/opt/local/lib/bash:/usr/pkg/lib/bash:/opt/pkg/lib/bash:. + BASH_SOURCE=([0]="/tmp/hooks/D02_print_environment" [1]="/tmp/hooks/D02_print_environment") + BASH_VERSINFO=([0]="5" [1]="2" [2]="37" [3]="1" [4]="release" [5]="arm-unknown-linux-gnueabihf") + BASH_VERSION='5.2.37(1)-release' + BUILDDIR=/build/reproducible-path + BUILDUSERGECOS='second user,second room,second work-phone,second home-phone,second other' + BUILDUSERNAME=pbuilder2 + BUILD_ARCH=armhf + DEBIAN_FRONTEND=noninteractive + DEB_BUILD_OPTIONS='buildinfo=+all reproducible=+all parallel=4 ' + DIRSTACK=() + DISTRIBUTION=unstable + EUID=0 + FUNCNAME=([0]="Echo" [1]="main") + GROUPS=() + HOME=/root + HOSTNAME=i-capture-the-hostname + HOSTTYPE=arm + HOST_ARCH=armhf IFS=' ' - INVOCATION_ID='ca4635d914da4ed4a3c5ee9a9351eb77' - LANG='C' - LANGUAGE='en_US:en' - LC_ALL='C' - MAIL='/var/mail/root' - OPTIND='1' - PATH='/usr/sbin:/usr/bin:/sbin:/bin:/usr/games' - PBCURRENTCOMMANDLINEOPERATION='build' - PBUILDER_OPERATION='build' - PBUILDER_PKGDATADIR='/usr/share/pbuilder' - PBUILDER_PKGLIBDIR='/usr/lib/pbuilder' - PBUILDER_SYSCONFDIR='/etc' - PPID='7386' - PS1='# ' - PS2='> ' + INVOCATION_ID=248292d6c5e8452caa5e063309db6ca3 + LANG=C + LANGUAGE=it_CH:it + LC_ALL=C + MACHTYPE=arm-unknown-linux-gnueabihf + MAIL=/var/mail/root + OPTERR=1 + OPTIND=1 + OSTYPE=linux-gnueabihf + PATH=/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/i/capture/the/path + PBCURRENTCOMMANDLINEOPERATION=build + PBUILDER_OPERATION=build + PBUILDER_PKGDATADIR=/usr/share/pbuilder + PBUILDER_PKGLIBDIR=/usr/lib/pbuilder + PBUILDER_SYSCONFDIR=/etc + PIPESTATUS=([0]="0") + POSIXLY_CORRECT=y + PPID=8277 PS4='+ ' - PWD='/' - SHELL='/bin/bash' - SHLVL='2' - SUDO_COMMAND='/usr/bin/timeout -k 18.1h 18h /usr/bin/ionice -c 3 /usr/bin/nice /usr/sbin/pbuilder --build --configfile /srv/reproducible-results/rbuild-debian/r-b-build.iZeLzV7K/pbuilderrc_kQ1n --distribution unstable --hookdir /etc/pbuilder/first-build-hooks --debbuildopts -b --basetgz /var/cache/pbuilder/unstable-reproducible-base.tgz --buildresult /srv/reproducible-results/rbuild-debian/r-b-build.iZeLzV7K/b1 --logfile b1/build.log yosys_0.52-1.dsc' - SUDO_GID='114' - SUDO_UID='108' - SUDO_USER='jenkins' - TERM='unknown' - TZ='/usr/share/zoneinfo/Etc/GMT+12' - USER='root' - _='/usr/bin/systemd-run' - http_proxy='http://10.0.0.15:3142/' + PWD=/ + SHELL=/bin/bash + SHELLOPTS=braceexpand:errexit:hashall:interactive-comments:posix + SHLVL=3 + SUDO_COMMAND='/usr/bin/timeout -k 24.1h 24h /usr/bin/ionice -c 3 /usr/bin/nice -n 11 /usr/bin/unshare --uts -- /usr/sbin/pbuilder --build --configfile /srv/reproducible-results/rbuild-debian/r-b-build.iZeLzV7K/pbuilderrc_Ywud --distribution unstable --hookdir /etc/pbuilder/rebuild-hooks --debbuildopts -b --basetgz /var/cache/pbuilder/unstable-reproducible-base.tgz --buildresult /srv/reproducible-results/rbuild-debian/r-b-build.iZeLzV7K/b2 --logfile b2/build.log yosys_0.52-1.dsc' + SUDO_GID=112 + SUDO_UID=106 + SUDO_USER=jenkins + TERM=unknown + TZ=/usr/share/zoneinfo/Etc/GMT-14 + UID=0 + USER=root + _='I: set' + http_proxy=http://10.0.0.15:3142/ I: uname -a - Linux virt64a 6.1.0-34-arm64 #1 SMP Debian 6.1.135-1 (2025-04-25) aarch64 GNU/Linux + Linux i-capture-the-hostname 6.1.0-34-armmp-lpae #1 SMP Debian 6.1.135-1 (2025-04-25) armv7l GNU/Linux I: ls -l /bin lrwxrwxrwx 1 root root 7 Mar 4 11:20 /bin -> usr/bin -I: user script /srv/workspace/pbuilder/7386/tmp/hooks/D02_print_environment finished +I: user script /srv/workspace/pbuilder/8277/tmp/hooks/D02_print_environment finished -> Attempting to satisfy build-dependencies -> Creating pbuilder-satisfydepends-dummy package Package: pbuilder-satisfydepends-dummy @@ -528,7 +560,7 @@ Get: 329 http://deb.debian.org/debian unstable/main armhf texlive-publishers all 2024.20250309-2 [22.8 MB] Get: 330 http://deb.debian.org/debian unstable/main armhf texlive-science all 2024.20250309-2 [3937 kB] Get: 331 http://deb.debian.org/debian unstable/main armhf txt2man all 1.7.1-4 [35.4 kB] -Fetched 1066 MB in 19s (57.3 MB/s) +Fetched 1066 MB in 17s (61.1 MB/s) Preconfiguring packages ... Selecting previously unselected package libsystemd-shared:armhf. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 19565 files and directories currently installed.) @@ -1609,8 +1641,8 @@ Setting up tzdata (2025b-2) ... Current default time zone: 'Etc/UTC' -Local time is now: Mon Apr 28 12:36:02 UTC 2025. -Universal Time is now: Mon Apr 28 12:36:02 UTC 2025. +Local time is now: Mon Apr 28 15:41:52 UTC 2025. +Universal Time is now: Mon Apr 28 15:41:52 UTC 2025. Run 'dpkg-reconfigure tzdata' if you wish to change it. Setting up liberror-perl (0.17030-1) ... @@ -1933,7 +1965,11 @@ Building tag database... -> Finished parsing the build-deps I: Building the package -I: Running cd /build/reproducible-path/yosys-0.52/ && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games" HOME="/nonexistent/first-build" dpkg-buildpackage -us -uc -b && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games" HOME="/nonexistent/first-build" dpkg-genchanges -S > ../yosys_0.52-1_source.changes +I: user script /srv/workspace/pbuilder/8277/tmp/hooks/A99_set_merged_usr starting +Not re-configuring usrmerge for unstable +I: user script /srv/workspace/pbuilder/8277/tmp/hooks/A99_set_merged_usr finished +hostname: Name or service not known +I: Running cd /build/reproducible-path/yosys-0.52/ && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/i/capture/the/path" HOME="/nonexistent/second-build" dpkg-buildpackage -us -uc -b && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/i/capture/the/path" HOME="/nonexistent/second-build" dpkg-genchanges -S > ../yosys_0.52-1_source.changes dpkg-buildpackage: info: source package yosys dpkg-buildpackage: info: source version 0.52-1 dpkg-buildpackage: info: source distribution unstable @@ -1944,7 +1980,7 @@ debian/rules clean PREFIX=/usr dh clean --with=python3 dh_auto_clean - make -j3 clean + make -j4 clean make[1]: Entering directory '/build/reproducible-path/yosys-0.52' rm -rf share rm -rf kernel/*.pyh @@ -1967,50 +2003,50 @@ make -C source/code_examples/extensions clean make -C source/code_examples/fifo clean make -C source/code_examples/intro clean +make -C source/code_examples/macc clean make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/extensions' rm -f *.d *.so *.dot make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/fifo' rm -f *.dot make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' rm -f *.dot +make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' +rm -f *.dot make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/extensions' -make -C source/code_examples/macc clean +make -C source/code_examples/opt clean rm -f fifo.out fifo.stat make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/fifo' -make -C source/code_examples/opt clean make -C source/code_examples/scrambler clean -make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' -rm -f *.dot +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/fifo' +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' rm -f *.dot -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' make -C source/code_examples/selections clean make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' rm -f *.dot -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' make -C source/code_examples/show clean make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' rm -rf *.dot make -C source/code_examples/stubnets clean +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' +make -C source/code_examples/synth_flow clean make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/show' rm -rf *.dot make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/stubnets' rm -f test1.log test2.log test3.log -rm -f stubnets.so stubnets.d rm -f sumprod.out +make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' +rm -f stubnets.so stubnets.d +rm -f *.dot +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' rm -f example.out +make -C source/code_examples/techmap clean make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/stubnets' -make -C source/code_examples/synth_flow clean -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/show' -make -C source/code_examples/techmap clean -make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' -rm -f *.dot make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/techmap' -rm -f *.dot make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' +rm -f *.dot make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/techmap' rm -rf build/* rm -rf source/cmd util/__pycache__ @@ -2077,25 +2113,25 @@ debian/rules override_dh_auto_build-arch make[1]: Entering directory '/build/reproducible-path/yosys-0.52' dh_auto_build -- all - make -j3 "INSTALL=install --strip-program=true" all + make -j4 "INSTALL=install --strip-program=true" all make[2]: Entering directory '/build/reproducible-path/yosys-0.52' [Makefile.conf] CONFIG := gcc [Makefile.conf] STRIP=: rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc mkdir -p kernel/ -mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90)\"; }" > kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f90.cc g++ -o kernel/driver.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/driver.cc +mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90)\"; }" > kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f90.cc mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simlib.v > techlibs/common/simlib_help.inc.new -'abc' comes from a tarball. Continuing. mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simcells.v > techlibs/common/simcells_help.inc.new -mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc +'abc' comes from a tarball. Continuing. mkdir -p kernel/ g++ -o kernel/rtlil.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/rtlil.cc -mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc +mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc mkdir -p kernel/ g++ -o kernel/log.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_SRC='"./"' kernel/log.cc +mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc mkdir -p kernel/ g++ -o kernel/calc.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/calc.cc mkdir -p kernel/ @@ -2308,8 +2344,6 @@ g++ -o passes/cmds/example_dt.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/example_dt.cc mkdir -p passes/cmds/ g++ -o passes/cmds/portarcs.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/portarcs.cc -mkdir -p passes/cmds/ -g++ -o passes/cmds/wrapcell.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/wrapcell.cc In file included from ./kernel/yosys.h:42, from ./kernel/timinginfo.h:24, from passes/cmds/portarcs.cc:21: @@ -2329,6 +2363,8 @@ | long unsigned int | %u mkdir -p passes/cmds/ +g++ -o passes/cmds/wrapcell.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/wrapcell.cc +mkdir -p passes/cmds/ g++ -o passes/cmds/setenv.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setenv.cc mkdir -p passes/cmds/ g++ -o passes/cmds/abstract.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/abstract.cc @@ -2637,8 +2673,8 @@ mkdir -p backends/rtlil/ g++ -o backends/rtlil/rtlil_backend.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/rtlil/rtlil_backend.cc mkdir -p backends/simplec/ -mkdir -p backends/smt2/ g++ -o backends/simplec/simplec.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/simplec/simplec.cc +mkdir -p backends/smt2/ g++ -o backends/smt2/smt2.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smt2/smt2.cc mkdir -p backends/smv/ g++ -o backends/smv/smv.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smv/smv.cc @@ -2741,7 +2777,7 @@ mkdir -p techlibs/xilinx/ && python3 passes/pmgen/pmgen.py -o techlibs/xilinx/xilinx_dsp_cascade_pm.h -p xilinx_dsp_cascade techlibs/xilinx/xilinx_dsp_cascade.pmg mkdir -p techlibs/xilinx/ g++ -o techlibs/xilinx/xilinx_srl.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/xilinx_srl.cc -sed -e 's#@CXXFLAGS@#-g -O2 -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=#;' \ +sed -e 's#@CXXFLAGS@#-g -O2 -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\0.52\ -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER#;' \ -e 's#@CXX@#g++#;' -e 's#@LINKFLAGS@#-rdynamic#;' -e 's#@LIBS@#-lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6#;' \ -e 's#@BINDIR@#/usr/bin#;' -e 's#@DATDIR@#/usr/share/yosys#;' < misc/yosys-config.in > yosys-config chmod +x yosys-config @@ -2874,8 +2910,8 @@ mkdir -p share/anlogic cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v mkdir -p share/anlogic -mkdir -p share/anlogic cp "./"/techlibs/anlogic/lutrams.txt share/anlogic/lutrams.txt +mkdir -p share/anlogic cp "./"/techlibs/anlogic/lutrams_map.v share/anlogic/lutrams_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/brams.txt share/anlogic/brams.txt @@ -2890,12 +2926,12 @@ mkdir -p share cp "./"/techlibs/common/smtmap.v share/smtmap.v mkdir -p share -mkdir -p share cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v -cp "./"/techlibs/common/adff2dff.v share/adff2dff.v mkdir -p share +cp "./"/techlibs/common/adff2dff.v share/adff2dff.v mkdir -p share cp "./"/techlibs/common/dff2ff.v share/dff2ff.v +mkdir -p share cp "./"/techlibs/common/gate2lut.v share/gate2lut.v mkdir -p share cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v @@ -2932,12 +2968,12 @@ mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh mkdir -p share/ecp5 -mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh -cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v mkdir -p share/ecp5 +cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v +mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v @@ -2954,12 +2990,12 @@ mkdir -p share/ecp5 cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v mkdir -p share/efinix -mkdir -p share/efinix cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v -cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v mkdir -p share/efinix +cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v +mkdir -p share/efinix cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v @@ -2998,16 +3034,17 @@ mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v mkdir -p share/gatemate -mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt +mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh mkdir -p share/gatemate cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v mkdir -p techlibs/gatemate -mkdir -p share/gowin python3 techlibs/gatemate/make_lut_tree_lib.py +touch techlibs/gatemate/lut_tree_lib.mk +mkdir -p share/gowin cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v @@ -3025,26 +3062,25 @@ cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt mkdir -p share/gowin cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v -touch techlibs/gatemate/lut_tree_lib.mk mkdir -p share/gowin -mkdir -p share/greenpak4 cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt -cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v mkdir -p share/greenpak4 +cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v -cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v mkdir -p share/greenpak4 +cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v +mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v mkdir -p share/greenpak4 -mkdir -p share/ice40 cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib +mkdir -p share/ice40 cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v @@ -3071,58 +3107,58 @@ mkdir -p share/intel/common cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v mkdir -p share/intel/common -mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt +mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v mkdir -p share/intel/common -mkdir -p share/intel/max10 cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v +mkdir -p share/intel/max10 cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v mkdir -p share/intel/cyclone10lp -mkdir -p share/intel/cycloneiv cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v +mkdir -p share/intel/cycloneiv cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v mkdir -p share/intel/cycloneive cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v mkdir -p share/intel/max10 -cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v mkdir -p share/intel/cyclone10lp +cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v mkdir -p share/intel/cycloneiv -cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v mkdir -p share/intel/cycloneive +cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v mkdir -p share/intel_alm/common -cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v mkdir -p share/intel_alm/common +cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v mkdir -p share/intel_alm/common -cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v mkdir -p share/intel_alm/common +cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v mkdir -p share/intel_alm/common -cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v mkdir -p share/intel_alm/common +cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v mkdir -p share/intel_alm/common -cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v mkdir -p share/intel_alm/common +cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v mkdir -p share/intel_alm/common -cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v mkdir -p share/intel_alm/common +cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v mkdir -p share/intel_alm/common -cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v mkdir -p share/intel_alm/common +cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v mkdir -p share/intel_alm/cyclonev -cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v mkdir -p share/intel_alm/common +cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt mkdir -p share/intel_alm/common -cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v mkdir -p share/intel_alm/common +cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v @@ -3143,8 +3179,8 @@ mkdir -p share/lattice cp "./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v mkdir -p share/lattice -mkdir -p share/lattice cp "./"/techlibs/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3.v +mkdir -p share/lattice cp "./"/techlibs/lattice/cells_sim_xo3d.v share/lattice/cells_sim_xo3d.v mkdir -p share/lattice cp "./"/techlibs/lattice/cells_bb_ecp5.v share/lattice/cells_bb_ecp5.v @@ -3165,18 +3201,18 @@ mkdir -p share/lattice cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v mkdir -p share/lattice -mkdir -p share/lattice cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt -cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v mkdir -p share/lattice +cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v mkdir -p share/lattice cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v +mkdir -p share/lattice cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v mkdir -p share/lattice cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v mkdir -p share/microchip -cp "./"/techlibs/microchip/arith_map.v share/microchip/arith_map.v mkdir -p share/microchip +cp "./"/techlibs/microchip/arith_map.v share/microchip/arith_map.v cp "./"/techlibs/microchip/cells_map.v share/microchip/cells_map.v mkdir -p share/microchip cp "./"/techlibs/microchip/cells_sim.v share/microchip/cells_sim.v @@ -3187,8 +3223,8 @@ mkdir -p share/microchip cp "./"/techlibs/microchip/LSRAM_map.v share/microchip/LSRAM_map.v mkdir -p share/microchip -mkdir -p share/microchip cp "./"/techlibs/microchip/LSRAM.txt share/microchip/LSRAM.txt +mkdir -p share/microchip cp "./"/techlibs/microchip/uSRAM_map.v share/microchip/uSRAM_map.v mkdir -p share/microchip cp "./"/techlibs/microchip/uSRAM.txt share/microchip/uSRAM.txt @@ -3213,20 +3249,20 @@ mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/cells_sim.v share/nanoxplore/cells_sim.v mkdir -p share/nanoxplore -mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/cells_sim_l.v share/nanoxplore/cells_sim_l.v -cp "./"/techlibs/nanoxplore/cells_sim_m.v share/nanoxplore/cells_sim_m.v mkdir -p share/nanoxplore +mkdir -p share/nanoxplore +cp "./"/techlibs/nanoxplore/cells_sim_m.v share/nanoxplore/cells_sim_m.v cp "./"/techlibs/nanoxplore/cells_sim_u.v share/nanoxplore/cells_sim_u.v mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/cells_wrap.v share/nanoxplore/cells_wrap.v mkdir -p share/nanoxplore -mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/cells_wrap_l.v share/nanoxplore/cells_wrap_l.v -cp "./"/techlibs/nanoxplore/cells_wrap_m.v share/nanoxplore/cells_wrap_m.v mkdir -p share/nanoxplore +cp "./"/techlibs/nanoxplore/cells_wrap_m.v share/nanoxplore/cells_wrap_m.v mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/cells_wrap_u.v share/nanoxplore/cells_wrap_u.v +mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/io_map.v share/nanoxplore/io_map.v mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/latches_map.v share/nanoxplore/latches_map.v @@ -3239,24 +3275,24 @@ mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/rf_rams_u.txt share/nanoxplore/rf_rams_u.txt mkdir -p share/nanoxplore -mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/rf_rams_map_l.v share/nanoxplore/rf_rams_map_l.v +mkdir -p share/nanoxplore cp "./"/techlibs/nanoxplore/rf_rams_map_m.v share/nanoxplore/rf_rams_map_m.v mkdir -p share/nanoxplore -mkdir -p share/nexus cp "./"/techlibs/nanoxplore/rf_rams_map_u.v share/nanoxplore/rf_rams_map_u.v -cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v mkdir -p share/nexus +cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v mkdir -p share/nexus cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v -cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh mkdir -p share/nexus +cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh mkdir -p share/nexus cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v +mkdir -p share/nexus cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v mkdir -p share/nexus -cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt mkdir -p share/nexus +cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v mkdir -p share/nexus cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt @@ -3267,8 +3303,8 @@ mkdir -p share/nexus cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v mkdir -p share/nexus -mkdir -p share/nexus cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v +mkdir -p share/nexus cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v mkdir -p share/quicklogic/common cp "./"/techlibs/quicklogic/common/cells_sim.v share/quicklogic/common/cells_sim.v @@ -3314,8 +3350,8 @@ mkdir -p share/quicklogic/qlf_k6n10f cp "./"/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v share/quicklogic/qlf_k6n10f/ufifo_ctl.v mkdir -p share/quicklogic/qlf_k6n10f -cp "./"/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v share/quicklogic/qlf_k6n10f/sram1024x18_mem.v mkdir -p share/sf2 +cp "./"/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v share/quicklogic/qlf_k6n10f/sram1024x18_mem.v cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v mkdir -p share/sf2 mkdir -p share/sf2 @@ -3388,22 +3424,22 @@ mkdir -p share/xilinx cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v mkdir -p share/xilinx -mkdir -p abc && make -C abc -f "/build/reproducible-path/yosys-0.52/abc/Makefile" ABCSRC="/build/reproducible-path/yosys-0.52/abc" CC="g++" CXX="g++" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE= ARCHFLAGS="-DABC_USE_STDINT_H """ PROG="abc" MSG_PREFIX="-> ABC: " cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v +mkdir -p abc && make -C abc -f "/build/reproducible-path/yosys-0.52/abc/Makefile" ABCSRC="/build/reproducible-path/yosys-0.52/abc" CC="g++" CXX="g++" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE= ARCHFLAGS="-DABC_USE_STDINT_H """ PROG="abc" MSG_PREFIX="-> ABC: " +mkdir -p kernel/ +g++ -o kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f90.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f90.cc make[3]: Entering directory '/build/reproducible-path/yosys-0.52/abc' -> ABC: Using CC=g++ -> ABC: Using CXX=g++ -> ABC: Using AR=ar -mkdir -p kernel/ -> ABC: Using LD=g++ -g++ -o kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f90.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f90.cc +mkdir -p kernel/ +g++ -o kernel/register.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/register.cc -> ABC: Compiling in namespace -> ABC: Compiling with CUDD -> ABC: Using libreadline -> ABC: Using pthreads -> ABC: Found GCC_VERSION 14 -mkdir -p kernel/ -g++ -o kernel/register.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/register.cc -> ABC: Found GCC_MAJOR>=5 -> ABC: Using explicit -lstdc++ -> ABC: Using CFLAGS=-g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable @@ -3512,6 +3548,8 @@ -> ABC: `` Generating dependency: /src/sat/cadical/cadical_cover.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/sat/cadical/cadical_cover.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_cover.cpp > src/sat/cadical/cadical_cover.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +mkdir -p frontends/rtlil/ +g++ -o frontends/rtlil/rtlil_parser.tab.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_parser.tab.cc -> ABC: `` Generating dependency: /src/sat/cadical/cadical_decide.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/sat/cadical/cadical_decide.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_decide.cpp > src/sat/cadical/cadical_decide.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -3629,6 +3667,8 @@ -> ABC: `` Generating dependency: /src/sat/cadical/cadical_propagate.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/sat/cadical/cadical_propagate.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_propagate.cpp > src/sat/cadical/cadical_propagate.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +mkdir -p frontends/rtlil/ +g++ -o frontends/rtlil/rtlil_lexer.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_lexer.cc -> ABC: `` Generating dependency: /src/sat/cadical/cadical_queue.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/sat/cadical/cadical_queue.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_queue.cpp > src/sat/cadical/cadical_queue.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -3683,6 +3723,8 @@ -> ABC: `` Generating dependency: /src/sat/cadical/cadical_sweep.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/sat/cadical/cadical_sweep.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_sweep.cpp > src/sat/cadical/cadical_sweep.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +mkdir -p frontends/verilog/ +g++ -o frontends/verilog/verilog_parser.tab.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYYMAXDEPTH=10000000 frontends/verilog/verilog_parser.tab.cc -> ABC: `` Generating dependency: /src/sat/cadical/cadical_terminal.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/sat/cadical/cadical_terminal.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_terminal.cpp > src/sat/cadical/cadical_terminal.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -3722,13 +3764,15 @@ -> ABC: `` Generating dependency: /src/aig/gia/giaRrr.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaRrr.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/aig/gia/giaRrr.cpp > src/aig/gia/giaRrr.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p frontends/rtlil/ -g++ -o frontends/rtlil/rtlil_parser.tab.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_parser.tab.cc -> ABC: `` Generating dependency: /src/aig/gia/giaTransduction.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaTransduction.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/aig/gia/giaTransduction.cpp > src/aig/gia/giaTransduction.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +mkdir -p frontends/verilog/ +flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l -> ABC: `` Generating dependency: /src/aig/gia/giaTtopt.cpp /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaTtopt.cpp` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/aig/gia/giaTtopt.cpp > src/aig/gia/giaTtopt.d +mkdir -p passes/opt/ +g++ -o passes/opt/peepopt.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/peepopt.cc cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/base/abc/abcAig.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/base/abc/abcAig.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/abc/abcAig.c > src/base/abc/abcAig.d @@ -4216,8 +4260,6 @@ -> ABC: `` Generating dependency: /src/base/wlc/wlcAbs2.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/base/wlc/wlcAbs2.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/wlc/wlcAbs2.c > src/base/wlc/wlcAbs2.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p frontends/rtlil/ -g++ -o frontends/rtlil/rtlil_lexer.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_lexer.cc -> ABC: `` Generating dependency: /src/base/wlc/wlcAbc.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/base/wlc/wlcAbc.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/wlc/wlcAbc.c > src/base/wlc/wlcAbc.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -4323,8 +4365,6 @@ -> ABC: `` Generating dependency: /src/base/acb/acbMfs.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/base/acb/acbMfs.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/acb/acbMfs.c > src/base/acb/acbMfs.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p frontends/verilog/ -g++ -o frontends/verilog/verilog_parser.tab.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYYMAXDEPTH=10000000 frontends/verilog/verilog_parser.tab.cc -> ABC: `` Generating dependency: /src/base/acb/acbPush.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/base/acb/acbPush.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/acb/acbPush.c > src/base/acb/acbPush.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -4462,6 +4502,8 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/map/mapper/mapperSwitch.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/map/mapper/mapperSwitch.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/mapper/mapperSwitch.c > src/map/mapper/mapperSwitch.d +mkdir -p passes/pmgen/ +g++ -o passes/pmgen/test_pmgen.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/test_pmgen.cc cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/map/mapper/mapperTable.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/map/mapper/mapperTable.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/mapper/mapperTable.c > src/map/mapper/mapperTable.d @@ -4616,6 +4658,8 @@ -> ABC: `` Generating dependency: /src/map/amap/amapOutput.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/map/amap/amapOutput.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapOutput.c > src/map/amap/amapOutput.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +mkdir -p techlibs/ice40/ +g++ -o techlibs/ice40/ice40_wrapcarry.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_wrapcarry.cc -> ABC: `` Generating dependency: /src/map/amap/amapParse.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/map/amap/amapParse.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapParse.c > src/map/amap/amapParse.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -5185,6 +5229,8 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/opt/rar/rewire_map.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/opt/rar/rewire_map.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/rar/rewire_map.c > src/opt/rar/rewire_map.d +mkdir -p techlibs/microchip/ +g++ -o techlibs/microchip/microchip_dsp.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/microchip/microchip_dsp.cc cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/opt/rar/rewire_rar.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/opt/rar/rewire_rar.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/rar/rewire_rar.c > src/opt/rar/rewire_rar.d @@ -5246,6 +5292,8 @@ -> ABC: `` Generating dependency: /src/opt/dau/dauCanon.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/opt/dau/dauCanon.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/dau/dauCanon.c > src/opt/dau/dauCanon.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +mkdir -p techlibs/quicklogic/ +g++ -o techlibs/quicklogic/ql_dsp_macc.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_dsp_macc.cc -> ABC: `` Generating dependency: /src/opt/dau/dauCore.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/opt/dau/dauCore.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/dau/dauCore.c > src/opt/dau/dauCore.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -5288,10 +5336,6 @@ -> ABC: `` Generating dependency: /src/opt/sfm/sfmCnf.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/opt/sfm/sfmCnf.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmCnf.c > src/opt/sfm/sfmCnf.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p frontends/verilog/ -flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l -mkdir -p passes/opt/ -g++ -o passes/opt/peepopt.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/peepopt.cc -> ABC: `` Generating dependency: /src/opt/sfm/sfmCore.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/opt/sfm/sfmCore.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmCore.c > src/opt/sfm/sfmCore.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -5577,8 +5621,6 @@ -> ABC: `` Generating dependency: /src/sat/kissat/allocate.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/sat/kissat/allocate.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/allocate.c > src/sat/kissat/allocate.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p passes/pmgen/ -g++ -o passes/pmgen/test_pmgen.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/test_pmgen.cc -> ABC: `` Generating dependency: /src/sat/kissat/analyze.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/sat/kissat/analyze.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/analyze.c > src/sat/kissat/analyze.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -5975,6 +6017,8 @@ -> ABC: `` Generating dependency: /src/proof/pdr/pdrUtil.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/pdr/pdrUtil.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/pdr/pdrUtil.c > src/proof/pdr/pdrUtil.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +mkdir -p techlibs/xilinx/ +g++ -o techlibs/xilinx/xilinx_dsp.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/xilinx_dsp.cc -> ABC: `` Generating dependency: /src/proof/abs/absDup.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/abs/absDup.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/abs/absDup.c > src/proof/abs/absDup.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6329,8 +6373,6 @@ -> ABC: `` Generating dependency: /src/proof/fra/fraSim.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/fra/fraSim.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fra/fraSim.c > src/proof/fra/fraSim.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p techlibs/ice40/ -g++ -o techlibs/ice40/ice40_wrapcarry.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_wrapcarry.cc -> ABC: `` Generating dependency: /src/proof/ssw/sswAig.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/ssw/sswAig.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswAig.c > src/proof/ssw/sswAig.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6372,22 +6414,22 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/proof/ssw/sswRarity.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/ssw/sswRarity.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswRarity.c > src/proof/ssw/sswRarity.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/proof/ssw/sswSat.c +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/ssw/sswSat.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswSat.c > src/proof/ssw/sswSat.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/proof/ssw/sswSemi.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/ssw/sswSemi.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswSemi.c > src/proof/ssw/sswSemi.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/proof/ssw/sswSim.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/ssw/sswSim.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswSim.c > src/proof/ssw/sswSim.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/proof/ssw/sswSimSat.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/ssw/sswSimSat.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswSimSat.c > src/proof/ssw/sswSimSat.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/proof/ssw/sswSweep.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/ssw/sswSweep.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswSweep.c > src/proof/ssw/sswSweep.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/proof/ssw/sswUnique.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/proof/ssw/sswUnique.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswUnique.c > src/proof/ssw/sswUnique.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6407,47 +6449,57 @@ /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigDup.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigDup.c > src/aig/aig/aigDup.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigFanout.c -/build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigFanout.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigFanout.c > src/aig/aig/aigFanout.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigFrames.c +/build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigFanout.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigFanout.c > src/aig/aig/aigFanout.d /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigFrames.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigFrames.c > src/aig/aig/aigFrames.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigInter.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigInter.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigInter.c > src/aig/aig/aigInter.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigJust.c -/build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigJust.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigJust.c > src/aig/aig/aigJust.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigMan.c +/build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigJust.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigJust.c > src/aig/aig/aigJust.d /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigMan.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigMan.c > src/aig/aig/aigMan.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigMem.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigMem.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigMem.c > src/aig/aig/aigMem.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigMffc.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigMffc.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigMffc.c > src/aig/aig/aigMffc.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigObj.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigObj.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigObj.c > src/aig/aig/aigObj.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigOper.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigOper.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigOper.c > src/aig/aig/aigOper.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigOrder.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigOrder.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigOrder.c > src/aig/aig/aigOrder.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigPack.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigPack.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigPack.c > src/aig/aig/aigPack.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigPart.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigPart.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigPart.c > src/aig/aig/aigPart.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigPartReg.c +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigPartReg.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigPartReg.c > src/aig/aig/aigPartReg.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/aig/aigPartSat.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigPartSat.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigPartSat.c > src/aig/aig/aigPartSat.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +mkdir -p ./ +g++ -o yosys-filterlib -rdynamic passes/techmap/filterlib.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 +mkdir -p share/gatemate +cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib +mkdir -p share/gatemate +cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v +mkdir -p share/quicklogic/qlf_k6n10f +cp techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v share/quicklogic/qlf_k6n10f/bram_types_sim.v +mkdir -p frontends/verilog/ +g++ -o frontends/verilog/verilog_lexer.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_lexer.cc -> ABC: `` Generating dependency: /src/aig/aig/aigRepr.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/aig/aigRepr.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigRepr.c > src/aig/aig/aigRepr.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6714,10 +6766,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaLf.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaLf.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaLf.c > src/aig/gia/giaLf.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaMf.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaMf.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMf.c > src/aig/gia/giaMf.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaMan.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaMan.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMan.c > src/aig/gia/giaMan.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6753,10 +6805,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaPat.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaPat.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaPat.c > src/aig/gia/giaPat.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaPat2.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaPat2.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaPat2.c > src/aig/gia/giaPat2.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaPf.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaPf.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaPf.c > src/aig/gia/giaPf.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6813,10 +6865,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaScript.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaScript.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaScript.c > src/aig/gia/giaScript.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaShow.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaShow.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaShow.c > src/aig/gia/giaShow.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaShrink.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaShrink.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaShrink.c > src/aig/gia/giaShrink.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6831,28 +6883,28 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaSim.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaSim.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSim.c > src/aig/gia/giaSim.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaSim2.c +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaSim2.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSim2.c > src/aig/gia/giaSim2.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaSimBase.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaSimBase.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSimBase.c > src/aig/gia/giaSimBase.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaSort.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaSort.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSort.c > src/aig/gia/giaSort.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaSpeedup.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaSpeedup.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSpeedup.c > src/aig/gia/giaSpeedup.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaSplit.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaSplit.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSplit.c > src/aig/gia/giaSplit.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Generating dependency: /src/aig/gia/giaStg.c -/build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaStg.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaStg.c > src/aig/gia/giaStg.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Generating dependency: /src/aig/gia/giaStg.c -> ABC: `` Generating dependency: /src/aig/gia/giaStoch.c +/build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaStg.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaStg.c > src/aig/gia/giaStg.d /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaStoch.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaStoch.c > src/aig/gia/giaStoch.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaStr.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaStr.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaStr.c > src/aig/gia/giaStr.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6882,19 +6934,19 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaTranStoch.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaTranStoch.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaTranStoch.c > src/aig/gia/giaTranStoch.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaTruth.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaTruth.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaTruth.c > src/aig/gia/giaTruth.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaTsim.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaTsim.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaTsim.c > src/aig/gia/giaTsim.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaUnate.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaUnate.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaUnate.c > src/aig/gia/giaUnate.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaUtil.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaUtil.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaUtil.c > src/aig/gia/giaUtil.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/gia/giaBound.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/gia/giaBound.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaBound.c > src/aig/gia/giaBound.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -6912,20 +6964,20 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/ivy/ivyCanon.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/ivy/ivyCanon.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyCanon.c > src/aig/ivy/ivyCanon.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/ivy/ivyCheck.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/ivy/ivyCheck.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyCheck.c > src/aig/ivy/ivyCheck.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/ivy/ivyCut.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/ivy/ivyCut.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyCut.c > src/aig/ivy/ivyCut.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/ivy/ivyCutTrav.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/ivy/ivyCutTrav.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyCutTrav.c > src/aig/ivy/ivyCutTrav.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/ivy/ivyDfs.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/ivy/ivyDfs.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyDfs.c > src/aig/ivy/ivyDfs.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/ivy/ivyDsd.c +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/aig/ivy/ivyDsd.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyDsd.c > src/aig/ivy/ivyDsd.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/aig/ivy/ivyFanout.c @@ -7021,8 +7073,6 @@ -> ABC: `` Generating dependency: /src/bdd/cudd/cuddAddIte.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/cudd/cuddAddIte.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/cudd/cuddAddIte.c > src/bdd/cudd/cuddAddIte.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p techlibs/microchip/ -g++ -o techlibs/microchip/microchip_dsp.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/microchip/microchip_dsp.cc -> ABC: `` Generating dependency: /src/bdd/cudd/cuddAddNeg.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/cudd/cuddAddNeg.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/cudd/cuddAddNeg.c > src/bdd/cudd/cuddAddNeg.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -7145,10 +7195,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/bdd/cudd/cuddSymmetry.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/cudd/cuddSymmetry.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/cudd/cuddSymmetry.c > src/bdd/cudd/cuddSymmetry.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/bdd/cudd/cuddTable.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/cudd/cuddTable.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/cudd/cuddTable.c > src/bdd/cudd/cuddTable.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/bdd/cudd/cuddUtil.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/cudd/cuddUtil.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/cudd/cuddUtil.c > src/bdd/cudd/cuddUtil.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -7219,15 +7269,15 @@ /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/extrab/extraBddTime.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/extrab/extraBddTime.c > src/bdd/extrab/extraBddTime.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/bdd/extrab/extraBddUnate.c -/build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/extrab/extraBddUnate.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/extrab/extraBddUnate.c > src/bdd/extrab/extraBddUnate.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/bdd/dsd/dsdApi.c +/build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/extrab/extraBddUnate.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/extrab/extraBddUnate.c > src/bdd/extrab/extraBddUnate.d /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/dsd/dsdApi.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/dsd/dsdApi.c > src/bdd/dsd/dsdApi.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/bdd/dsd/dsdCheck.c /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/dsd/dsdCheck.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/dsd/dsdCheck.c > src/bdd/dsd/dsdCheck.d -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/bdd/dsd/dsdLocal.c +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ /build/reproducible-path/yosys-0.52/abc/depends.sh "g++" `dirname src/bdd/dsd/dsdLocal.c` -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/dsd/dsdLocal.c > src/bdd/dsd/dsdLocal.d cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Generating dependency: /src/bdd/dsd/dsdMan.c @@ -7370,6 +7420,15 @@ -> ABC: Using CFLAGS=-g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -> ABC: `` Compiling: /src/map/if/acd/ac_wrapper.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/map/if/acd/ac_wrapper.cpp -o src/map/if/acd/ac_wrapper.o +-> ABC: `` Compiling: /src/opt/rar/rewire_miaig.cpp +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/opt/rar/rewire_miaig.cpp -o src/opt/rar/rewire_miaig.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/opt/eslim/relationGeneration.cpp +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/opt/eslim/relationGeneration.cpp -o src/opt/eslim/relationGeneration.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/opt/eslim/eSLIM.cpp +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/opt/eslim/eSLIM.cpp -o src/opt/eslim/eSLIM.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from /usr/include/c++/14/bits/hashtable_policy.h:34, from /usr/include/c++/14/bits/hashtable.h:35, @@ -7390,9 +7449,6 @@ src/map/if/acd/ac_decomposition.hpp:547:40: note: 'res_perm' declared here 547 | std::array res_perm; | ^~~~~~~~ --> ABC: `` Compiling: /src/opt/rar/rewire_miaig.cpp -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/opt/rar/rewire_miaig.cpp -o src/opt/rar/rewire_miaig.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In member function 'std::_Head_base<1u, std::array, false>::_Head_base&>(std::array&)', inlined from 'std::_Tuple_impl<1u, std::array, unsigned int>::_Tuple_impl&, unsigned int, void>(std::array&, unsigned int&&)' at /usr/include/c++/14/tuple:318:38, inlined from 'std::_Tuple_impl<0u, abc::kitty::static_truth_table<11u, false>, std::array, unsigned int>::_Tuple_impl&, std::array&, unsigned int, void>(abc::kitty::static_truth_table<11u, false>&, std::array&, unsigned int&&)' at /usr/include/c++/14/tuple:318:38, @@ -7406,14 +7462,6 @@ src/map/if/acd/ac_decomposition.hpp:514:40: note: 'res_perm' declared here 514 | std::array res_perm; | ^~~~~~~~ -mkdir -p techlibs/quicklogic/ -g++ -o techlibs/quicklogic/ql_dsp_macc.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_dsp_macc.cc --> ABC: `` Compiling: /src/opt/eslim/relationGeneration.cpp -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/opt/eslim/relationGeneration.cpp -o src/opt/eslim/relationGeneration.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/opt/eslim/eSLIM.cpp -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/opt/eslim/eSLIM.cpp -o src/opt/eslim/eSLIM.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/glucose/AbcGlucose.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/glucose/AbcGlucose.cpp -o src/sat/glucose/AbcGlucose.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -7487,8 +7535,6 @@ | | int64_t {aka long long int} | long int | %lld -mkdir -p techlibs/xilinx/ -g++ -o techlibs/xilinx/xilinx_dsp.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/xilinx_dsp.cc -> ABC: `` Compiling: /src/sat/glucose/Options.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/glucose/Options.cpp -o src/sat/glucose/Options.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -7501,19 +7547,9 @@ -> ABC: `` Compiling: /src/sat/glucose2/AbcGlucose2.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/glucose2/AbcGlucose2.cpp -o src/sat/glucose2/AbcGlucose2.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p ./ -g++ -o yosys-filterlib -rdynamic passes/techmap/filterlib.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -> ABC: `` Compiling: /src/sat/glucose2/AbcGlucoseCmd2.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/glucose2/AbcGlucoseCmd2.cpp -o src/sat/glucose2/AbcGlucoseCmd2.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -mkdir -p share/gatemate -cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib -mkdir -p share/gatemate -cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v -mkdir -p share/quicklogic/qlf_k6n10f -cp techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v share/quicklogic/qlf_k6n10f/bram_types_sim.v -mkdir -p frontends/verilog/ -g++ -o frontends/verilog/verilog_lexer.o -c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=\\"0.52\\" -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_lexer.cc -> ABC: `` Compiling: /src/sat/glucose2/Glucose2.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/glucose2/Glucose2.cpp -o src/sat/glucose2/Glucose2.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -7632,12 +7668,25 @@ -> ABC: `` Compiling: /src/sat/cadical/cadical_condition.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_condition.cpp -o src/sat/cadical/cadical_condition.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +g++ -o yosys -rdynamic kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f90.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/io.o kernel/gzip.o kernel/binding.o kernel/tclapi.o kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o kernel/drivertools.o kernel/functional.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o libs/subcircuit/subcircuit.o frontends/aiger/aigerparse.o frontends/aiger2/xaiger.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/viz.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/splitcells.o passes/cmds/stat.o passes/cmds/internal_stats.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/cmds/xprop.o passes/cmds/dft_tag.o passes/cmds/future.o passes/cmds/box_derive.o passes/cmds/example_dt.o passes/cmds/portarcs.o passes/cmds/wrapcell.o passes/cmds/setenv.o passes/cmds/abstract.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/hierarchy/keep_hierarchy.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/memory/memory_libmap.o passes/memory/memory_bmux2rom.o passes/memory/memlib.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/opt_ffinv.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/opt/peepopt.o passes/pmgen/test_pmgen.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_rom.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/formalff.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/recover_names.o passes/sat/qbfsat.o passes/sat/synthprop.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/booth.o passes/techmap/libparse.o passes/techmap/libcache.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/abc_new.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/bwmuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/bufnorm.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/techmap/cellmatch.o passes/techmap/clockgate.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/aiger2/aiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/functional/cxx.o backends/functional/smtlib.o backends/functional/smtlib_rosette.o backends/functional/test_generic.o backends/intersynth/intersynth.o backends/jny/jny.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/fabulous/synth_fabulous.o techlibs/gatemate/synth_gatemate.o techlibs/gatemate/gatemate_foldinv.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/ice40/ice40_dsp.o techlibs/ice40/ice40_wrapcarry.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/lattice/synth_lattice.o techlibs/lattice/lattice_gsr.o techlibs/microchip/synth_microchip.o techlibs/microchip/microchip_dffopt.o techlibs/microchip/microchip_dsp.o techlibs/nanoxplore/synth_nanoxplore.o techlibs/nanoxplore/nx_carry.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/quicklogic/ql_bram_merge.o techlibs/quicklogic/ql_bram_types.o techlibs/quicklogic/ql_dsp_simd.o techlibs/quicklogic/ql_dsp_io_regs.o techlibs/quicklogic/ql_ioff.o techlibs/quicklogic/ql_dsp_macc.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o techlibs/xilinx/xilinx_dsp.o techlibs/xilinx/xilinx_srl.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -> ABC: `` Compiling: /src/sat/cadical/cadical_config.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_config.cpp -o src/sat/cadical/cadical_config.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/cadical/cadical_congruence.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_congruence.cpp -o src/sat/cadical/cadical_congruence.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +frontends/rtlil/rtlil_parser.tab.cc:492:7: warning: type 'union yyalloc' violates the C++ One Definition Rule [-Wodr] + 492 | union yyalloc + | ^ +frontends/verilog/verilog_parser.tab.cc:1164:7: note: a different type is defined in another translation unit + 1164 | union yyalloc + | ^ +frontends/rtlil/rtlil_parser.tab.cc:494:14: note: the first difference of corresponding definitions is field 'yyss_alloc' + 494 | yy_state_t yyss_alloc; + | ^ +frontends/verilog/verilog_parser.tab.cc:1166:14: note: a field of same name but different type is defined in another translation unit + 1166 | yy_state_t yyss_alloc; + | ^ -> ABC: `` Compiling: /src/sat/cadical/cadical_constrain.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_constrain.cpp -o src/sat/cadical/cadical_constrain.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -7657,6 +7706,14 @@ -> ABC: `` Compiling: /src/sat/cadical/cadical_decide.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_decide.cpp -o src/sat/cadical/cadical_decide.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +frontends/rtlil/rtlil_parser.tab.cc:126: warning: type 'yysymbol_kind_t' violates the C++ One Definition Rule [-Wodr] + 126 | enum yysymbol_kind_t +frontends/verilog/verilog_parser.tab.cc:431: note: an enum with different value name is defined in another translation unit + 431 | enum yysymbol_kind_t +frontends/rtlil/rtlil_parser.tab.cc:132: note: name 'YYSYMBOL_TOK_ID' differs from name 'YYSYMBOL_TOK_STRING' defined in another translation unit + 132 | YYSYMBOL_TOK_ID = 3, /* TOK_ID */ +frontends/verilog/verilog_parser.tab.cc:437: note: mismatching definition + 437 | YYSYMBOL_TOK_STRING = 3, /* TOK_STRING */ -> ABC: `` Compiling: /src/sat/cadical/cadical_decompose.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_decompose.cpp -o src/sat/cadical/cadical_decompose.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -7669,33 +7726,12 @@ -> ABC: `` Compiling: /src/sat/cadical/cadical_drattracer.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_drattracer.cpp -o src/sat/cadical/cadical_drattracer.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -g++ -o yosys -rdynamic kernel/version_fee39a3284c90249e1d9684cf6944ffbbcbb8f90.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/io.o kernel/gzip.o kernel/binding.o kernel/tclapi.o kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o kernel/drivertools.o kernel/functional.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o libs/subcircuit/subcircuit.o frontends/aiger/aigerparse.o frontends/aiger2/xaiger.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/viz.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/splitcells.o passes/cmds/stat.o passes/cmds/internal_stats.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/cmds/xprop.o passes/cmds/dft_tag.o passes/cmds/future.o passes/cmds/box_derive.o passes/cmds/example_dt.o passes/cmds/portarcs.o passes/cmds/wrapcell.o passes/cmds/setenv.o passes/cmds/abstract.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/hierarchy/keep_hierarchy.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/memory/memory_libmap.o passes/memory/memory_bmux2rom.o passes/memory/memlib.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/opt_ffinv.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/opt/peepopt.o passes/pmgen/test_pmgen.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_rom.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/formalff.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/recover_names.o passes/sat/qbfsat.o passes/sat/synthprop.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/booth.o passes/techmap/libparse.o passes/techmap/libcache.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/abc_new.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/bwmuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/bufnorm.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/techmap/cellmatch.o passes/techmap/clockgate.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/aiger2/aiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/functional/cxx.o backends/functional/smtlib.o backends/functional/smtlib_rosette.o backends/functional/test_generic.o backends/intersynth/intersynth.o backends/jny/jny.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/fabulous/synth_fabulous.o techlibs/gatemate/synth_gatemate.o techlibs/gatemate/gatemate_foldinv.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/ice40/ice40_dsp.o techlibs/ice40/ice40_wrapcarry.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/lattice/synth_lattice.o techlibs/lattice/lattice_gsr.o techlibs/microchip/synth_microchip.o techlibs/microchip/microchip_dffopt.o techlibs/microchip/microchip_dsp.o techlibs/nanoxplore/synth_nanoxplore.o techlibs/nanoxplore/nx_carry.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/quicklogic/ql_bram_merge.o techlibs/quicklogic/ql_bram_types.o techlibs/quicklogic/ql_dsp_simd.o techlibs/quicklogic/ql_dsp_io_regs.o techlibs/quicklogic/ql_ioff.o techlibs/quicklogic/ql_dsp_macc.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o techlibs/xilinx/xilinx_dsp.o techlibs/xilinx/xilinx_srl.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 -> ABC: `` Compiling: /src/sat/cadical/cadical_elim.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_elim.cpp -o src/sat/cadical/cadical_elim.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -frontends/rtlil/rtlil_parser.tab.cc:492:7: warning: type 'union yyalloc' violates the C++ One Definition Rule [-Wodr] - 492 | union yyalloc - | ^ -frontends/verilog/verilog_parser.tab.cc:1164:7: note: a different type is defined in another translation unit - 1164 | union yyalloc - | ^ -frontends/rtlil/rtlil_parser.tab.cc:494:14: note: the first difference of corresponding definitions is field 'yyss_alloc' - 494 | yy_state_t yyss_alloc; - | ^ -frontends/verilog/verilog_parser.tab.cc:1166:14: note: a field of same name but different type is defined in another translation unit - 1166 | yy_state_t yyss_alloc; - | ^ -> ABC: `` Compiling: /src/sat/cadical/cadical_elimfast.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_elimfast.cpp -o src/sat/cadical/cadical_elimfast.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -frontends/rtlil/rtlil_parser.tab.cc:126: warning: type 'yysymbol_kind_t' violates the C++ One Definition Rule [-Wodr] - 126 | enum yysymbol_kind_t -frontends/verilog/verilog_parser.tab.cc:431: note: an enum with different value name is defined in another translation unit - 431 | enum yysymbol_kind_t -frontends/rtlil/rtlil_parser.tab.cc:132: note: name 'YYSYMBOL_TOK_ID' differs from name 'YYSYMBOL_TOK_STRING' defined in another translation unit - 132 | YYSYMBOL_TOK_ID = 3, /* TOK_ID */ -frontends/verilog/verilog_parser.tab.cc:437: note: mismatching definition - 437 | YYSYMBOL_TOK_STRING = 3, /* TOK_STRING */ -> ABC: `` Compiling: /src/sat/cadical/cadical_ema.cpp g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable -std=c++17 -fno-exceptions src/sat/cadical/cadical_ema.cpp -o src/sat/cadical/cadical_ema.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -8579,9 +8615,6 @@ -> ABC: `` Compiling: /src/base/wlc/wlcReadVer.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/wlc/wlcReadVer.c -o src/base/wlc/wlcReadVer.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/base/wlc/wlcSim.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/wlc/wlcSim.c -o src/base/wlc/wlcSim.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/base/wlc/wlc.h:34, from src/base/wlc/wlcReadVer.c:21: In function 'abc::Abc_TtSetHex(unsigned long long*, int, int)', @@ -8604,6 +8637,9 @@ src/base/wlc/wlcReadVer.c:985:27: note: object 'Value' of size 4 985 | int v, b, Value, nBits, nInts; | ^~~~~ +-> ABC: `` Compiling: /src/base/wlc/wlcSim.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/wlc/wlcSim.c -o src/base/wlc/wlcSim.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/base/wlc/wlcShow.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/wlc/wlcShow.c -o src/base/wlc/wlcShow.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -8658,6 +8694,9 @@ -> ABC: `` Compiling: /src/base/wln/wlnWriteVer.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/wln/wlnWriteVer.c -o src/base/wln/wlnWriteVer.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/base/acb/acbAbc.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/acb/acbAbc.c -o src/base/acb/acbAbc.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/base/wln/wlnWriteVer.c:21: In function 'abc::Wln_ObjFanin(abc::Wln_Ntk_t_*, int, int)', inlined from 'abc::Wln_ObjFanin2(abc::Wln_Ntk_t_*, int)' at src/base/wln/wln.h:115:103, @@ -8707,9 +8746,6 @@ src/base/wln/wln.h:51:28: note: while referencing 'Array' 51 | union { int Array[2]; | ^~~~~ --> ABC: `` Compiling: /src/base/acb/acbAbc.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/acb/acbAbc.c -o src/base/acb/acbAbc.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/base/acb/acbAig.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/base/acb/acbAig.c -o src/base/acb/acbAig.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -8889,10 +8925,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/mio/mioParse.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/mio/mioParse.c -o src/map/mio/mioParse.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/mio/mioRead.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/mio/mioRead.c -o src/map/mio/mioRead.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/mio/mioSop.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/mio/mioSop.c -o src/map/mio/mioSop.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -9001,6 +9037,21 @@ -> ABC: `` Compiling: /src/map/amap/amapLiberty.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapLiberty.c -o src/map/amap/amapLiberty.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/map/amap/amapMan.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapMan.c -o src/map/amap/amapMan.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/map/amap/amapMatch.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapMatch.c -o src/map/amap/amapMatch.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/map/amap/amapMerge.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapMerge.c -o src/map/amap/amapMerge.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/map/amap/amapOutput.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapOutput.c -o src/map/amap/amapOutput.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/map/amap/amapParse.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapParse.c -o src/map/amap/amapParse.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/map/amap/amapLiberty.c: In function 'abc::Amap_LibertyBuildItem(abc::Amap_Tree_t_*, char**, char*)': src/map/amap/amapLiberty.c:966:77: warning: '%s' directive writing up to 4999 bytes into a region of size 955 [-Wformat-overflow=] 353 | return Buffer; @@ -9021,21 +9072,6 @@ | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 | __va_arg_pack ()); | ~~~~~~~~~~~~~~~~~ --> ABC: `` Compiling: /src/map/amap/amapMan.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapMan.c -o src/map/amap/amapMan.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/map/amap/amapMatch.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapMatch.c -o src/map/amap/amapMatch.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/map/amap/amapMerge.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapMerge.c -o src/map/amap/amapMerge.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/map/amap/amapOutput.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapOutput.c -o src/map/amap/amapOutput.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/map/amap/amapParse.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapParse.c -o src/map/amap/amapParse.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/amap/amapPerm.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/amap/amapPerm.c -o src/map/amap/amapPerm.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -9067,10 +9103,10 @@ g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/cov/covMinSop.c -o src/map/cov/covMinSop.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/cov/covMinUtil.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/cov/covMinUtil.c -o src/map/cov/covMinUtil.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/scl/scl.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/scl/scl.c -o src/map/scl/scl.o +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/cov/covMinUtil.c -o src/map/cov/covMinUtil.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/scl/sclBuffer.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/scl/sclBuffer.c -o src/map/scl/sclBuffer.o @@ -9122,8 +9158,8 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/mpm/mpmMap.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/mpm/mpmMap.c -o src/map/mpm/mpmMap.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/mpm/mpmMig.c +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/map/mpm/mpmMig.c -o src/map/mpm/mpmMig.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/map/mpm/mpmPre.c @@ -9142,14 +9178,17 @@ g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilCanon.c -o src/misc/extra/extraUtilCanon.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/misc/extra/extraUtilCfs.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilCfs.c -o src/misc/extra/extraUtilCfs.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/misc/extra/extraUtilCube.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilCube.c -o src/misc/extra/extraUtilCube.o +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilCfs.c -o src/misc/extra/extraUtilCfs.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/misc/extra/extraUtilDsd.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilDsd.c -o src/misc/extra/extraUtilDsd.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/misc/extra/extraUtilEnum.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilEnum.c -o src/misc/extra/extraUtilEnum.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vec.h:29, from src/misc/extra/extraUtilCube.c:25: src/misc/extra/extraUtilCube.c: In function 'abc::Abc_EnumerateCubeStates()': @@ -9162,9 +9201,6 @@ /usr/include/stdlib.h:675:14: note: in a call to allocation function 'calloc' declared here 675 | extern void *calloc (size_t __nmemb, size_t __size) | ^~~~~~ --> ABC: `` Compiling: /src/misc/extra/extraUtilEnum.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilEnum.c -o src/misc/extra/extraUtilEnum.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/misc/extra/extraUtilFile.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilFile.c -o src/misc/extra/extraUtilFile.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -9199,6 +9235,18 @@ -> ABC: `` Compiling: /src/misc/extra/extraUtilMisc.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilMisc.c -o src/misc/extra/extraUtilMisc.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/misc/extra/extraUtilMult.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilMult.c -o src/misc/extra/extraUtilMult.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/misc/extra/extraUtilPath.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilPath.c -o src/misc/extra/extraUtilPath.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/misc/extra/extraUtilPerm.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilPerm.c -o src/misc/extra/extraUtilPerm.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/misc/extra/extraUtilProgress.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilProgress.c -o src/misc/extra/extraUtilProgress.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In function 'abc::Extra_NtkPrintBin(unsigned long long*, int)', inlined from 'abc::Extra_NtkPowerTest()' at src/misc/extra/extraUtilMisc.c:2568:26: src/misc/extra/extraUtilMisc.c:2556:30: warning: array subscript 'word[0]' is partly outside array bounds of 'int[1]' [-Warray-bounds=] @@ -9217,18 +9265,6 @@ src/misc/extra/extraUtilMisc.c:2560:9: note: object 'i' of size 4 2560 | int i, j, k, n = 4; | ^ --> ABC: `` Compiling: /src/misc/extra/extraUtilMult.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilMult.c -o src/misc/extra/extraUtilMult.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/misc/extra/extraUtilPath.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilPath.c -o src/misc/extra/extraUtilPath.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/misc/extra/extraUtilPerm.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilPerm.c -o src/misc/extra/extraUtilPerm.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/misc/extra/extraUtilProgress.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilProgress.c -o src/misc/extra/extraUtilProgress.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/misc/extra/extraUtilReader.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/extra/extraUtilReader.c -o src/misc/extra/extraUtilReader.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -9298,21 +9334,6 @@ -> ABC: `` Compiling: /src/misc/util/utilBSet.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/util/utilBSet.c -o src/misc/util/utilBSet.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -In file included from /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vec.h:29, - from src/misc/util/utilBSet.c:26: -In function 'abc::Vec_WecAlloc(int)', - inlined from 'abc::Vec_WecStart(int)' at /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vecWec.h:113:21, - inlined from 'abc::Abc_BSEvalCreateCofactorSets(int, abc::Vec_Wec_t_**)' at src/misc/util/utilBSet.c:813:38: -/build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:265:50: warning: argument 1 range [2147483649, 4294967295] exceeds maximum object size 2147483647 [-Walloc-size-larger-than=] - 265 | #define ABC_CALLOC(type, num) ((type *) calloc((size_t)(num), sizeof(type))) - | ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -In file included from /usr/include/c++/14/cstdlib:79, - from /usr/include/c++/14/stdlib.h:36, - from src/misc/util/utilBSet.c:23: -/usr/include/stdlib.h: In function 'abc::Abc_BSEvalCreateCofactorSets(int, abc::Vec_Wec_t_**)': -/usr/include/stdlib.h:675:14: note: in a call to allocation function 'calloc' declared here - 675 | extern void *calloc (size_t __nmemb, size_t __size) - | ^~~~~~ -> ABC: `` Compiling: /src/misc/util/utilCex.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/util/utilCex.c -o src/misc/util/utilCex.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -9340,6 +9361,21 @@ -> ABC: `` Compiling: /src/misc/nm/nmApi.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/nm/nmApi.c -o src/misc/nm/nmApi.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +In file included from /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vec.h:29, + from src/misc/util/utilBSet.c:26: +In function 'abc::Vec_WecAlloc(int)', + inlined from 'abc::Vec_WecStart(int)' at /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vecWec.h:113:21, + inlined from 'abc::Abc_BSEvalCreateCofactorSets(int, abc::Vec_Wec_t_**)' at src/misc/util/utilBSet.c:813:38: +/build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:265:50: warning: argument 1 range [2147483649, 4294967295] exceeds maximum object size 2147483647 [-Walloc-size-larger-than=] + 265 | #define ABC_CALLOC(type, num) ((type *) calloc((size_t)(num), sizeof(type))) + | ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +In file included from /usr/include/c++/14/cstdlib:79, + from /usr/include/c++/14/stdlib.h:36, + from src/misc/util/utilBSet.c:23: +/usr/include/stdlib.h: In function 'abc::Abc_BSEvalCreateCofactorSets(int, abc::Vec_Wec_t_**)': +/usr/include/stdlib.h:675:14: note: in a call to allocation function 'calloc' declared here + 675 | extern void *calloc (size_t __nmemb, size_t __size) + | ^~~~~~ -> ABC: `` Compiling: /src/misc/nm/nmTable.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/misc/nm/nmTable.c -o src/misc/nm/nmTable.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -9560,10 +9596,10 @@ g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/res/resDivs.c -o src/opt/res/resDivs.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/opt/res/resFilter.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/res/resFilter.c -o src/opt/res/resFilter.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/opt/res/resSat.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/res/resSat.c -o src/opt/res/resSat.o +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/res/resFilter.c -o src/opt/res/resFilter.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/opt/res/resSim.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/res/resSim.c -o src/opt/res/resSim.o @@ -9672,10 +9708,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/opt/cgt/cgtCore.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/cgt/cgtCore.c -o src/opt/cgt/cgtCore.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/opt/cgt/cgtDecide.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/cgt/cgtDecide.c -o src/opt/cgt/cgtDecide.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/opt/cgt/cgtMan.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/cgt/cgtMan.c -o src/opt/cgt/cgtMan.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -9757,6 +9793,24 @@ -> ABC: `` Compiling: /src/opt/dau/dauTree.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/dau/dauTree.c -o src/opt/dau/dauTree.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/opt/dsc/dsc.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/dsc/dsc.c -o src/opt/dsc/dsc.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/opt/sfm/sfmArea.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmArea.c -o src/opt/sfm/sfmArea.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/opt/sfm/sfmCnf.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmCnf.c -o src/opt/sfm/sfmCnf.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/opt/sfm/sfmCore.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmCore.c -o src/opt/sfm/sfmCore.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/opt/sfm/sfmDec.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmDec.c -o src/opt/sfm/sfmDec.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/opt/sfm/sfmLib.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmLib.c -o src/opt/sfm/sfmLib.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/opt/dau/dauTree.c: In function 'abc::Dss_ManBooleanAnd(abc::Dss_Man_t_*, abc::Dss_Ent_t_*, int)': src/opt/dau/dauTree.c:1492:22: warning: array subscript i_38 is outside array bounds of 'unsigned char[4294967296]' [-Warray-bounds=] 1492 | pFun->pFans[i] = (unsigned char)Abc_Lit2LitV( pMapDsd2Truth, pPermDsd[i] ); @@ -9777,24 +9831,6 @@ src/opt/dau/dauTree.c:48:20: note: while referencing 'pShared' 48 | unsigned char pShared[0]; // shared literals | ^~~~~~~ --> ABC: `` Compiling: /src/opt/dsc/dsc.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/dsc/dsc.c -o src/opt/dsc/dsc.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/opt/sfm/sfmArea.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmArea.c -o src/opt/sfm/sfmArea.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/opt/sfm/sfmCnf.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmCnf.c -o src/opt/sfm/sfmCnf.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/opt/sfm/sfmCore.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmCore.c -o src/opt/sfm/sfmCore.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/opt/sfm/sfmDec.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmDec.c -o src/opt/sfm/sfmDec.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/opt/sfm/sfmLib.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmLib.c -o src/opt/sfm/sfmLib.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/opt/sfm/sfmNtk.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/opt/sfm/sfmNtk.c -o src/opt/sfm/sfmNtk.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -9875,16 +9911,13 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/bsat/satTruth.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/bsat/satTruth.c -o src/sat/bsat/satTruth.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/bsat/satUtil.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/bsat/satUtil.c -o src/sat/bsat/satUtil.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/xsat/xsatSolver.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/xsat/xsatSolver.c -o src/sat/xsat/xsatSolver.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/xsat/xsatSolverAPI.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/xsat/xsatSolverAPI.c -o src/sat/xsat/xsatSolverAPI.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/xsat/xsatSolver.c:30: src/sat/xsat/xsatSolver.h: In function 'void abc::xSAT_SolverPrintState(xSAT_Solver_t*)': src/sat/xsat/xsatSolver.h:227:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] @@ -9905,7 +9938,13 @@ | | | | long int abc::iword {aka long long int} | %10lld -In file included from src/sat/xsat/xsatSolverAPI.c:29: +-> ABC: `` Compiling: /src/sat/xsat/xsatSolverAPI.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/xsat/xsatSolverAPI.c -o src/sat/xsat/xsatSolverAPI.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/xsat/xsatCnfReader.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/xsat/xsatCnfReader.c -o src/sat/xsat/xsatCnfReader.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +In file included from src/sat/xsat/xsatCnfReader.c:30: src/sat/xsat/xsatSolver.h: In function 'void abc::xSAT_SolverPrintState(xSAT_Solver_t*)': src/sat/xsat/xsatSolver.h:227:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] 227 | printf( "conflicts : %10ld\n", s->Stats.nConflicts ); @@ -9925,44 +9964,41 @@ | | | | long int abc::iword {aka long long int} | %10lld -src/sat/xsat/xsatSolverAPI.c: In function 'void abc::xSAT_SolverPrintStats(xSAT_Solver_t*)': -src/sat/xsat/xsatSolverAPI.c:341:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] - 341 | printf( "conflicts : %10ld\n", s->Stats.nConflicts ); +In file included from src/sat/xsat/xsatSolverAPI.c:29: +src/sat/xsat/xsatSolver.h: In function 'void abc::xSAT_SolverPrintState(xSAT_Solver_t*)': +src/sat/xsat/xsatSolver.h:227:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] + 227 | printf( "conflicts : %10ld\n", s->Stats.nConflicts ); | ~~~~^ ~~~~~~~~~~~~~~~~~~~ | | | | long int abc::iword {aka long long int} | %10lld -src/sat/xsat/xsatSolverAPI.c:342:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] - 342 | printf( "decisions : %10ld\n", s->Stats.nDecisions ); +src/sat/xsat/xsatSolver.h:228:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] + 228 | printf( "decisions : %10ld\n", s->Stats.nDecisions ); | ~~~~^ ~~~~~~~~~~~~~~~~~~~ | | | | long int abc::iword {aka long long int} | %10lld -src/sat/xsat/xsatSolverAPI.c:343:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] - 343 | printf( "propagations : %10ld\n", s->Stats.nPropagations ); +src/sat/xsat/xsatSolver.h:229:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] + 229 | printf( "propagations : %10ld\n", s->Stats.nPropagations ); | ~~~~^ ~~~~~~~~~~~~~~~~~~~~~~ | | | | long int abc::iword {aka long long int} | %10lld --> ABC: `` Compiling: /src/sat/xsat/xsatCnfReader.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/xsat/xsatCnfReader.c -o src/sat/xsat/xsatCnfReader.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -In file included from src/sat/xsat/xsatCnfReader.c:30: -src/sat/xsat/xsatSolver.h: In function 'void abc::xSAT_SolverPrintState(xSAT_Solver_t*)': -src/sat/xsat/xsatSolver.h:227:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] - 227 | printf( "conflicts : %10ld\n", s->Stats.nConflicts ); +src/sat/xsat/xsatSolverAPI.c: In function 'void abc::xSAT_SolverPrintStats(xSAT_Solver_t*)': +src/sat/xsat/xsatSolverAPI.c:341:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] + 341 | printf( "conflicts : %10ld\n", s->Stats.nConflicts ); | ~~~~^ ~~~~~~~~~~~~~~~~~~~ | | | | long int abc::iword {aka long long int} | %10lld -src/sat/xsat/xsatSolver.h:228:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] - 228 | printf( "decisions : %10ld\n", s->Stats.nDecisions ); +src/sat/xsat/xsatSolverAPI.c:342:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] + 342 | printf( "decisions : %10ld\n", s->Stats.nDecisions ); | ~~~~^ ~~~~~~~~~~~~~~~~~~~ | | | | long int abc::iword {aka long long int} | %10lld -src/sat/xsat/xsatSolver.h:229:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] - 229 | printf( "propagations : %10ld\n", s->Stats.nPropagations ); +src/sat/xsat/xsatSolverAPI.c:343:34: warning: format '%ld' expects argument of type 'long int', but argument 2 has type 'abc::iword' {aka 'long long int'} [-Wformat=] + 343 | printf( "propagations : %10ld\n", s->Stats.nPropagations ); | ~~~~^ ~~~~~~~~~~~~~~~~~~~~~~ | | | | long int abc::iword {aka long long int} @@ -9984,8 +10020,8 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/msat/msatClause.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/msat/msatClause.c -o src/sat/msat/msatClause.o --> ABC: `` Compiling: /src/sat/msat/msatClauseVec.c cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/msat/msatClauseVec.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/msat/msatClauseVec.c -o src/sat/msat/msatClauseVec.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/msat/msatMem.c @@ -10002,10 +10038,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/msat/msatSolverApi.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/msat/msatSolverApi.c -o src/sat/msat/msatSolverApi.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/msat/msatSolverCore.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/msat/msatSolverCore.c -o src/sat/msat/msatSolverCore.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/msat/msatSolverIo.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/msat/msatSolverIo.c -o src/sat/msat/msatSolverIo.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -10056,8 +10092,8 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/bmc/bmcBmc3.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/bmc/bmcBmc3.c -o src/sat/bmc/bmcBmc3.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/bmc/bmcBmcAnd.c +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/bmc/bmcBmcAnd.c -o src/sat/bmc/bmcBmcAnd.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/bmc/bmcBmci.c @@ -10123,6 +10159,9 @@ -> ABC: `` Compiling: /src/sat/bmc/bmcMaj2.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/bmc/bmcMaj2.c -o src/sat/bmc/bmcMaj2.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/bmc/bmcMaj3.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/bmc/bmcMaj3.c -o src/sat/bmc/bmcMaj3.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/sat/bmc/bmcMaj.c: In function 'void abc::Exa_NpnCascadeTest6()': src/sat/bmc/bmcMaj.c:4150:62: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'abc::word' {aka 'long long unsigned int'} [-Wformat=] 4150 | sprintf( Command, "lutexact -I 6 -N 2 -K 5 -gvc %016lx", Truth ); @@ -10131,9 +10170,6 @@ | | abc::word {aka long long unsigned int} | long unsigned int | %016llx --> ABC: `` Compiling: /src/sat/bmc/bmcMaj3.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/bmc/bmcMaj3.c -o src/sat/bmc/bmcMaj3.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/bmc/bmcMaxi.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/bmc/bmcMaxi.c -o src/sat/bmc/bmcMaxi.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -11244,24 +11280,12 @@ -> ABC: `` Compiling: /src/sat/kissat/averages.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/averages.c -o src/sat/kissat/averages.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -In file included from /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vec.h:29, - from /build/reproducible-path/yosys-0.52/abc/src/aig/aig/aig.h:34, - from /build/reproducible-path/yosys-0.52/abc/src/aig/saig/saig.h:29, - from src/sat/bmc/bmc.h:29, - from src/sat/bmc/bmcMaj.c:21: -In function 'abc::Abc_InfoHasBit(unsigned int*, int)', - inlined from 'abc::Abc_TtPrintBits(unsigned long long*, int)' at /build/reproducible-path/yosys-0.52/abc/src/misc/util/utilTruth.h:1597:15, - inlined from 'abc::Exa_ManExactSynthesis6_(abc::Bmc_EsPar_t_*, char*)' at src/sat/bmc/bmcMaj.c:3259:24: -/build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:303:81: warning: 'Entry' may be used uninitialized [-Wmaybe-uninitialized] - 303 | static inline int Abc_InfoHasBit( unsigned * p, int i ) { return (p[(i)>>5] & (unsigned)(1<<((i) & 31))) > 0; } - | ~~~~~~~~^ -src/sat/bmc/bmcMaj.c: In function 'abc::Exa_ManExactSynthesis6_(abc::Bmc_EsPar_t_*, char*)': -src/sat/bmc/bmcMaj.c:3248:10: note: 'Entry' declared here - 3248 | word Entry, Truths[100] = { 0x96, 0xE8 }; - | ^~~~~ -> ABC: `` Compiling: /src/sat/kissat/backbone.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/backbone.c -o src/sat/kissat/backbone.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/backtrack.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/backtrack.c -o src/sat/kissat/backtrack.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/averages.c:1: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] @@ -11475,8 +11499,8 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/backtrack.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/backtrack.c -o src/sat/kissat/backtrack.o +-> ABC: `` Compiling: /src/sat/kissat/build.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/build.c -o src/sat/kissat/build.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, @@ -11908,18 +11932,12 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/build.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/build.c -o src/sat/kissat/build.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/bump.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/bump.c -o src/sat/kissat/bump.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/check.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/check.c -o src/sat/kissat/check.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/classify.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/classify.c -o src/sat/kissat/classify.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlineheap.h:5, from src/sat/kissat/bump.c:3: @@ -12134,6 +12152,12 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/classify.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/classify.c -o src/sat/kissat/classify.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/clause.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/clause.c -o src/sat/kissat/clause.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/classify.c:2: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] @@ -12347,8 +12371,8 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/clause.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/clause.c -o src/sat/kissat/clause.o +-> ABC: `` Compiling: /src/sat/kissat/collect.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/collect.c -o src/sat/kissat/collect.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/collect.h:4, @@ -12564,9 +12588,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/collect.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/collect.c -o src/sat/kissat/collect.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/collect.h:4, from src/sat/kissat/collect.c:3: @@ -12781,26 +12802,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ -In function 'abc::Abc_InfoHasBit(unsigned int*, int)', - inlined from 'abc::Abc_TtPrintBits(unsigned long long*, int)' at /build/reproducible-path/yosys-0.52/abc/src/misc/util/utilTruth.h:1597:15, - inlined from 'abc::Exa_ManExactPrint(abc::Vec_Wrd_t_*, abc::Vec_Wrd_t_*, int, int)' at src/sat/bmc/bmcMaj.c:3863:24: -/build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:303:81: warning: 'Entry' may be used uninitialized [-Wmaybe-uninitialized] - 303 | static inline int Abc_InfoHasBit( unsigned * p, int i ) { return (p[(i)>>5] & (unsigned)(1<<((i) & 31))) > 0; } - | ~~~~~~~~^ -src/sat/bmc/bmcMaj.c: In function 'abc::Exa_ManExactPrint(abc::Vec_Wrd_t_*, abc::Vec_Wrd_t_*, int, int)': -src/sat/bmc/bmcMaj.c:3861:10: note: 'Entry' declared here - 3861 | word Entry; int i; - | ^~~~~ -In function 'abc::Abc_InfoHasBit(unsigned int*, int)', - inlined from 'abc::Abc_TtPrintBits(unsigned long long*, int)' at /build/reproducible-path/yosys-0.52/abc/src/misc/util/utilTruth.h:1597:15, - inlined from 'abc::Exa_ManExactPrint(abc::Vec_Wrd_t_*, abc::Vec_Wrd_t_*, int, int)' at src/sat/bmc/bmcMaj.c:3866:24: -/build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:303:81: warning: 'Entry' may be used uninitialized [-Wmaybe-uninitialized] - 303 | static inline int Abc_InfoHasBit( unsigned * p, int i ) { return (p[(i)>>5] & (unsigned)(1<<((i) & 31))) > 0; } - | ~~~~~~~~^ -src/sat/bmc/bmcMaj.c: In function 'abc::Exa_ManExactPrint(abc::Vec_Wrd_t_*, abc::Vec_Wrd_t_*, int, int)': -src/sat/bmc/bmcMaj.c:3861:10: note: 'Entry' declared here - 3861 | word Entry; int i; - | ^~~~~ -> ABC: `` Compiling: /src/sat/kissat/colors.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/colors.c -o src/sat/kissat/colors.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -13028,9 +13029,6 @@ -> ABC: `` Compiling: /src/sat/kissat/congruence.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/congruence.c -o src/sat/kissat/congruence.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/decide.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/decide.c -o src/sat/kissat/decide.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/dense.h:4, from src/sat/kissat/congruence.c:2: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] @@ -13254,6 +13252,12 @@ src/sat/kissat/congruence.c:398:29: note: in expansion of macro 'MAX_HASH_TABLE_SIZE' 398 | if (closure->hash.size == MAX_HASH_TABLE_SIZE) | ^~~~~~~~~~~~~~~~~~~ +-> ABC: `` Compiling: /src/sat/kissat/decide.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/decide.c -o src/sat/kissat/decide.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/deduce.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/deduce.c -o src/sat/kissat/deduce.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlineframes.h:5, from src/sat/kissat/decide.c:2: @@ -13468,9 +13472,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/deduce.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/deduce.c -o src/sat/kissat/deduce.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -13686,6 +13687,21 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +In file included from /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vec.h:29, + from /build/reproducible-path/yosys-0.52/abc/src/aig/aig/aig.h:34, + from /build/reproducible-path/yosys-0.52/abc/src/aig/saig/saig.h:29, + from src/sat/bmc/bmc.h:29, + from src/sat/bmc/bmcMaj.c:21: +In function 'abc::Abc_InfoHasBit(unsigned int*, int)', + inlined from 'abc::Abc_TtPrintBits(unsigned long long*, int)' at /build/reproducible-path/yosys-0.52/abc/src/misc/util/utilTruth.h:1597:15, + inlined from 'abc::Exa_ManExactSynthesis6_(abc::Bmc_EsPar_t_*, char*)' at src/sat/bmc/bmcMaj.c:3259:24: +/build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:303:81: warning: 'Entry' may be used uninitialized [-Wmaybe-uninitialized] + 303 | static inline int Abc_InfoHasBit( unsigned * p, int i ) { return (p[(i)>>5] & (unsigned)(1<<((i) & 31))) > 0; } + | ~~~~~~~~^ +src/sat/bmc/bmcMaj.c: In function 'abc::Exa_ManExactSynthesis6_(abc::Bmc_EsPar_t_*, char*)': +src/sat/bmc/bmcMaj.c:3248:10: note: 'Entry' declared here + 3248 | word Entry, Truths[100] = { 0x96, 0xE8 }; + | ^~~~~ -> ABC: `` Compiling: /src/sat/kissat/definition.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/definition.c -o src/sat/kissat/definition.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -13927,9 +13943,6 @@ src/sat/kissat/watch.h:14:21: note: declared here 14 | typedef union watch watch; | ^~~~~ --> ABC: `` Compiling: /src/sat/kissat/dump.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/dump.c -o src/sat/kissat/dump.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, from src/sat/kissat/dense.c:4: @@ -14085,6 +14098,7 @@ src/sat/kissat/internal.h:191:3: note: used here to mean 'typedef struct abc::classification abc::classification' 191 | classification classification; | ^~~~~~~~~~~~~~ +-> ABC: `` Compiling: /src/sat/kissat/dump.c In file included from src/sat/kissat/internal.h:9: src/sat/kissat/classify.h:16:31: note: declared here 16 | typedef struct classification classification; @@ -14095,6 +14109,7 @@ src/sat/kissat/internal.h:192:3: note: used here to mean 'typedef struct abc::delays abc::delays' 192 | delays delays; | ^~~~~~ +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/dump.c -o src/sat/kissat/dump.o src/sat/kissat/kimits.h:12:23: note: declared here 12 | typedef struct delays delays; | ^~~~~~ @@ -14135,6 +14150,7 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/eliminate.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/eliminate.c -o src/sat/kissat/eliminate.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -14795,7 +14811,26 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/fastel.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/fastel.c -o src/sat/kissat/fastel.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +In function 'abc::Abc_InfoHasBit(unsigned int*, int)', + inlined from 'abc::Abc_TtPrintBits(unsigned long long*, int)' at /build/reproducible-path/yosys-0.52/abc/src/misc/util/utilTruth.h:1597:15, + inlined from 'abc::Exa_ManExactPrint(abc::Vec_Wrd_t_*, abc::Vec_Wrd_t_*, int, int)' at src/sat/bmc/bmcMaj.c:3863:24: +/build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:303:81: warning: 'Entry' may be used uninitialized [-Wmaybe-uninitialized] + 303 | static inline int Abc_InfoHasBit( unsigned * p, int i ) { return (p[(i)>>5] & (unsigned)(1<<((i) & 31))) > 0; } + | ~~~~~~~~^ +src/sat/bmc/bmcMaj.c: In function 'abc::Exa_ManExactPrint(abc::Vec_Wrd_t_*, abc::Vec_Wrd_t_*, int, int)': +src/sat/bmc/bmcMaj.c:3861:10: note: 'Entry' declared here + 3861 | word Entry; int i; + | ^~~~~ +In function 'abc::Abc_InfoHasBit(unsigned int*, int)', + inlined from 'abc::Abc_TtPrintBits(unsigned long long*, int)' at /build/reproducible-path/yosys-0.52/abc/src/misc/util/utilTruth.h:1597:15, + inlined from 'abc::Exa_ManExactPrint(abc::Vec_Wrd_t_*, abc::Vec_Wrd_t_*, int, int)' at src/sat/bmc/bmcMaj.c:3866:24: +/build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:303:81: warning: 'Entry' may be used uninitialized [-Wmaybe-uninitialized] + 303 | static inline int Abc_InfoHasBit( unsigned * p, int i ) { return (p[(i)>>5] & (unsigned)(1<<((i) & 31))) > 0; } + | ~~~~~~~~^ +src/sat/bmc/bmcMaj.c: In function 'abc::Exa_ManExactPrint(abc::Vec_Wrd_t_*, abc::Vec_Wrd_t_*, int, int)': +src/sat/bmc/bmcMaj.c:3861:10: note: 'Entry' declared here + 3861 | word Entry; int i; + | ^~~~~ In file included from src/sat/kissat/dense.h:4, from src/sat/kissat/factor.c:4: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] @@ -14807,6 +14842,7 @@ src/sat/kissat/watch.h:14:21: note: declared here 14 | typedef union watch watch; | ^~~~~ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, from src/sat/kissat/factor.c:7: @@ -15246,6 +15282,9 @@ -> ABC: `` Compiling: /src/sat/kissat/format.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/format.c -o src/sat/kissat/format.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/forward.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/forward.c -o src/sat/kissat/forward.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -15461,12 +15500,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/forward.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/forward.c -o src/sat/kissat/forward.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/gates.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/gates.c -o src/sat/kissat/gates.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -15682,6 +15715,9 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/gates.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/gates.c -o src/sat/kissat/gates.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/heap.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/heap.c -o src/sat/kissat/heap.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -16335,6 +16371,9 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/internal.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/internal.c -o src/sat/kissat/internal.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/import.c:1: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] @@ -16548,14 +16587,9 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/internal.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/internal.c -o src/sat/kissat/internal.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/kimits.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/kimits.c -o src/sat/kissat/kimits.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/kitten.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/kitten.c -o src/sat/kissat/kitten.o In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -16594,7 +16628,6 @@ src/sat/kissat/internal.h:118:3: note: used here to mean 'typedef struct abc::flags abc::flags' 118 | flags *flags; | ^~~~~ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:13: src/sat/kissat/flags.h:9:22: note: declared here 9 | typedef struct flags flags; @@ -16772,8 +16805,14 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/kitten.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/kitten.c -o src/sat/kissat/kitten.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/krite.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/krite.c -o src/sat/kissat/krite.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, - from src/sat/kissat/kimits.c:1: + from src/sat/kissat/kitten.c:116: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] 61 | watch watch; | ^~~~~ @@ -16986,7 +17025,7 @@ 9 | typedef struct mode mode; | ^~~~ In file included from src/sat/kissat/internal.h:34, - from src/sat/kissat/kitten.c:116: + from src/sat/kissat/kimits.c:1: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] 61 | watch watch; | ^~~~~ @@ -17198,12 +17237,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/krite.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/krite.c -o src/sat/kissat/krite.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/learn.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/learn.c -o src/sat/kissat/learn.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -17419,6 +17452,15 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/learn.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/learn.c -o src/sat/kissat/learn.o +-> ABC: `` Compiling: /src/sat/kissat/logging.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/logging.c -o src/sat/kissat/logging.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/kucky.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/kucky.c -o src/sat/kissat/kucky.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -17634,12 +17676,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/logging.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/logging.c -o src/sat/kissat/logging.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/kucky.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/kucky.c -o src/sat/kissat/kucky.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/minimize.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/minimize.c -o src/sat/kissat/minimize.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -17746,22 +17782,9 @@ src/sat/kissat/internal.h:175:9: warning: declaration of 'abc::arena abc::kissat::arena' changes meaning of 'arena' [-Wchanges-meaning] 175 | arena arena; | ^~~~~ -In file included from src/sat/kissat/internal.h:34, - from src/sat/kissat/inlinevector.h:4, - from src/sat/kissat/inline.h:4, - from src/sat/kissat/minimize.c:2: -src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] - 61 | watch watch; - | ^~~~~ src/sat/kissat/internal.h:175:3: note: used here to mean 'typedef struct abc::arena abc::arena' 175 | arena arena; | ^~~~~ -src/sat/kissat/watch.h:61:3: note: used here to mean 'typedef union abc::watch abc::watch' - 61 | watch watch; - | ^~~~~ -src/sat/kissat/watch.h:14:21: note: declared here - 14 | typedef union watch watch; - | ^~~~~ In file included from src/sat/kissat/internal.h:4: src/sat/kissat/arena.h:25:22: note: declared here 25 | typedef STACK (ward) arena; @@ -17801,6 +17824,89 @@ src/sat/kissat/internal.h:188:3: note: used here to mean 'typedef struct abc::reluctant abc::reluctant' 188 | reluctant reluctant; | ^~~~~~~~~ +In file included from src/sat/kissat/internal.h:27: +src/sat/kissat/reluctant.h:10:26: note: declared here + 10 | typedef struct reluctant reluctant; + | ^~~~~~~~~ +src/sat/kissat/internal.h:190:10: warning: declaration of 'abc::bounds abc::kissat::bounds' changes meaning of 'bounds' [-Wchanges-meaning] + 190 | bounds bounds; + | ^~~~~~ +src/sat/kissat/internal.h:190:3: note: used here to mean 'typedef struct abc::bounds abc::bounds' + 190 | bounds bounds; + | ^~~~~~ +In file included from src/sat/kissat/internal.h:17: +src/sat/kissat/kimits.h:10:23: note: declared here + 10 | typedef struct bounds bounds; + | ^~~~~~ +src/sat/kissat/internal.h:191:18: warning: declaration of 'abc::classification abc::kissat::classification' changes meaning of 'classification' [-Wchanges-meaning] + 191 | classification classification; + | ^~~~~~~~~~~~~~ +src/sat/kissat/internal.h:191:3: note: used here to mean 'typedef struct abc::classification abc::classification' + 191 | classification classification; + | ^~~~~~~~~~~~~~ +In file included from src/sat/kissat/internal.h:9: +src/sat/kissat/classify.h:16:31: note: declared here + 16 | typedef struct classification classification; + | ^~~~~~~~~~~~~~ +src/sat/kissat/internal.h:192:10: warning: declaration of 'abc::delays abc::kissat::delays' changes meaning of 'delays' [-Wchanges-meaning] + 192 | delays delays; + | ^~~~~~ +src/sat/kissat/internal.h:192:3: note: used here to mean 'typedef struct abc::delays abc::delays' + 192 | delays delays; + | ^~~~~~ +src/sat/kissat/kimits.h:12:23: note: declared here + 12 | typedef struct delays delays; + | ^~~~~~ +src/sat/kissat/internal.h:193:11: warning: declaration of 'abc::enabled abc::kissat::enabled' changes meaning of 'enabled' [-Wchanges-meaning] + 193 | enabled enabled; + | ^~~~~~~ +src/sat/kissat/internal.h:193:3: note: used here to mean 'typedef struct abc::enabled abc::enabled' + 193 | enabled enabled; + | ^~~~~~~ +src/sat/kissat/kimits.h:15:24: note: declared here + 15 | typedef struct enabled enabled; + | ^~~~~~~ +src/sat/kissat/internal.h:194:11: warning: declaration of 'abc::limited abc::kissat::limited' changes meaning of 'limited' [-Wchanges-meaning] + 194 | limited limited; + | ^~~~~~~ +src/sat/kissat/internal.h:194:3: note: used here to mean 'typedef struct abc::limited abc::limited' + 194 | limited limited; + | ^~~~~~~ +src/sat/kissat/kimits.h:16:24: note: declared here + 16 | typedef struct limited limited; + | ^~~~~~~ +src/sat/kissat/internal.h:195:10: warning: declaration of 'abc::limits abc::kissat::limits' changes meaning of 'limits' [-Wchanges-meaning] + 195 | limits limits; + | ^~~~~~ +src/sat/kissat/internal.h:195:3: note: used here to mean 'typedef struct abc::limits abc::limits' + 195 | limits limits; + | ^~~~~~ +src/sat/kissat/kimits.h:17:23: note: declared here + 17 | typedef struct limits limits; + | ^~~~~~ +src/sat/kissat/internal.h:199:8: warning: declaration of 'abc::mode abc::kissat::mode' changes meaning of 'mode' [-Wchanges-meaning] + 199 | mode mode; + | ^~~~ +src/sat/kissat/internal.h:199:3: note: used here to mean 'typedef struct abc::mode abc::mode' + 199 | mode mode; + | ^~~~ +In file included from src/sat/kissat/internal.h:20: +src/sat/kissat/mode.h:9:21: note: declared here + 9 | typedef struct mode mode; + | ^~~~ +In file included from src/sat/kissat/internal.h:34, + from src/sat/kissat/inlinevector.h:4, + from src/sat/kissat/inline.h:4, + from src/sat/kissat/minimize.c:2: +src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] + 61 | watch watch; + | ^~~~~ +src/sat/kissat/watch.h:61:3: note: used here to mean 'typedef union abc::watch abc::watch' + 61 | watch watch; + | ^~~~~ +src/sat/kissat/watch.h:14:21: note: declared here + 14 | typedef union watch watch; + | ^~~~~ src/sat/kissat/internal.h:104:15: warning: declaration of 'abc::termination abc::kissat::termination' changes meaning of 'termination' [-Wchanges-meaning] 104 | termination termination; | ^~~~~~~~~~~ @@ -17836,49 +17942,29 @@ src/sat/kissat/internal.h:123:3: note: used here to mean 'typedef struct abc::phases abc::phases' 123 | phases phases; | ^~~~~~ -In file included from src/sat/kissat/internal.h:27: -src/sat/kissat/reluctant.h:10:26: note: declared here - 10 | typedef struct reluctant reluctant; - | ^~~~~~~~~ In file included from src/sat/kissat/internal.h:22: src/sat/kissat/phases.h:9:23: note: declared here 9 | typedef struct phases phases; | ^~~~~~ -src/sat/kissat/internal.h:190:10: warning: declaration of 'abc::bounds abc::kissat::bounds' changes meaning of 'bounds' [-Wchanges-meaning] - 190 | bounds bounds; - | ^~~~~~ src/sat/kissat/internal.h:125:14: warning: declaration of 'abc::eliminated abc::kissat::eliminated' changes meaning of 'eliminated' [-Wchanges-meaning] 125 | eliminated eliminated; | ^~~~~~~~~~ src/sat/kissat/internal.h:125:3: note: used here to mean 'typedef struct abc::eliminated abc::eliminated' 125 | eliminated eliminated; | ^~~~~~~~~~ -src/sat/kissat/internal.h:190:3: note: used here to mean 'typedef struct abc::bounds abc::bounds' - 190 | bounds bounds; - | ^~~~~~ src/sat/kissat/internal.h:69:23: note: declared here 69 | typedef STACK (value) eliminated; | ^~~~~~~~~~ src/sat/kissat/internal.h:128:10: warning: declaration of 'abc::links* abc::kissat::links' changes meaning of 'links' [-Wchanges-meaning] 128 | links *links; | ^~~~~ -In file included from src/sat/kissat/internal.h:17: -src/sat/kissat/kimits.h:10:23: note: declared here - 10 | typedef struct bounds bounds; - | ^~~~~~ src/sat/kissat/internal.h:128:3: note: used here to mean 'typedef struct abc::links abc::links' 128 | links *links; | ^~~~~ -src/sat/kissat/internal.h:191:18: warning: declaration of 'abc::classification abc::kissat::classification' changes meaning of 'classification' [-Wchanges-meaning] - 191 | classification classification; - | ^~~~~~~~~~~~~~ In file included from src/sat/kissat/internal.h:25: src/sat/kissat/queue.h:12:22: note: declared here 12 | typedef struct links links; | ^~~~~ -src/sat/kissat/internal.h:191:3: note: used here to mean 'typedef struct abc::classification abc::classification' - 191 | classification classification; - | ^~~~~~~~~~~~~~ src/sat/kissat/internal.h:129:9: warning: declaration of 'abc::queue abc::kissat::queue' changes meaning of 'queue' [-Wchanges-meaning] 129 | queue queue; | ^~~~~ @@ -17888,50 +17974,19 @@ src/sat/kissat/queue.h:13:22: note: declared here 13 | typedef struct queue queue; | ^~~~~ -In file included from src/sat/kissat/internal.h:9: -src/sat/kissat/classify.h:16:31: note: declared here - 16 | typedef struct classification classification; - | ^~~~~~~~~~~~~~ src/sat/kissat/internal.h:138:10: warning: declaration of 'abc::frames abc::kissat::frames' changes meaning of 'frames' [-Wchanges-meaning] 138 | frames frames; | ^~~~~~ -src/sat/kissat/internal.h:192:10: warning: declaration of 'abc::delays abc::kissat::delays' changes meaning of 'delays' [-Wchanges-meaning] - 192 | delays delays; - | ^~~~~~ src/sat/kissat/internal.h:138:3: note: used here to mean 'typedef struct abc::frames abc::frames' 138 | frames frames; | ^~~~~~ -src/sat/kissat/internal.h:192:3: note: used here to mean 'typedef struct abc::delays abc::delays' - 192 | delays delays; - | ^~~~~~ -src/sat/kissat/kimits.h:12:23: note: declared here - 12 | typedef struct delays delays; - | ^~~~~~ In file included from src/sat/kissat/internal.h:15: src/sat/kissat/frames.h:27:23: note: declared here 27 | typedef STACK (frame) frames; | ^~~~~~ -src/sat/kissat/internal.h:193:11: warning: declaration of 'abc::enabled abc::kissat::enabled' changes meaning of 'enabled' [-Wchanges-meaning] - 193 | enabled enabled; - | ^~~~~~~ -src/sat/kissat/internal.h:193:3: note: used here to mean 'typedef struct abc::enabled abc::enabled' - 193 | enabled enabled; - | ^~~~~~~ -src/sat/kissat/kimits.h:15:24: note: declared here - 15 | typedef struct enabled enabled; - | ^~~~~~~ -src/sat/kissat/internal.h:194:11: warning: declaration of 'abc::limited abc::kissat::limited' changes meaning of 'limited' [-Wchanges-meaning] - 194 | limited limited; - | ^~~~~~~ -src/sat/kissat/internal.h:194:3: note: used here to mean 'typedef struct abc::limited abc::limited' - 194 | limited limited; - | ^~~~~~~ src/sat/kissat/internal.h:172:13: warning: declaration of 'abc::unsigneds abc::kissat::clause' changes meaning of 'clause' [-Wchanges-meaning] 172 | unsigneds clause; | ^~~~~~ -src/sat/kissat/kimits.h:16:24: note: declared here - 16 | typedef struct limited limited; - | ^~~~~~~ src/sat/kissat/internal.h:166:3: note: used here to mean 'typedef struct abc::clause abc::clause' 166 | clause conflict; | ^~~~~~ @@ -17939,41 +17994,22 @@ src/sat/kissat/clause.h:14:23: note: declared here 14 | typedef struct clause clause; | ^~~~~~ -src/sat/kissat/internal.h:195:10: warning: declaration of 'abc::limits abc::kissat::limits' changes meaning of 'limits' [-Wchanges-meaning] - 195 | limits limits; - | ^~~~~~ -src/sat/kissat/internal.h:195:3: note: used here to mean 'typedef struct abc::limits abc::limits' - 195 | limits limits; - | ^~~~~~ src/sat/kissat/internal.h:175:9: warning: declaration of 'abc::arena abc::kissat::arena' changes meaning of 'arena' [-Wchanges-meaning] 175 | arena arena; | ^~~~~ -src/sat/kissat/kimits.h:17:23: note: declared here - 17 | typedef struct limits limits; - | ^~~~~~ src/sat/kissat/internal.h:175:3: note: used here to mean 'typedef struct abc::arena abc::arena' 175 | arena arena; | ^~~~~ -src/sat/kissat/internal.h:199:8: warning: declaration of 'abc::mode abc::kissat::mode' changes meaning of 'mode' [-Wchanges-meaning] - 199 | mode mode; - | ^~~~ In file included from src/sat/kissat/internal.h:4: src/sat/kissat/arena.h:25:22: note: declared here 25 | typedef STACK (ward) arena; | ^~~~~ -src/sat/kissat/internal.h:199:3: note: used here to mean 'typedef struct abc::mode abc::mode' - 199 | mode mode; - | ^~~~ src/sat/kissat/internal.h:176:11: warning: declaration of 'abc::vectors abc::kissat::vectors' changes meaning of 'vectors' [-Wchanges-meaning] 176 | vectors vectors; | ^~~~~~~ src/sat/kissat/internal.h:176:3: note: used here to mean 'typedef struct abc::vectors abc::vectors' 176 | vectors vectors; | ^~~~~~~ -In file included from src/sat/kissat/internal.h:20: -src/sat/kissat/mode.h:9:21: note: declared here - 9 | typedef struct mode mode; - | ^~~~ In file included from src/sat/kissat/internal.h:33: src/sat/kissat/vector.h:25:24: note: declared here 25 | typedef struct vectors vectors; @@ -18076,9 +18112,6 @@ -> ABC: `` Compiling: /src/sat/kissat/mode.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/mode.c -o src/sat/kissat/mode.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/kptions.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/kptions.c -o src/sat/kissat/kptions.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -18294,6 +18327,9 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/kptions.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/kptions.c -o src/sat/kissat/kptions.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/phases.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/phases.c -o src/sat/kissat/phases.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -19832,6 +19868,9 @@ -> ABC: `` Compiling: /src/sat/kissat/propsearch.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/propsearch.c -o src/sat/kissat/propsearch.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/queue.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/queue.c -o src/sat/kissat/queue.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -20048,9 +20087,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/queue.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/queue.c -o src/sat/kissat/queue.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -20267,6 +20303,9 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/reduce.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/reduce.c -o src/sat/kissat/reduce.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -20482,14 +20521,12 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/reduce.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/reduce.c -o src/sat/kissat/reduce.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/reluctant.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/reluctant.c -o src/sat/kissat/reluctant.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, - from src/sat/kissat/reluctant.c:1: + from src/sat/kissat/collect.h:4, + from src/sat/kissat/reduce.c:3: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] 61 | watch watch; | ^~~~~ @@ -20701,12 +20738,8 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/reorder.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/reorder.c -o src/sat/kissat/reorder.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, - from src/sat/kissat/collect.h:4, - from src/sat/kissat/reduce.c:3: + from src/sat/kissat/reluctant.c:1: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] 61 | watch watch; | ^~~~~ @@ -20716,6 +20749,8 @@ src/sat/kissat/watch.h:14:21: note: declared here 14 | typedef union watch watch; | ^~~~~ +-> ABC: `` Compiling: /src/sat/kissat/reorder.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/reorder.c -o src/sat/kissat/reorder.o src/sat/kissat/internal.h:104:15: warning: declaration of 'abc::termination abc::kissat::termination' changes meaning of 'termination' [-Wchanges-meaning] 104 | termination termination; | ^~~~~~~~~~~ @@ -20918,9 +20953,13 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/rephase.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/rephase.c -o src/sat/kissat/rephase.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/report.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/report.c -o src/sat/kissat/report.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -21136,6 +21175,8 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/resize.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/resize.c -o src/sat/kissat/resize.o In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/rephase.c:4: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] @@ -21263,6 +21304,7 @@ src/sat/kissat/watch.h:49:16: note: declared here 49 | typedef vector watches; | ^~~~~~~ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/sat/kissat/internal.h:186:12: warning: declaration of 'abc::averages abc::kissat::averages [2]' changes meaning of 'averages' [-Wchanges-meaning] 186 | averages averages[2]; | ^~~~~~~~ @@ -21349,11 +21391,8 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/report.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/report.c -o src/sat/kissat/report.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/resize.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/resize.c -o src/sat/kissat/resize.o +-> ABC: `` Compiling: /src/sat/kissat/resolve.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/resolve.c -o src/sat/kissat/resolve.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, @@ -21570,14 +21609,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/resolve.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/resolve.c -o src/sat/kissat/resolve.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/resources.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/resources.c -o src/sat/kissat/resources.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/restart.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/restart.c -o src/sat/kissat/restart.o In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -21707,7 +21738,6 @@ src/sat/kissat/watch.h:49:16: note: declared here 49 | typedef vector watches; | ^~~~~~~ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/sat/kissat/internal.h:186:12: warning: declaration of 'abc::averages abc::kissat::averages [2]' changes meaning of 'averages' [-Wchanges-meaning] 186 | averages averages[2]; | ^~~~~~~~ @@ -21794,6 +21824,12 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/resources.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/resources.c -o src/sat/kissat/resources.o +-> ABC: `` Compiling: /src/sat/kissat/restart.c +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/restart.c -o src/sat/kissat/restart.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/search.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/search.c -o src/sat/kissat/search.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -22010,6 +22046,12 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +-> ABC: `` Compiling: /src/sat/kissat/shrink.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/shrink.c -o src/sat/kissat/shrink.o +-> ABC: `` Compiling: /src/sat/kissat/smooth.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/smooth.c -o src/sat/kissat/smooth.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -22225,15 +22267,12 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/shrink.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/shrink.c -o src/sat/kissat/shrink.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/smooth.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/smooth.c -o src/sat/kissat/smooth.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/sort.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/sort.c -o src/sat/kissat/sort.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/stack.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/stack.c -o src/sat/kissat/stack.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -22685,6 +22724,8 @@ src/sat/kissat/internal.h:117:13: warning: declaration of 'abc::assigned* abc::kissat::assigned' changes meaning of 'assigned' [-Wchanges-meaning] 117 | assigned *assigned; | ^~~~~~~~ +-> ABC: `` Compiling: /src/sat/kissat/statistics.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/statistics.c -o src/sat/kissat/statistics.o src/sat/kissat/internal.h:117:3: note: used here to mean 'typedef struct abc::assigned abc::assigned' 117 | assigned *assigned; | ^~~~~~~~ @@ -22875,20 +22916,18 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/stack.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/stack.c -o src/sat/kissat/stack.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/statistics.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/statistics.c -o src/sat/kissat/statistics.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/strengthen.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/strengthen.c -o src/sat/kissat/strengthen.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/substitute.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/substitute.c -o src/sat/kissat/substitute.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/sat/kissat/sweep.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/sweep.c -o src/sat/kissat/sweep.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/terminate.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/terminate.c -o src/sat/kissat/terminate.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/dense.h:4, from src/sat/kissat/sweep.c:2: @@ -22977,22 +23016,9 @@ src/sat/kissat/internal.h:129:3: note: used here to mean 'typedef struct abc::queue abc::queue' 129 | queue queue; | ^~~~~ -In file included from src/sat/kissat/internal.h:34, - from src/sat/kissat/inlinevector.h:4, - from src/sat/kissat/inline.h:4, - from src/sat/kissat/substitute.c:4: -src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] - 61 | watch watch; - | ^~~~~ src/sat/kissat/queue.h:13:22: note: declared here 13 | typedef struct queue queue; | ^~~~~ -src/sat/kissat/watch.h:61:3: note: used here to mean 'typedef union abc::watch abc::watch' - 61 | watch watch; - | ^~~~~ -src/sat/kissat/watch.h:14:21: note: declared here - 14 | typedef union watch watch; - | ^~~~~ src/sat/kissat/internal.h:138:10: warning: declaration of 'abc::frames abc::kissat::frames' changes meaning of 'frames' [-Wchanges-meaning] 138 | frames frames; | ^~~~~~ @@ -23128,6 +23154,9 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ +In file included from src/sat/kissat/inlinevector.h:4, + from src/sat/kissat/inline.h:4, + from src/sat/kissat/sweep.c:3: src/sat/kissat/internal.h:104:15: warning: declaration of 'abc::termination abc::kissat::termination' changes meaning of 'termination' [-Wchanges-meaning] 104 | termination termination; | ^~~~~~~~~~~ @@ -23231,7 +23260,7 @@ src/sat/kissat/internal.h:176:3: note: used here to mean 'typedef struct abc::vectors abc::vectors' 176 | vectors vectors; | ^~~~~~~ -In file included from src/sat/kissat/internal.h:33: +In file included from src/sat/kissat/watch.h:7: src/sat/kissat/vector.h:25:24: note: declared here 25 | typedef struct vectors vectors; | ^~~~~~~ @@ -23330,9 +23359,19 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ -In file included from src/sat/kissat/inlinevector.h:4, +In file included from src/sat/kissat/internal.h:34, + from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, - from src/sat/kissat/sweep.c:3: + from src/sat/kissat/substitute.c:4: +src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] + 61 | watch watch; + | ^~~~~ +src/sat/kissat/watch.h:61:3: note: used here to mean 'typedef union abc::watch abc::watch' + 61 | watch watch; + | ^~~~~ +src/sat/kissat/watch.h:14:21: note: declared here + 14 | typedef union watch watch; + | ^~~~~ src/sat/kissat/internal.h:104:15: warning: declaration of 'abc::termination abc::kissat::termination' changes meaning of 'termination' [-Wchanges-meaning] 104 | termination termination; | ^~~~~~~~~~~ @@ -23436,7 +23475,7 @@ src/sat/kissat/internal.h:176:3: note: used here to mean 'typedef struct abc::vectors abc::vectors' 176 | vectors vectors; | ^~~~~~~ -In file included from src/sat/kissat/watch.h:7: +In file included from src/sat/kissat/internal.h:33: src/sat/kissat/vector.h:25:24: note: declared here 25 | typedef struct vectors vectors; | ^~~~~~~ @@ -23535,9 +23574,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/terminate.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/terminate.c -o src/sat/kissat/terminate.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/terminate.h:4, from src/sat/kissat/terminate.c:1: @@ -24410,6 +24446,9 @@ -> ABC: `` Compiling: /src/sat/kissat/vector.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/vector.c -o src/sat/kissat/vector.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/vivify.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/vivify.c -o src/sat/kissat/vivify.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/collect.h:4, from src/sat/kissat/vector.c:2: @@ -24624,12 +24663,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/vivify.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/vivify.c -o src/sat/kissat/vivify.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/sat/kissat/walk.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/walk.c -o src/sat/kissat/walk.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/collect.h:4, from src/sat/kissat/vivify.c:4: @@ -24719,17 +24752,6 @@ src/sat/kissat/frames.h:27:23: note: declared here 27 | typedef STACK (frame) frames; | ^~~~~~ -In file included from src/sat/kissat/dense.h:4, - from src/sat/kissat/walk.c:4: -src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] - 61 | watch watch; - | ^~~~~ -src/sat/kissat/watch.h:61:3: note: used here to mean 'typedef union abc::watch abc::watch' - 61 | watch watch; - | ^~~~~ -src/sat/kissat/watch.h:14:21: note: declared here - 14 | typedef union watch watch; - | ^~~~~ src/sat/kissat/internal.h:172:13: warning: declaration of 'abc::unsigneds abc::kissat::clause' changes meaning of 'clause' [-Wchanges-meaning] 172 | unsigneds clause; | ^~~~~~ @@ -24864,6 +24886,20 @@ src/sat/kissat/vivify.c:150:26: note: declared here 150 | typedef STACK (countref) countrefs; | ^~~~~~~~~ +-> ABC: `` Compiling: /src/sat/kissat/walk.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/walk.c -o src/sat/kissat/walk.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +In file included from src/sat/kissat/dense.h:4, + from src/sat/kissat/walk.c:4: +src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] + 61 | watch watch; + | ^~~~~ +src/sat/kissat/watch.h:61:3: note: used here to mean 'typedef union abc::watch abc::watch' + 61 | watch watch; + | ^~~~~ +src/sat/kissat/watch.h:14:21: note: declared here + 14 | typedef union watch watch; + | ^~~~~ In file included from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, from src/sat/kissat/walk.c:5: @@ -25072,6 +25108,9 @@ -> ABC: `` Compiling: /src/sat/kissat/warmup.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/warmup.c -o src/sat/kissat/warmup.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/sat/kissat/watch.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/watch.c -o src/sat/kissat/watch.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/warmup.c:4: src/sat/kissat/watch.h:61:9: warning: declaration of 'abc::watch abc::litwatch::watch' changes meaning of 'watch' [-Wchanges-meaning] @@ -25285,9 +25324,6 @@ src/sat/kissat/mode.h:9:21: note: declared here 9 | typedef struct mode mode; | ^~~~ --> ABC: `` Compiling: /src/sat/kissat/watch.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/kissat/watch.c -o src/sat/kissat/watch.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from src/sat/kissat/internal.h:34, from src/sat/kissat/inlinevector.h:4, from src/sat/kissat/inline.h:4, @@ -25730,9 +25766,6 @@ -> ABC: `` Compiling: /src/sat/cadical/cadical_kitten.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/sat/cadical/cadical_kitten.c -o src/sat/cadical/cadical_kitten.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/bool/bdc/bdcCore.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/bdc/bdcCore.c -o src/bool/bdc/bdcCore.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/sat/cadical/cadical_kitten.c:198:14: warning: declaration of 'abc::statistics abc::cadical_kitten::statistics' changes meaning of 'statistics' [-Wchanges-meaning] 198 | statistics statistics; | ^~~~~~~~~~ @@ -25749,6 +25782,9 @@ src/sat/cadical/cadical_kitten.c:2528:16: warning: unused variable 'ignoring' [-Wunused-variable] 2528 | const bool ignoring = i; | ^~~~~~~~ +-> ABC: `` Compiling: /src/bool/bdc/bdcCore.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/bdc/bdcCore.c -o src/bool/bdc/bdcCore.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bool/bdc/bdcDec.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/bdc/bdcDec.c -o src/bool/bdc/bdcDec.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -25764,6 +25800,9 @@ -> ABC: `` Compiling: /src/bool/dec/decFactor.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/dec/decFactor.c -o src/bool/dec/decFactor.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/bool/dec/decMan.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/dec/decMan.c -o src/bool/dec/decMan.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/bool/bdc/bdcSpfd.c: In function 'abc::Bdc_SpfdDecomposeTest__(abc::Vec_Int_t_**)': src/bool/bdc/bdcSpfd.c:602:28: warning: product '250000000 * 24' of arguments 1 and 2 exceeds 'SIZE_MAX' [-Walloc-size-larger-than=] 602 | p = (Bdc_Ent_t *)calloc( nFuncs, sizeof(Bdc_Ent_t) ); @@ -25776,9 +25815,6 @@ /usr/include/stdlib.h:675:14: note: in a call to allocation function 'calloc' declared here 675 | extern void *calloc (size_t __nmemb, size_t __size) | ^~~~~~ --> ABC: `` Compiling: /src/bool/dec/decMan.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/dec/decMan.c -o src/bool/dec/decMan.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bool/dec/decPrint.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/dec/decPrint.c -o src/bool/dec/decPrint.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -25793,10 +25829,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bool/kit/kitCloud.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/kit/kitCloud.c -o src/bool/kit/kitCloud.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bool/kit/cloud.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/kit/cloud.c -o src/bool/kit/cloud.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bool/kit/kitDsd.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/kit/kitDsd.c -o src/bool/kit/kitDsd.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -25815,18 +25851,18 @@ -> ABC: `` Compiling: /src/bool/kit/kitPla.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/kit/kitPla.c -o src/bool/kit/kitPla.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -In file included from src/bool/kit/kitDsd.c:21: -In function 'abc::Kit_DsdLitSupport(abc::Kit_DsdNtk_t_*, int)', - inlined from 'abc::Kit_DsdGetSupports(abc::Kit_DsdNtk_t_*)' at src/bool/kit/kitDsd.c:1779:52: -src/bool/kit/kit.h:156:203: warning: '*_54' may be used uninitialized [-Wmaybe-uninitialized] - 156 | static inline unsigned Kit_DsdLitSupport( Kit_DsdNtk_t * pNtk, int Lit ) { int Id = Abc_Lit2Var(Lit); assert( Id >= 0 && Id < pNtk->nVars + pNtk->nNodes ); return pNtk->pSupps? (Id < pNtk->nVars? (1 << Id) : pNtk->pSupps[Id - pNtk->nVars]) : 0; } - | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -> ABC: `` Compiling: /src/bool/kit/kitSop.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/kit/kitSop.c -o src/bool/kit/kitSop.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bool/kit/kitTruth.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/kit/kitTruth.c -o src/bool/kit/kitTruth.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +In file included from src/bool/kit/kitDsd.c:21: +In function 'abc::Kit_DsdLitSupport(abc::Kit_DsdNtk_t_*, int)', + inlined from 'abc::Kit_DsdGetSupports(abc::Kit_DsdNtk_t_*)' at src/bool/kit/kitDsd.c:1779:52: +src/bool/kit/kit.h:156:203: warning: '*_54' may be used uninitialized [-Wmaybe-uninitialized] + 156 | static inline unsigned Kit_DsdLitSupport( Kit_DsdNtk_t * pNtk, int Lit ) { int Id = Abc_Lit2Var(Lit); assert( Id >= 0 && Id < pNtk->nVars + pNtk->nNodes ); return pNtk->pSupps? (Id < pNtk->nVars? (1 << Id) : pNtk->pSupps[Id - pNtk->nVars]) : 0; } + | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -> ABC: `` Compiling: /src/bool/lucky/lucky.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bool/lucky/lucky.c -o src/bool/lucky/lucky.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -25920,13 +25956,6 @@ -> ABC: `` Compiling: /src/proof/abs/absOldRef.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/abs/absOldRef.c -o src/proof/abs/absOldRef.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -src/proof/abs/absGlaOld.c: In function 'abc::Gia_ManPerformGlaOld(abc::Gia_Man_t_*, abc::Abs_Par_t_*, int)': -src/proof/abs/absGlaOld.c:1896:43: warning: 'Status' may be used uninitialized [-Wmaybe-uninitialized] - 1896 | if ( p->pPars->fVerbose && Status == -1 ) - | ~~~~~~~^~~~~ -src/proof/abs/absGlaOld.c:1645:31: note: 'Status' declared here - 1645 | int f, i, iPrev, nConfls, Status, nVarsOld = 0, nCoreSize, fOneIsSent = 0, RetValue = -1; - | ^~~~~~ -> ABC: `` Compiling: /src/proof/abs/absOldSat.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/abs/absOldSat.c -o src/proof/abs/absOldSat.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -25936,6 +25965,13 @@ -> ABC: `` Compiling: /src/proof/abs/absOut.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/abs/absOut.c -o src/proof/abs/absOut.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +src/proof/abs/absGlaOld.c: In function 'abc::Gia_ManPerformGlaOld(abc::Gia_Man_t_*, abc::Abs_Par_t_*, int)': +src/proof/abs/absGlaOld.c:1896:43: warning: 'Status' may be used uninitialized [-Wmaybe-uninitialized] + 1896 | if ( p->pPars->fVerbose && Status == -1 ) + | ~~~~~~~^~~~~ +src/proof/abs/absGlaOld.c:1645:31: note: 'Status' declared here + 1645 | int f, i, iPrev, nConfls, Status, nVarsOld = 0, nCoreSize, fOneIsSent = 0, RetValue = -1; + | ^~~~~~ -> ABC: `` Compiling: /src/proof/abs/absPth.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/abs/absPth.c -o src/proof/abs/absPth.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -25983,10 +26019,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/live/combination.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/live/combination.c -o src/proof/live/combination.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/ssc/sscClass.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssc/sscClass.c -o src/proof/ssc/sscClass.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/ssc/sscCore.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssc/sscCore.c -o src/proof/ssc/sscCore.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -26065,8 +26101,6 @@ -> ABC: `` Compiling: /src/proof/cec/cecSatG2.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/cec/cecSatG2.c -o src/proof/cec/cecSatG2.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/proof/cec/cecSatG3.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/cec/cecSatG3.c -o src/proof/cec/cecSatG3.o src/proof/cec/cecSatG2.c: In function 'void abc::exportSimValues(Gia_Man_t*, char*)': src/proof/cec/cecSatG2.c:3910:36: warning: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'abc::word' {aka 'long long unsigned int'} [-Wformat=] 3910 | fprintf( pFile, "[%d]: %lu ", j, pSim[j] ); @@ -26075,6 +26109,8 @@ | | abc::word {aka long long unsigned int} | long unsigned int | %llu +-> ABC: `` Compiling: /src/proof/cec/cecSatG3.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/cec/cecSatG3.c -o src/proof/cec/cecSatG3.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/cec/cecSeq.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/cec/cecSeq.c -o src/proof/cec/cecSeq.o @@ -26106,6 +26142,9 @@ -> ABC: `` Compiling: /src/proof/acec/acecCo.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/acec/acecCo.c -o src/proof/acec/acecCo.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/proof/acec/acecBo.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/acec/acecBo.c -o src/proof/acec/acecBo.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vec.h:31, from /build/reproducible-path/yosys-0.52/abc/src/aig/gia/gia.h:34, from src/proof/acec/acecInt.h:29, @@ -26121,9 +26160,6 @@ /build/reproducible-path/yosys-0.52/abc/src/misc/util/abc_global.h:267:48: note: call to 'free' here 267 | #define ABC_FREE(obj) ((obj) ? (free((char *) (obj)), (obj) = 0) : 0) | ~~~~^~~~~~~~~~~~~~~~ --> ABC: `` Compiling: /src/proof/acec/acecBo.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/acec/acecBo.c -o src/proof/acec/acecBo.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/acec/acecRe.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/acec/acecRe.c -o src/proof/acec/acecRe.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -26228,10 +26264,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/fraig/fraigTable.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fraig/fraigTable.c -o src/proof/fraig/fraigTable.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/fraig/fraigUtil.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fraig/fraigUtil.c -o src/proof/fraig/fraigUtil.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/fraig/fraigVec.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fraig/fraigVec.c -o src/proof/fraig/fraigVec.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -26275,10 +26311,10 @@ g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fra/fraMan.c -o src/proof/fra/fraMan.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/fra/fraPart.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fra/fraPart.c -o src/proof/fra/fraPart.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/fra/fraSat.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fra/fraSat.c -o src/proof/fra/fraSat.o +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fra/fraPart.c -o src/proof/fra/fraPart.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/fra/fraSec.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/fra/fraSec.c -o src/proof/fra/fraSec.o @@ -26324,10 +26360,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/ssw/sswPairs.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswPairs.c -o src/proof/ssw/sswPairs.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/ssw/sswRarity.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswRarity.c -o src/proof/ssw/sswRarity.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/proof/ssw/sswSat.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/proof/ssw/sswSat.c -o src/proof/ssw/sswSat.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -26387,10 +26423,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/aig/aigOper.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigOper.c -o src/aig/aig/aigOper.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/aig/aigOrder.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigOrder.c -o src/aig/aig/aigOrder.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/aig/aigPack.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/aig/aigPack.c -o src/aig/aig/aigPack.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -26477,10 +26513,10 @@ cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/saig/saigPhase.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/saig/saigPhase.c -o src/aig/saig/saigPhase.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/saig/saigRetFwd.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/saig/saigRetFwd.c -o src/aig/saig/saigRetFwd.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/saig/saigRetMin.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/saig/saigRetMin.c -o src/aig/saig/saigRetMin.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -26610,6 +26646,12 @@ -> ABC: `` Compiling: /src/aig/gia/giaEsop.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaEsop.c -o src/aig/gia/giaEsop.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/aig/gia/giaExist.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaExist.c -o src/aig/gia/giaExist.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/aig/gia/giaFalse.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaFalse.c -o src/aig/gia/giaFalse.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vec.h:29, from src/aig/gia/gia.h:34, from src/aig/gia/giaEquiv.c:21: @@ -26623,12 +26665,6 @@ /usr/include/stdlib.h:675:14: note: in a call to allocation function 'calloc' declared here 675 | extern void *calloc (size_t __nmemb, size_t __size) | ^~~~~~ --> ABC: `` Compiling: /src/aig/gia/giaExist.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaExist.c -o src/aig/gia/giaExist.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/aig/gia/giaFalse.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaFalse.c -o src/aig/gia/giaFalse.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/gia/giaFanout.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaFanout.c -o src/aig/gia/giaFanout.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -26729,6 +26765,9 @@ -> ABC: `` Compiling: /src/aig/gia/giaMf.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMf.c -o src/aig/gia/giaMf.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/aig/gia/giaMan.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMan.c -o src/aig/gia/giaMan.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In function 'abc::Lf_MemLoadMuxCut(abc::Lf_Man_t_*, int, abc::Lf_Cut_t_*)', inlined from 'abc::Lf_ObjCutBestNew(abc::Lf_Man_t_*, int, abc::Lf_Cut_t_*)' at src/aig/gia/giaLf.c:614:32, inlined from 'abc::Lf_CutRef_rec(abc::Lf_Man_t_*, abc::Lf_Cut_t_*)' at src/aig/gia/giaLf.c:1082:35: @@ -26789,6 +26828,9 @@ src/aig/gia/giaLf.c:52:21: note: while referencing 'pLeaves' 52 | int pLeaves[0]; // leaves | ^~~~~~~ +-> ABC: `` Compiling: /src/aig/gia/giaMem.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMem.c -o src/aig/gia/giaMem.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In function 'abc::Lf_CutCreateUnit(abc::Lf_Cut_t_*, int)', inlined from 'abc::Lf_ManPrepareSet(abc::Lf_Man_t_*, int, int, abc::Lf_Cut_t_**)' at src/aig/gia/giaLf.c:400:32, inlined from 'abc::Lf_ObjMergeOrder(abc::Lf_Man_t_*, int)' at src/aig/gia/giaLf.c:1200:38: @@ -26859,11 +26901,8 @@ src/aig/gia/giaLf.c:52:21: note: while referencing 'pLeaves' 52 | int pLeaves[0]; // leaves | ^~~~~~~ --> ABC: `` Compiling: /src/aig/gia/giaMan.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMan.c -o src/aig/gia/giaMan.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/aig/gia/giaMem.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMem.c -o src/aig/gia/giaMem.o +-> ABC: `` Compiling: /src/aig/gia/giaMfs.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMfs.c -o src/aig/gia/giaMfs.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/aig/gia/giaMan.c: In function 'abc::Gia_ManDumpVerilogNoInter(abc::Gia_Man_t_*, char*, abc::Vec_Int_t_*, int, int)': src/aig/gia/giaMan.c:1387:30: warning: '%0*d' directive writing between 1 and 2147483647 bytes into a region of size 9999 [-Wformat-overflow=] @@ -27416,9 +27455,6 @@ | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 | __va_arg_pack ()); | ~~~~~~~~~~~~~~~~~ --> ABC: `` Compiling: /src/aig/gia/giaMfs.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMfs.c -o src/aig/gia/giaMfs.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/aig/gia/giaMan.c: In function 'abc::Gia_ManDumpInterface(abc::Gia_Man_t_*, char*)': src/aig/gia/giaMan.c:1387:30: warning: '%0*d' directive writing between 1 and 2147483647 bytes into a region of size 9999 [-Wformat-overflow=] 1387 | sprintf( pBuffer, "%c%0*d%c", c, d, i, c ); @@ -27723,6 +27759,12 @@ | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 | __va_arg_pack ()); | ~~~~~~~~~~~~~~~~~ +-> ABC: `` Compiling: /src/aig/gia/giaMini.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMini.c -o src/aig/gia/giaMini.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/aig/gia/giaMinLut.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMinLut.c -o src/aig/gia/giaMinLut.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/aig/gia/giaMan.c: In function 'abc::Gia_ManDumpVerilogNand(abc::Gia_Man_t_*, char*)': src/aig/gia/giaMan.c:1387:30: warning: '%0*d' directive writing between 1 and 2147483647 bytes into a region of size 9999 [-Wformat-overflow=] 1387 | sprintf( pBuffer, "%c%0*d%c", c, d, i, c ); @@ -27837,12 +27879,6 @@ | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 | __va_arg_pack ()); | ~~~~~~~~~~~~~~~~~ --> ABC: `` Compiling: /src/aig/gia/giaMini.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMini.c -o src/aig/gia/giaMini.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ --> ABC: `` Compiling: /src/aig/gia/giaMinLut.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMinLut.c -o src/aig/gia/giaMinLut.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/gia/giaMinLut2.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaMinLut2.c -o src/aig/gia/giaMinLut2.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -27867,6 +27903,9 @@ -> ABC: `` Compiling: /src/aig/gia/giaPat2.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaPat2.c -o src/aig/gia/giaPat2.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/aig/gia/giaPf.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaPf.c -o src/aig/gia/giaPf.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from /build/reproducible-path/yosys-0.52/abc/src/sat/bsat/satSolver.h:29, from /build/reproducible-path/yosys-0.52/abc/src/sat/bsat/satStore.h:36, from src/aig/gia/giaOf.c:30: @@ -27877,9 +27916,6 @@ src/aig/gia/giaOf.c:1307:9: note: 'Delays' declared here 1307 | int Delays[6], Perm[6] = {0, 1, 2, 3, 4, 5}; | ^~~~~~ --> ABC: `` Compiling: /src/aig/gia/giaPf.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaPf.c -o src/aig/gia/giaPf.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/gia/giaQbf.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaQbf.c -o src/aig/gia/giaQbf.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -27988,6 +28024,9 @@ -> ABC: `` Compiling: /src/aig/gia/giaSweep.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSweep.c -o src/aig/gia/giaSweep.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/aig/gia/giaSweeper.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSweeper.c -o src/aig/gia/giaSweeper.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In file included from /build/reproducible-path/yosys-0.52/abc/src/misc/vec/vec.h:29, from src/aig/gia/gia.h:34, from src/aig/gia/giaSimBase.c:21: @@ -28011,9 +28050,6 @@ src/aig/gia/giaSimBase.c:3586:10: note: 'Entry' declared here 3586 | word Entry; int i; | ^~~~~ --> ABC: `` Compiling: /src/aig/gia/giaSweeper.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSweeper.c -o src/aig/gia/giaSweeper.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/gia/giaSwitch.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/gia/giaSwitch.c -o src/aig/gia/giaSwitch.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -28080,6 +28116,9 @@ -> ABC: `` Compiling: /src/aig/ivy/ivyFraig.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyFraig.c -o src/aig/ivy/ivyFraig.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/aig/ivy/ivyHaig.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyHaig.c -o src/aig/ivy/ivyHaig.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/aig/ivy/ivyFastMap.c: In function 'abc::Ivy_FastMapNodeArea2(abc::Ivy_Man_t_*, abc::Ivy_Obj_t_*, int)': src/aig/ivy/ivyFastMap.c:400:25: warning: array subscript 0 is outside array bounds of 'int[4294967296]' [-Warray-bounds=] 400 | pSupp0->pArray[0] = Ivy_ObjFaninId0(pObj); @@ -28093,8 +28132,8 @@ src/aig/ivy/ivyFastMap.c:52:17: note: while referencing 'pArray' 52 | int pArray[0]; // the support nodes | ^~~~~~ --> ABC: `` Compiling: /src/aig/ivy/ivyHaig.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyHaig.c -o src/aig/ivy/ivyHaig.o +-> ABC: `` Compiling: /src/aig/ivy/ivyMan.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyMan.c -o src/aig/ivy/ivyMan.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ In function 'abc::Ivy_FastMapNodeArea(abc::Ivy_Man_t_*, abc::Ivy_Obj_t_*, int)', inlined from 'abc::Ivy_FastMapPerform(abc::Ivy_Man_t_*, int, int, int)' at src/aig/ivy/ivyFastMap.c:152:28: @@ -28114,9 +28153,6 @@ src/aig/ivy/ivyFastMap.c:52:17: note: while referencing 'pArray' 52 | int pArray[0]; // the support nodes | ^~~~~~ --> ABC: `` Compiling: /src/aig/ivy/ivyMan.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyMan.c -o src/aig/ivy/ivyMan.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/ivy/ivyMem.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/ivy/ivyMem.c -o src/aig/ivy/ivyMem.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -28166,20 +28202,20 @@ g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/hop/hopObj.c -o src/aig/hop/hopObj.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/hop/hopOper.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/hop/hopOper.c -o src/aig/hop/hopOper.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/hop/hopTable.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/hop/hopOper.c -o src/aig/hop/hopOper.o g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/hop/hopTable.c -o src/aig/hop/hopTable.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/hop/hopTruth.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/hop/hopTruth.c -o src/aig/hop/hopTruth.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/aig/hop/hopUtil.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/aig/hop/hopUtil.c -o src/aig/hop/hopUtil.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bdd/cudd/cuddAPI.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/cudd/cuddAPI.c -o src/bdd/cudd/cuddAPI.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bdd/cudd/cuddAddAbs.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/cudd/cuddAddAbs.c -o src/bdd/cudd/cuddAddAbs.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -28504,6 +28540,9 @@ -> ABC: `` Compiling: /src/bdd/llb/llb2Dump.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/llb/llb2Dump.c -o src/bdd/llb/llb2Dump.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ +-> ABC: `` Compiling: /src/bdd/llb/llb2Flow.c +g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/llb/llb2Flow.c -o src/bdd/llb/llb2Flow.o +cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ src/bdd/llb/llb2Dump.c: In function 'abc::Llb_ManDumpReached(abc::DdManager*, abc::DdNode*, char*, char*)': src/bdd/llb/llb2Dump.c:48:25: warning: '%0*d' directive writing between 1 and 2147483647 bytes into a region of size 1998 [-Wformat-overflow=] 48 | sprintf( Buffer, "%s%0*d", pPrefix, nDigits, Num ); @@ -28526,9 +28565,6 @@ | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 | __va_arg_pack ()); | ~~~~~~~~~~~~~~~~~ --> ABC: `` Compiling: /src/bdd/llb/llb2Flow.c -g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/llb/llb2Flow.c -o src/bdd/llb/llb2Flow.o -cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ -> ABC: `` Compiling: /src/bdd/llb/llb2Image.c g++ -c -g -O -I/build/reproducible-path/yosys-0.52/abc/src -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -D_TIME_BITS=64 -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -Werror=implicit-function-declaration -ffile-prefix-map=/build/reproducible-path/yosys-0.52=. -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare -DABC_USE_STDINT_H -DABC_MEMALIGN=4 -DABC_NAMESPACE=abc -fpermissive -x c++ -DABC_USE_CUDD=1 -DABC_USE_READLINE -DABC_USE_PTHREADS -Wno-unused-but-set-variable src/bdd/llb/llb2Image.c -o src/bdd/llb/llb2Image.o cc1plus: warning: '-Werror=' argument '-Werror=implicit-function-declaration' is not valid for C++ @@ -28867,7 +28903,7 @@ debian/rules override_dh_auto_build-indep make[1]: Entering directory '/build/reproducible-path/yosys-0.52' dh_auto_build -- docs DOC_TARGET=latexpdf - make -j3 "INSTALL=install --strip-program=true" docs DOC_TARGET=latexpdf + make -j4 "INSTALL=install --strip-program=true" docs DOC_TARGET=latexpdf make[2]: Entering directory '/build/reproducible-path/yosys-0.52' [Makefile.conf] CONFIG := gcc [Makefile.conf] STRIP=: @@ -28876,18 +28912,19 @@ mkdir -p docs/source/generated/functional mkdir -p docs/source/generated/functional mkdir -p docs/source/cmd +./yosys -p 'help -dump-cells-json docs/source/generated/cells.json' cp backends/functional/smtlib.cc docs/source/generated/functional/smtlib.cc diff -U 20 backends/functional/smtlib.cc backends/functional/smtlib_rosette.cc > docs/source/generated/functional/rosette.diff || exit 0 mkdir -p temp/docs/source/cmd -./yosys -p 'help -dump-cells-json docs/source/generated/cells.json' -cd temp && ./../yosys -p 'help -write-rst-command-reference-manual' >/dev/null make -C docs gen +cd temp && ./../yosys -p 'help -write-rst-command-reference-manual' >/dev/null make[3]: Entering directory '/build/reproducible-path/yosys-0.52/docs' make examples make[4]: Entering directory '/build/reproducible-path/yosys-0.52/docs' make -C source/code_examples/extensions examples make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/extensions' -../../../../yosys-config --exec --cxx -g -O2 -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I../../../../share/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER= --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs +PYTHONPATH=./share/python3 ./yosys --help > docs/source/generated/yosys || rm docs/source/generated/yosys +../../../../yosys-config --exec --cxx -g -O2 -flto=auto -ffat-lto-objects -fstack-protector-strong -fstack-clash-protection -Wformat -Werror=format-security -Wall -Wextra -ggdb -I../../../../share/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -DYOSYS_VER=@CXXFLAGS@.52 -DYOSYS_MAJOR=0 -DYOSYS_MINOR=52 -DYOSYS_COMMIT=0.52 -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -28898,14 +28935,17 @@ -- Running command `help -dump-cells-json docs/source/generated/cells.json' -- -End of script. Logfile hash: 435b0c1a21, CPU: user 0.02s system 0.01s, MEM: 10.54 MB peak +End of script. Logfile hash: 435b0c1a21, CPU: user 0.02s system 0.01s, MEM: 10.48 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 100% 1x help (0 sec) -PYTHONPATH=./share/python3 ./yosys --help > docs/source/generated/yosys || rm docs/source/generated/yosys PYTHONPATH=./share/python3 ./yosys-smtbmc --help > docs/source/generated/yosys-smtbmc || rm docs/source/generated/yosys-smtbmc +PYTHONPATH=./share/python3 ./yosys-witness --help > docs/source/generated/yosys-witness || rm docs/source/generated/yosys-witness cp -ru temp/docs/source/cmd docs/source rm -rf temp -PYTHONPATH=./share/python3 ./yosys-witness --help > docs/source/generated/yosys-witness || rm docs/source/generated/yosys-witness +PYTHONPATH=./share/python3 ./yosys-config --help > docs/source/generated/yosys-config || rm docs/source/generated/yosys-config +./yosys-filterlib --help 2> docs/source/generated/yosys-filterlib +make[2]: [Makefile:1071: docs/source/generated/yosys-filterlib] Error 1 (ignored) +./yosys-abc --help 2> docs/source/generated/yosys-abc make -C source/code_examples/fifo examples make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/fifo' ../../../../yosys fifo.ys -l fifo.out -Q -T @@ -28974,12 +29014,15 @@ yosys> show -format dot -prefix new_cells_show -notitle @new_cells 5. Generating Graphviz representation of design. +UC Berkeley, ABC 1.01 (compiled Apr 11 2025 08:41:09) Writing dot description to `new_cells_show.dot'. Dumping selected parts of module addr_gen to page 1. yosys> show -color maroon3 @new_cells -color cornflowerblue p:* -notitle -format dot -prefix addr_gen_hier 6. Generating Graphviz representation of design. +make[2]: [Makefile:1071: docs/source/generated/yosys-abc] Error 1 (ignored) +../../../../yosys fifo_map.ys Writing dot description to `addr_gen_hier.dot'. Dumping module addr_gen to page 1. @@ -29055,14 +29098,45 @@ yosys> show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc 8. Generating Graphviz representation of design. +make -C source/code_examples/intro examples Writing dot description to `addr_gen_proc.dot'. Dumping module addr_gen to page 1. yosys> opt_expr 9. Executing OPT_EXPR pass (perform const folding). +make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' +make[5]: Nothing to be done for 'examples'. +make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' +make -C source/code_examples/macc examples + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `fifo_map.ys' -- + +1. Executing Verilog-2005 frontend: fifo.v Optimizing module addr_gen. +make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' +make[5]: Nothing to be done for 'examples'. +make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' +make -C source/code_examples/opt examples +Parsing Verilog input from `fifo.v' to AST representation. +Generating RTLIL representation for module `\addr_gen'. +Generating RTLIL representation for module `\fifo'. +Successfully finished Verilog frontend. +echo on + +yosys> tee -o fifo.stat stat + +yosys> stat + +2. Printing statistics. yosys> clean Removed 0 unused cells and 5 unused wires. @@ -29072,14 +29146,64 @@ yosys> show -color cornflowerblue @new_cells -notitle -format dot -prefix addr_gen_clean 10. Generating Graphviz representation of design. + +=== fifo === + + Number of wires: 28 + Number of wire bits: 219 + Number of public wires: 9 + Number of public wire bits: 45 + Number of ports: 7 + Number of port bits: 29 + Number of memories: 1 + Number of memory bits: 2048 + Number of processes: 3 + Number of cells: 9 + $add 1 + $logic_and 2 + $logic_not 2 + $memrd 1 + $sub 1 + addr_gen 2 + +=== addr_gen === + + Number of wires: 8 + Number of wire bits: 60 + Number of public wires: 4 + Number of public wire bits: 11 + Number of ports: 4 + Number of port bits: 11 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 2 + Number of cells: 2 + $add 1 + $eq 1 + + +yosys> echo off +echo off + +3. Executing SYNTH_ICE40 pass. + +3.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/ice40/cells_sim.v +make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' +make[5]: Nothing to be done for 'examples'. +make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' Writing dot description to `addr_gen_clean.dot'. Dumping module addr_gen to page 1. +make -C source/code_examples/scrambler examples yosys> design -reset yosys> read_verilog fifo.v 11. Executing Verilog-2005 frontend: fifo.v +make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' +make[5]: Nothing to be done for 'examples'. +make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' +make -C source/code_examples/selections examples Parsing Verilog input from `fifo.v' to AST representation. Generating RTLIL representation for module `\addr_gen'. Generating RTLIL representation for module `\fifo'. @@ -29109,6 +29233,8 @@ Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 Removing unused module `\addr_gen'. Removed 1 unused modules. +make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' +../../../../yosys sumprod.ys yosys> proc @@ -29207,171 +29333,6 @@ yosys> opt_expr -keepdc 13.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module fifo. - -Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. - - -yosys> select -set new_cells t:$memrd - -yosys> show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci* - -14. Generating Graphviz representation of design. -Writing dot description to `rdata_proc.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> flatten - -15. Executing FLATTEN pass (flatten design). -Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. - - -yosys> clean -Removed 3 unused cells and 28 unused wires. - -yosys> select -set rdata_path o:rdata %ci* - -yosys> select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path - -16. Generating Graphviz representation of design. -Writing dot description to `rdata_flat.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> opt_dff - -17. Executing OPT_DFF pass (perform DFF optimizations). -PYTHONPATH=./share/python3 ./yosys-config --help > docs/source/generated/yosys-config || rm docs/source/generated/yosys-config -Adding EN signal on $procdff$59 ($adff) from module fifo (D = $0\count[8:0], Q = \count). -Adding EN signal on $flatten\fifo_writer.$procdff$66 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$53_Y, Q = \fifo_writer.addr). -Adding EN signal on $flatten\fifo_reader.$procdff$66 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$53_Y, Q = \fifo_reader.addr). - -yosys> select -set new_cells t:$adffe - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci* - -18. Generating Graphviz representation of design. -Writing dot description to `rdata_adffe.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> wreduce - -19. Executing WREDUCE pass (reducing word size of cells). -Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:66$29 ($add). -Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:66$29 ($add). -Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:68$32 ($sub). -Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:68$32 ($sub). -Removed top 1 bits (of 2) from port B of cell fifo.$auto$opt_dff.cc:195:make_patterns_logic$72 ($ne). -Removed cell fifo.$flatten\fifo_writer.$procmux$55 ($mux). -Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$36 ($add). -Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$36 ($add). -Removed cell fifo.$flatten\fifo_reader.$procmux$55 ($mux). -Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$36 ($add). -Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$36 ($add). -Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:66$29_Y. -Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_reader.$add$fifo.v:19$36_Y. -Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_writer.$add$fifo.v:19$36_Y. - -yosys> show -notitle -format dot -prefix rdata_wreduce o:rdata %ci* - -20. Generating Graphviz representation of design. -Writing dot description to `rdata_wreduce.dot'. -Dumping selected parts of module fifo to page 1. -./yosys-filterlib --help 2> docs/source/generated/yosys-filterlib - -yosys> opt_clean - -21. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \fifo.. -Removed 0 unused cells and 5 unused wires. - - -yosys> memory_dff - -22. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Checking read port `\data'[0] in module `\fifo': merging output FF to cell. - Write port 0: non-transparent. - -yosys> select -set new_cells t:$memrd_v2 - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci* - -23. Generating Graphviz representation of design. -make[2]: [Makefile:1071: docs/source/generated/yosys-filterlib] Error 1 (ignored) -make -C source/code_examples/intro examples -Writing dot description to `rdata_memrdv2.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> alumacc - -24. Executing ALUMACC pass (create $alu and $macc cells). -make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' -Extracting $alu and $macc cells in module fifo: - creating $macc model for $add$fifo.v:66$29 ($add). - creating $macc model for $flatten\fifo_reader.$add$fifo.v:19$36 ($add). - creating $macc model for $flatten\fifo_writer.$add$fifo.v:19$36 ($add). - creating $macc model for $sub$fifo.v:68$32 ($sub). - creating $alu model for $macc $sub$fifo.v:68$32. - creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:19$36. - creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:19$36. - creating $alu model for $macc $add$fifo.v:66$29. - creating $alu cell for $add$fifo.v:66$29: $auto$alumacc.cc:495:replace_alu$87 - creating $alu cell for $flatten\fifo_reader.$add$fifo.v:19$36: $auto$alumacc.cc:495:replace_alu$90 - creating $alu cell for $flatten\fifo_writer.$add$fifo.v:19$36: $auto$alumacc.cc:495:replace_alu$93 - creating $alu cell for $sub$fifo.v:68$32: $auto$alumacc.cc:495:replace_alu$96 - created 4 $alu and 0 $macc cells. - -yosys> select -set new_cells t:$alu t:$macc_v2 - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci* - -25. Generating Graphviz representation of design. -make[5]: Nothing to be done for 'examples'. -make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' -make -C source/code_examples/macc examples -Writing dot description to `rdata_alumacc.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> memory_collect - -26. Executing MEMORY_COLLECT pass (generating $mem cells). -make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' -make[5]: Nothing to be done for 'examples'. -make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' -make -C source/code_examples/opt examples - -yosys> select -set new_cells t:$mem_v2 - -yosys> select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %% - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path - -27. Generating Graphviz representation of design. -make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' -make[5]: Nothing to be done for 'examples'. -make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' -make -C source/code_examples/scrambler examples -Writing dot description to `rdata_coarse.dot'. -Dumping selected parts of module fifo to page 1. -make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' -make[5]: Nothing to be done for 'examples'. -make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' -../../../../yosys fifo_map.ys -make -C source/code_examples/selections examples -make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' -../../../../yosys sumprod.ys - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `fifo_map.ys' -- - -1. Executing Verilog-2005 frontend: fifo.v /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -29383,6 +29344,10 @@ -- Executing script file `sumprod.ys' -- 1. Executing Verilog-2005 frontend: sumprod.v +Optimizing module fifo. + +Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. + Parsing Verilog input from `sumprod.v' to AST representation. Generating RTLIL representation for module `\sumprod'. Successfully finished Verilog frontend. @@ -29404,6 +29369,12 @@ Cleaned up 0 empty switches. 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). + +yosys> select -set new_cells t:$memrd + +yosys> show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci* + +14. Generating Graphviz representation of design. Removed a total of 0 dead cases. 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). @@ -29420,72 +29391,26 @@ 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). -Parsing Verilog input from `fifo.v' to AST representation. -Generating RTLIL representation for module `\addr_gen'. -Generating RTLIL representation for module `\fifo'. -Successfully finished Verilog frontend. -echo on - -yosys> tee -o fifo.stat stat - -yosys> stat - -2. Printing statistics. 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -=== fifo === - - Number of wires: 28 - Number of wire bits: 219 - Number of public wires: 9 - Number of public wire bits: 45 - Number of ports: 7 - Number of port bits: 29 - Number of memories: 1 - Number of memory bits: 2048 - Number of processes: 3 - Number of cells: 9 - $add 1 - $logic_and 2 - $logic_not 2 - $memrd 1 - $sub 1 - addr_gen 2 - -=== addr_gen === - - Number of wires: 8 - Number of wire bits: 60 - Number of public wires: 4 - Number of public wire bits: 11 - Number of ports: 4 - Number of port bits: 11 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 2 - Number of cells: 2 - $add 1 - $eq 1 - - -yosys> echo off -echo off - -3. Executing SYNTH_ICE40 pass. - -3.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/ice40/cells_sim.v - 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2.12. Executing OPT_EXPR pass (perform const folding). +Writing dot description to `rdata_proc.dot'. +Dumping selected parts of module fifo to page 1. Optimizing module sumprod. 2.3. Executing FUTURE pass. +yosys> flatten + +15. Executing FLATTEN pass (flatten design). +Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. + 2.4. Executing OPT_EXPR pass (perform const folding). Optimizing module sumprod. @@ -29504,6 +29429,18 @@ Optimizing module sumprod. 2.7.2. Executing OPT_MERGE pass (detect identical cells). + + +yosys> clean +Removed 3 unused cells and 28 unused wires. + +yosys> select -set rdata_path o:rdata %ci* + +yosys> select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path + +16. Generating Graphviz representation of design. Finding identical cells in module `\sumprod'. Removed a total of 0 cells. @@ -29518,10 +29455,16 @@ Performed a total of 0 changes. 2.7.5. Executing OPT_MERGE pass (detect identical cells). +Writing dot description to `rdata_flat.dot'. +Dumping selected parts of module fifo to page 1. Finding identical cells in module `\sumprod'. Removed a total of 0 cells. 2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). + +yosys> opt_dff + +17. Executing OPT_DFF pass (perform DFF optimizations). Finding unused cells or wires in module \sumprod.. 2.7.7. Executing OPT_EXPR pass (perform const folding). @@ -29530,6 +29473,15 @@ 2.7.8. Finished OPT passes. (There is nothing left to do.) 2.8. Executing WREDUCE pass (reducing word size of cells). +Adding EN signal on $procdff$59 ($adff) from module fifo (D = $0\count[8:0], Q = \count). +Adding EN signal on $flatten\fifo_writer.$procdff$66 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$53_Y, Q = \fifo_writer.addr). +Adding EN signal on $flatten\fifo_reader.$procdff$66 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$53_Y, Q = \fifo_reader.addr). + +yosys> select -set new_cells t:$adffe + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci* + +18. Generating Graphviz representation of design. 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \sumprod.. @@ -29539,13 +29491,37 @@ 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). +Writing dot description to `rdata_adffe.dot'. +Dumping selected parts of module fifo to page 1. Optimizing module sumprod. 2.11.2. Executing OPT_MERGE pass (detect identical cells). + +yosys> wreduce + +19. Executing WREDUCE pass (reducing word size of cells). Finding identical cells in module `\sumprod'. Removed a total of 0 cells. 2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:66$29 ($add). +Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:66$29 ($add). +Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:68$32 ($sub). +Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:68$32 ($sub). +Removed top 1 bits (of 2) from port B of cell fifo.$auto$opt_dff.cc:195:make_patterns_logic$72 ($ne). +Removed cell fifo.$flatten\fifo_writer.$procmux$55 ($mux). +Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$36 ($add). +Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$36 ($add). +Removed cell fifo.$flatten\fifo_reader.$procmux$55 ($mux). +Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$36 ($add). +Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$36 ($add). +Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:66$29_Y. +Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_reader.$add$fifo.v:19$36_Y. +Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_writer.$add$fifo.v:19$36_Y. + +yosys> show -notitle -format dot -prefix rdata_wreduce o:rdata %ci* + +20. Generating Graphviz representation of design. Finding unused cells or wires in module \sumprod.. 2.11.4. Finished fast OPT passes. @@ -29572,10 +29548,16 @@ Found and reported 0 problems. 3. Generating Graphviz representation of design. +Writing dot description to `rdata_wreduce.dot'. +Dumping selected parts of module fifo to page 1. Writing dot description to `sumprod_00.dot'. Dumping selected parts of module sumprod to page 1. 4. Generating Graphviz representation of design. + +yosys> opt_clean + +21. Executing OPT_CLEAN pass (remove unused cells and wires). Writing dot description to `sumprod_01.dot'. Dumping selected parts of module sumprod to page 1. @@ -29584,25 +29566,83 @@ Dumping selected parts of module sumprod to page 1. 6. Generating Graphviz representation of design. +Finding unused cells or wires in module \fifo.. +Removed 0 unused cells and 5 unused wires. Writing dot description to `sumprod_03.dot'. Dumping selected parts of module sumprod to page 1. 7. Generating Graphviz representation of design. + + +yosys> memory_dff + +22. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Writing dot description to `sumprod_04.dot'. Dumping selected parts of module sumprod to page 1. 8. Generating Graphviz representation of design. Writing dot description to `sumprod_05.dot'. Dumping selected parts of module sumprod to page 1. +Checking read port `\data'[0] in module `\fifo': merging output FF to cell. + Write port 0: non-transparent. + +yosys> select -set new_cells t:$memrd_v2 + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci* + +23. Generating Graphviz representation of design. -End of script. Logfile hash: ad287e9838, CPU: user 0.06s system 0.01s, MEM: 8.59 MB peak +End of script. Logfile hash: ad287e9838, CPU: user 0.06s system 0.00s, MEM: 8.59 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 27% 6x show (0 sec), 24% 5x opt_expr (0 sec), ... +Time spent: 26% 6x show (0 sec), 23% 5x opt_expr (0 sec), ... +Writing dot description to `rdata_memrdv2.dot'. +Dumping selected parts of module fifo to page 1. + +yosys> alumacc + +24. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module fifo: + creating $macc model for $add$fifo.v:66$29 ($add). + creating $macc model for $flatten\fifo_reader.$add$fifo.v:19$36 ($add). + creating $macc model for $flatten\fifo_writer.$add$fifo.v:19$36 ($add). + creating $macc model for $sub$fifo.v:68$32 ($sub). + creating $alu model for $macc $sub$fifo.v:68$32. + creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:19$36. + creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:19$36. + creating $alu model for $macc $add$fifo.v:66$29. + creating $alu cell for $add$fifo.v:66$29: $auto$alumacc.cc:495:replace_alu$87 + creating $alu cell for $flatten\fifo_reader.$add$fifo.v:19$36: $auto$alumacc.cc:495:replace_alu$90 + creating $alu cell for $flatten\fifo_writer.$add$fifo.v:19$36: $auto$alumacc.cc:495:replace_alu$93 + creating $alu cell for $sub$fifo.v:68$32: $auto$alumacc.cc:495:replace_alu$96 + created 4 $alu and 0 $macc cells. + +yosys> select -set new_cells t:$alu t:$macc_v2 + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci* + +25. Generating Graphviz representation of design. make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' make -C source/code_examples/show examples +Writing dot description to `rdata_alumacc.dot'. +Dumping selected parts of module fifo to page 1. + +yosys> memory_collect + +26. Executing MEMORY_COLLECT pass (generating $mem cells). make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/show' ../../../../yosys example_lscd.ys -l example.out -Q -T +yosys> select -set new_cells t:$mem_v2 + +yosys> select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %% + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path + +27. Generating Graphviz representation of design. +Writing dot description to `rdata_coarse.dot'. +Dumping selected parts of module fifo to page 1. +make -C source/code_examples/stubnets examples + -- Executing script file `example_lscd.ys' -- 1. Executing Verilog-2005 frontend: example.v @@ -29656,20 +29696,18 @@ yosys> echo off echo off -make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/show' -make -C source/code_examples/stubnets examples make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/stubnets' make[5]: Nothing to be done for 'examples'. make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/stubnets' make -C source/code_examples/synth_flow examples +make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/show' +make -C source/code_examples/techmap examples make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' make[5]: Nothing to be done for 'examples'. make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' -make -C source/code_examples/techmap examples make[5]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/techmap' make[5]: Nothing to be done for 'examples'. make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/techmap' -./yosys-abc --help 2> docs/source/generated/yosys-abc Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. @@ -29912,8 +29950,6 @@ 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). -UC Berkeley, ABC 1.01 (compiled Apr 11 2025 08:41:09) -make[2]: [Makefile:1071: docs/source/generated/yosys-abc] Error 1 (ignored) Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/build/reproducible-path/yosys-0.52/share/ice40/cells_sim.v:1414$262'. created $adff cell `$procdff$471' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/build/reproducible-path/yosys-0.52/share/ice40/cells_sim.v:1353$255'. @@ -31273,9 +31309,9 @@ yosys> echo off echo off -End of script. Logfile hash: 6869f329aa, CPU: user 5.68s system 0.02s, MEM: 22.66 MB peak +End of script. Logfile hash: 6869f329aa, CPU: user 5.40s system 0.04s, MEM: 22.66 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 37% 21x read_verilog (2 sec), 35% 11x techmap (1 sec), ... +Time spent: 38% 21x read_verilog (2 sec), 35% 11x techmap (1 sec), ... make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/fifo' ../../../../yosys -QTl test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' -f verilog absval_ref.v ../../../../yosys -QTl test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' -f verilog absval_ref.v @@ -31299,17 +31335,6 @@ -- Running command `hierarchy -top test; test2' -- 2. Executing HIERARCHY pass (managing design hierarchy). -Parsing Verilog input from `absval_ref.v' to AST representation. -Generating RTLIL representation for module `\absval_ref'. -Successfully finished Verilog frontend. - --- Running command `my_cmd foo bar' -- -Arguments to my_cmd: - my_cmd - foo - bar -Modules in current design: - absval_ref (4 wires, 2 cells) 2.1. Analyzing design hierarchy.. Top module: \test @@ -31332,6 +31357,18 @@ Log message #7. Log message #8. Log message #9. +Parsing Verilog input from `absval_ref.v' to AST representation. +Generating RTLIL representation for module `\absval_ref'. +Successfully finished Verilog frontend. + +-- Running command `my_cmd foo bar' -- +Arguments to my_cmd: + my_cmd + foo + bar +Modules in current design: + absval_ref (4 wires, 2 cells) +mv test0.log_new test0.log mv test2.log_new test2.log Parsing Verilog input from `absval_ref.v' to AST representation. Generating RTLIL representation for module `\absval_ref'. @@ -31399,7 +31436,6 @@ connect \Y \y end end -mv test0.log_new test0.log mv test1.log_new test1.log make[5]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/extensions' make[4]: Leaving directory '/build/reproducible-path/yosys-0.52/docs' @@ -31411,9 +31447,11 @@ ../../../../yosys -m ./my_cmd.so -p 'test1; show -format dot -prefix test1' make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/fifo' make[6]: Nothing to be done for 'dots'. -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/fifo' make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' ../../../../yosys counter.ys +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/fifo' +make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' +../../../../yosys macc_simple_test.ys /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -31440,7 +31478,7 @@ 1. Executing Verilog-2005 frontend: counter.v -End of script. Logfile hash: 2e5f50e91f, CPU: user 0.01s system 0.01s, MEM: 6.25 MB peak +End of script. Logfile hash: 2e5f50e91f, CPU: user 0.01s system 0.00s, MEM: 6.24 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 94% 1x show (0 sec), 5% 1x test1 (0 sec) Parsing Verilog input from `counter.v' to AST representation. @@ -31457,6 +31495,17 @@ Removed 0 unused modules. 3. Generating Graphviz representation of design. + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `macc_simple_test.ys' -- + +1. Executing Verilog-2005 frontend: macc_simple_test.v make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/extensions' Writing dot description to `counter_00.dot'. Dumping module counter to page 1. @@ -31467,16 +31516,28 @@ Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Parsing Verilog input from `macc_simple_test.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. Marked 1 switch rules as full_case in process $proc$counter.v:6$1 in module counter. Removed a total of 0 dead cases. 4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Top module: \test + +2.2. Analyzing design hierarchy.. Removed 0 redundant assignments. Promoted 0 assignments to connections. 4.4. Executing PROC_INIT pass (extract init attributes). 4.5. Executing PROC_ARST pass (detect async resets in processes). +Top module: \test +Removed 0 unused modules. 4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. @@ -31505,127 +31566,10 @@ 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. - -5.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. - -5.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -5.6. Executing OPT_DFF pass (perform DFF optimizations). -Adding SRST signal on $procdff$8 ($dff) from module counter (D = $procmux$3_Y, Q = \count, rval = 2'00). -Adding EN signal on $auto$ff.cc:266:slice$9 ($sdff) from module counter (D = $add$counter.v:10$2_Y, Q = \count). - -5.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \counter.. -Removed 2 unused cells and 5 unused wires. - - -5.8. Executing OPT_EXPR pass (perform const folding). -make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' -../../../../yosys macc_simple_test.ys -Optimizing module counter. - -5.9. Rerunning OPT passes. (Maybe there is more to do..) - -5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. - -5.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -5.13. Executing OPT_DFF pass (perform DFF optimizations). - -5.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \counter.. - -5.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. - -5.16. Finished OPT passes. (There is nothing left to do.) - -6. Executing MEMORY pass. - -6.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. - -6.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `macc_simple_test.ys' -- - -1. Executing Verilog-2005 frontend: macc_simple_test.v -Performed a total of 0 transformations. - -6.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). - -6.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). - -6.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Parsing Verilog input from `macc_simple_test.v' to AST representation. -Generating RTLIL representation for module `\test'. -Successfully finished Verilog frontend. - -2. Executing HIERARCHY pass (managing design hierarchy). - -2.1. Analyzing design hierarchy.. -Top module: \test - -2.2. Analyzing design hierarchy.. -Top module: \test -Removed 0 unused modules. - -6.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \counter.. - -6.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). - -6.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). -Performed a total of 0 transformations. - -6.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \counter.. Removed 0 unused cells and 1 unused wires. 3. Generating Graphviz representation of design. -6.10. Executing MEMORY_COLLECT pass (generating $mem cells). - -6.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). - -7. Executing OPT pass (performing simple optimizations). - -7.1. Executing OPT_EXPR pass (perform const folding). - 3.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. @@ -31633,28 +31577,14 @@ 3.2. Continuing show pass. Optimizing module counter. - -7.2. Executing OPT_MERGE pass (detect identical cells). Writing dot description to `macc_simple_test_00a.dot'. Dumping module test to page 1. -4. Executing EXTRACT pass (map subcircuits to cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. +5.2. Executing OPT_MERGE pass (detect identical cells). -7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +4. Executing EXTRACT pass (map subcircuits to cells). 4.1. Executing Verilog-2005 frontend: macc_simple_xmap.v - Optimizing cells in module \counter. -Performed a total of 0 changes. - -7.5. Executing OPT_MERGE pass (detect identical cells). Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. @@ -31684,9 +31614,21 @@ Finding identical cells in module `\counter'. Removed a total of 0 cells. -7.6. Executing OPT_DFF pass (perform DFF optimizations). +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 4.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). 4.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). @@ -31694,32 +31636,29 @@ Cleaned up 0 empty switches. 4.2.12. Executing OPT_EXPR pass (perform const folding). +Finding identical cells in module `\counter'. +Removed a total of 0 cells. -7.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \counter.. - -7.8. Executing OPT_EXPR pass (perform const folding). +5.6. Executing OPT_DFF pass (perform DFF optimizations). Optimizing module macc_16_16_32. 4.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module counter. - -7.9. Finished OPT passes. (There is nothing left to do.) - -8. Executing FSM pass (extract and optimize FSM). +Adding SRST signal on $procdff$8 ($dff) from module counter (D = $procmux$3_Y, Q = \count, rval = 2'00). +Adding EN signal on $auto$ff.cc:266:slice$9 ($sdff) from module counter (D = $add$counter.v:10$2_Y, Q = \count). -8.1. Executing FSM_DETECT pass (finding FSMs in design). +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. +Finding unused cells or wires in module \counter.. +Removed 2 unused cells and 5 unused wires. 4.4. Creating graphs for SubCircuit library. + -8.2. Executing FSM_EXTRACT pass (extracting FSM from design). - -8.3. Executing FSM_OPT pass (simple optimizations of FSMs). - -8.4. Executing OPT_CLEAN pass (remove unused cells and wires). +5.8. Executing OPT_EXPR pass (perform const folding). +make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' +../../../../yosys opt_share.ys Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. @@ -31728,15 +31667,6 @@ Found 1 matches. 4.6. Substitute SubCircuits with cells. -Finding unused cells or wires in module \counter.. - -8.5. Executing FSM_OPT pass (simple optimizations of FSMs). - -8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). - -8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). - -8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$7 -> $add$macc_simple_test.v:5$2 \A:\A \B:\B \Y:\Y @@ -31746,13 +31676,27 @@ $const$z -> $const$z \Y:\Y $mul$macc_simple_xmap.v:5$6 -> $mul$macc_simple_test.v:5$1 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$8 +Optimizing module counter. -9. Executing OPT pass (performing simple optimizations). +5.9. Rerunning OPT passes. (Maybe there is more to do..) -9.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. -9.2. Executing OPT_MERGE pass (detect identical cells). +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. +Performed a total of 0 changes. + +5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +5.13. Executing OPT_DFF pass (perform DFF optimizations). + +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Removed 0 unused cells and 1 unused wires. 5. Generating Graphviz representation of design. @@ -31763,26 +31707,11 @@ Successfully finished Verilog frontend. 5.2. Continuing show pass. -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. +Finding unused cells or wires in module \counter.. -9.5. Executing OPT_MERGE pass (detect identical cells). +5.15. Executing OPT_EXPR pass (perform const folding). Writing dot description to `macc_simple_test_00b.dot'. Dumping module test to page 1. -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -9.6. Executing OPT_DFF pass (perform DFF optimizations). 6. Executing Verilog-2005 frontend: macc_simple_test_01.v Parsing Verilog input from `macc_simple_test_01.v' to AST representation. @@ -31791,44 +31720,66 @@ 7. Executing HIERARCHY pass (managing design hierarchy). -9.7. Executing OPT_CLEAN pass (remove unused cells and wires). - 7.1. Analyzing design hierarchy.. Top module: \test 7.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. -Finding unused cells or wires in module \counter.. +Optimizing module counter. -9.8. Executing OPT_EXPR pass (perform const folding). -make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' +5.16. Finished OPT passes. (There is nothing left to do.) + +6. Executing MEMORY pass. + +6.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +6.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `opt_share.ys' -- + +1. Executing Verilog-2005 frontend: < 9.4. Creating graphs for SubCircuit library. +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. +Performed a total of 0 changes. + +7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +7.6. Executing OPT_DFF pass (perform DFF optimizations). Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. @@ -31883,26 +31882,15 @@ 9.6. Substitute SubCircuits with cells. +7.7. Executing OPT_CLEAN pass (remove unused cells and wires). + Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$18 -> $add$macc_simple_test_01.v:5$13 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$17 -> $mul$macc_simple_test_01.v:5$11 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$19 +Finding unused cells or wires in module \counter.. - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `opt_share.ys' -- - -1. Executing Verilog-2005 frontend: < | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `opt_muxtree.ys' -- + +1. Executing Verilog-2005 frontend: < 14.4. Creating graphs for SubCircuit library. -Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu_brent_kung'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod_trunc'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\$__div_mod_floor'. -Generating RTLIL representation for module `\_90_divfloor'. -Generating RTLIL representation for module `\_90_modfloor'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_demux'. -Generating RTLIL representation for module `\_90_lut'. +Parsing Verilog input from `< +Removed 0 unused cells and 3 unused wires. + +3. Generating Graphviz representation of design. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$24 \A:\A \B:\B \Y:\Y @@ -32057,7 +32086,13 @@ $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$25 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$22 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$31 -../../../../yosys opt_muxtree.ys +Writing dot description to `opt_muxtree_full.dot'. +Dumping module after to page 1. +Dumping module uut to page 2. + +End of script. Logfile hash: b6e098eb19, CPU: user 0.02s system 0.00s, MEM: 8.40 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 53% 1x clean (0 sec), 29% 1x show (0 sec), ... Removed 0 unused cells and 2 unused wires. 15. Generating Graphviz representation of design. @@ -32068,6 +32103,7 @@ Successfully finished Verilog frontend. 15.2. Continuing show pass. +gvpack -u -o opt_muxtree.dot opt_muxtree_full.dot Writing dot description to `macc_simple_test_02b.dot'. Dumping module test to page 1. @@ -32089,119 +32125,16 @@ 18. Generating Graphviz representation of design. Writing dot description to `macc_simple_xmap.dot'. Dumping module macc_16_16_32 to page 1. - -End of script. Logfile hash: a39cb7f441, CPU: user 0.09s system 0.01s, MEM: 8.07 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 31% 7x clean (0 sec), 16% 7x show (0 sec), ... - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `opt_muxtree.ys' -- - -1. Executing Verilog-2005 frontend: < -Removed 0 unused cells and 3 unused wires. - -3. Generating Graphviz representation of design. -Writing dot description to `opt_muxtree_full.dot'. -Dumping module after to page 1. -Dumping module uut to page 2. - -End of script. Logfile hash: b6e098eb19, CPU: user 0.01s system 0.01s, MEM: 8.41 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 52% 1x clean (0 sec), 29% 1x show (0 sec), ... -gvpack -u -o opt_muxtree.dot opt_muxtree_full.dot -Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. -Using extmapper simplemap for cells of type $pos. -Using extmapper simplemap for cells of type $mux. -Using extmapper simplemap for cells of type $not. -Using extmapper simplemap for cells of type $or. -No more expansions possible. - - -12. Executing OPT pass (performing simple optimizations). - -12.1. Executing OPT_EXPR pass (perform const folding). - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `macc_xilinx_test.ys' -- - -1. Executing Verilog-2005 frontend: macc_xilinx_test.v -Parsing Verilog input from `macc_xilinx_test.v' to AST representation. -Generating RTLIL representation for module `\test1'. -Generating RTLIL representation for module `\test2'. -Successfully finished Verilog frontend. - -2. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v Warning: node n2 in graph[1] uut already defined Some nodes will be renamed. -Optimizing module counter. - - -12.2. Executing OPT_MERGE pass (detect identical cells). -Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. -Generating RTLIL representation for module `$__mul_wrapper'. -Generating RTLIL representation for module `$__add_wrapper'. -Successfully finished Verilog frontend. -3. Executing Verilog-2005 frontend: macc_xilinx_xmap.v +End of script. Logfile hash: a39cb7f441, CPU: user 0.10s system 0.01s, MEM: 8.06 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 32% 7x clean (0 sec), 16% 7x show (0 sec), ... ../../../../yosys opt_merge.ys -Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. -Generating RTLIL representation for module `\DSP48_MACC'. -Successfully finished Verilog frontend. - -4. Executing HIERARCHY pass (managing design hierarchy). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. - -12.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -12.6. Executing OPT_DFF pass (perform DFF optimizations). - -12.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \counter.. -Removed 1 unused cells and 32 unused wires. - - -12.8. Executing OPT_EXPR pass (perform const folding). -Removed 0 unused cells and 2 unused wires. - -5. Generating Graphviz representation of design. +make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' +../../../../yosys scrambler.ys +../../../../yosys macc_xilinx_test.ys /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -32213,136 +32146,6 @@ -- Executing script file `opt_merge.ys' -- 1. Executing Verilog-2005 frontend: < -Removed a total of 1 cells. -Removed 0 unused cells and 4 unused wires. - -3. Generating Graphviz representation of design. -Writing dot description to `opt_merge_full.dot'. -Dumping module after to page 1. -Dumping module uut to page 2. -Using template $paramod$cb31b7e2c27e209b1e5fc8ca3c6ec22d65eb4c07\mul_swap_ports for cells of type $mul. - -End of script. Logfile hash: dedbdef5c2, CPU: user 0.02s system 0.00s, MEM: 8.47 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 43% 1x clean (0 sec), 24% 1x show (0 sec), ... -Optimizing module counter. - -12.16. Finished OPT passes. (There is nothing left to do.) - -13. Executing SPLITNETS pass (splitting up multi-bit signals). -No more expansions possible. -gvpack -u -o opt_merge.dot opt_merge_full.dot -Removed 0 unused cells and 2 unused wires. - -14. Generating Graphviz representation of design. -Writing dot description to `counter_02.dot'. -Dumping module counter to page 1. - -15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). - cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. - final dff cell mappings: - unmapped dff cell: $_DFF_N_ - \DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); - unmapped dff cell: $_DFF_NN0_ - unmapped dff cell: $_DFF_NN1_ - unmapped dff cell: $_DFF_NP0_ - unmapped dff cell: $_DFF_NP1_ - unmapped dff cell: $_DFF_PN0_ - unmapped dff cell: $_DFF_PN1_ - unmapped dff cell: $_DFF_PP0_ - unmapped dff cell: $_DFF_PP1_ - unmapped dff cell: $_DFFE_NN_ - unmapped dff cell: $_DFFE_NP_ - unmapped dff cell: $_DFFE_PN_ - unmapped dff cell: $_DFFE_PP_ - unmapped dff cell: $_DFFSR_NNN_ - unmapped dff cell: $_DFFSR_NNP_ - unmapped dff cell: $_DFFSR_NPN_ - unmapped dff cell: $_DFFSR_NPP_ - unmapped dff cell: $_DFFSR_PNN_ - unmapped dff cell: $_DFFSR_PNP_ - unmapped dff cell: $_DFFSR_PPN_ - unmapped dff cell: $_DFFSR_PPP_ - -15.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). -Mapping DFF cells in module `\counter': - mapped 2 $_DFF_P_ cells to \DFF cells. - -16. Executing ABC pass (technology mapping using ABC). - -16.1. Extracting gate netlist of module `\counter' to `/input.blif'.. -Extracted 6 gates and 11 wires to a netlist network with 4 inputs and 2 outputs. - -16.1.1. Executing ABC. -Warning: node n1 in graph[1] uut already defined -Some nodes will be renamed. -../../../../yosys opt_expr.ys - -Removed 0 unused cells and 8 unused wires. - -8. Generating Graphviz representation of design. -Writing dot description to `macc_xilinx_test1b.dot'. -Dumping module test1 to page 1. - -9. Generating Graphviz representation of design. -Writing dot description to `macc_xilinx_test2b.dot'. -Dumping module test2 to page 1. - -10. Executing TECHMAP pass (map to technology primitives). - -10.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v -Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. -Generating RTLIL representation for module `\mul_wrap'. -Generating RTLIL representation for module `\add_wrap'. -Successfully finished Verilog frontend. - -10.2. Continuing TECHMAP pass. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -32351,85 +32154,14 @@ \----------------------------------------------------------------------------/ Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) --- Executing script file `opt_expr.ys' -- +-- Executing script file `scrambler.ys' -- -1. Executing Verilog-2005 frontend: < -Removed 0 unused cells and 4 unused wires. - -3. Generating Graphviz representation of design. -Writing dot description to `opt_expr_full.dot'. -Dumping module after to page 1. -Dumping module uut to page 2. - -End of script. Logfile hash: 1d1df32b64, CPU: user 0.01s system 0.01s, MEM: 8.06 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 45% 1x opt_expr (0 sec), 29% 1x clean (0 sec), ... -gvpack -u -o opt_expr.dot opt_expr_full.dot -Warning: node n1 in graph[1] uut already defined -Some nodes will be renamed. -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' -Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\mul_wrap for cells of type $mul. -Using template $paramod$48197a291a9e3825142389e9d2e41385cae2467c\mul_wrap for cells of type $mul. -Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\add_wrap for cells of type $add. -No more expansions possible. - - -11. Executing CONNWRAPPERS pass (connect extended ports of wrapper cells). -make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' -../../../../yosys scrambler.ys -Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:A: { 6'000000 $add$macc_xilinx_test.v:5$3_Y } -> { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } -Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:B: { 6'000000 $mul$macc_xilinx_test.v:5$4_Y } -> { $techmap25$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y } -Connected extended bits of test1.$add$macc_xilinx_test.v:5$3:B: { 6'000000 $mul$macc_xilinx_test.v:5$2_Y } -> { $techmap23$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y } -Connected extended bits of test2.$add$macc_xilinx_test.v:12$10:B: { 6'000000 $add$macc_xilinx_test.v:12$9_Y } -> { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } -Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:A: { 6'000000 $mul$macc_xilinx_test.v:12$7_Y } -> { $techmap19$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y } -Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:B: { 6'000000 $mul$macc_xilinx_test.v:12$8_Y } -> { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } -Removed 0 unused cells and 56 unused wires. - -12. Generating Graphviz representation of design. -Writing dot description to `macc_xilinx_test1c.dot'. -Dumping module test1 to page 1. - -13. Generating Graphviz representation of design. -Writing dot description to `macc_xilinx_test2c.dot'. -Dumping module test2 to page 1. - -14. Executing Verilog-2005 frontend: macc_xilinx_xmap.v -Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. -Generating RTLIL representation for module `\DSP48_MACC'. -Successfully finished Verilog frontend. - -15. Executing TECHMAP pass (map to technology primitives). - -15.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v -Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. -Generating RTLIL representation for module `\mul_swap_ports'. -Successfully finished Verilog frontend. - -15.2. Continuing TECHMAP pass. - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `scrambler.ys' -- - -1. Executing Verilog-2005 frontend: scrambler.v -No more expansions possible. - - -16. Executing TECHMAP pass (map to technology primitives). - -16.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v +2. Executing OPT_MERGE pass (detect identical cells). Parsing Verilog input from `scrambler.v' to AST representation. Generating RTLIL representation for module `\scrambler'. Successfully finished Verilog frontend. @@ -32462,20 +32194,37 @@ 1/1: $1\xs[31:0] 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). -Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. -Generating RTLIL representation for module `\mul_wrap'. -Generating RTLIL representation for module `\add_wrap'. -Successfully finished Verilog frontend. -16.2. Continuing TECHMAP pass. + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `macc_xilinx_test.ys' -- + +1. Executing Verilog-2005 frontend: macc_xilinx_test.v 3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Finding identical cells in module `\after'. + +Removed a total of 1 cells. +Removed 0 unused cells and 4 unused wires. + +3. Generating Graphviz representation of design. Creating register for signal `\scrambler.\out_bit' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$12' with positive edge clock. Creating register for signal `\scrambler.\xs' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$13' with positive edge clock. 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +Parsing Verilog input from `macc_xilinx_test.v' to AST representation. +Generating RTLIL representation for module `\test1'. +Generating RTLIL representation for module `\test2'. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\scrambler.$proc$scrambler.v:6$1'. @@ -32483,19 +32232,108 @@ Cleaned up 1 empty switch. 3.12. Executing OPT_EXPR pass (perform const folding). +Writing dot description to `opt_merge_full.dot'. +Dumping module after to page 1. +Dumping module uut to page 2. +Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +11.2. Continuing TECHMAP pass. + +End of script. Logfile hash: dedbdef5c2, CPU: user 0.02s system 0.00s, MEM: 8.46 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 44% 1x clean (0 sec), 22% 1x show (0 sec), ... +Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +Using extmapper simplemap for cells of type $sdffe. +Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. +Generating RTLIL representation for module `$__mul_wrapper'. +Generating RTLIL representation for module `$__add_wrapper'. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: macc_xilinx_xmap.v +Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. +Generating RTLIL representation for module `\DSP48_MACC'. +Successfully finished Verilog frontend. + +4. Executing HIERARCHY pass (managing design hierarchy). +gvpack -u -o opt_merge.dot opt_merge_full.dot +Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $and. Optimizing module scrambler. -Using template $paramod$81421da67e3cf07e7ac8b39f28efc75ee750e82a\mul_wrap for cells of type $mul. +Warning: node n1 in graph[1] uut already defined +Some nodes will be renamed. Removed 0 unused cells and 5 unused wires. 4. Executing SUBMOD pass (moving cells to submodules as requested). +Removed 0 unused cells and 2 unused wires. + +5. Generating Graphviz representation of design. +../../../../yosys opt_expr.ys +Writing dot description to `macc_xilinx_test1a.dot'. +Dumping module test1 to page 1. + +6. Generating Graphviz representation of design. +Writing dot description to `macc_xilinx_test2a.dot'. +Dumping module test2 to page 1. + +7. Executing TECHMAP pass (map to technology primitives). + +7.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v +Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. +Generating RTLIL representation for module `\mul_swap_ports'. +Successfully finished Verilog frontend. + +7.2. Continuing TECHMAP pass. +Using template $paramod$cb31b7e2c27e209b1e5fc8ca3c6ec22d65eb4c07\mul_swap_ports for cells of type $mul. 4.1. Executing OPT_CLEAN pass (remove unused cells and wires). -Using template $paramod$88aad6f8473fb7e4e5fbfb8335ddebad03429eaa\add_wrap for cells of type $add. No more expansions possible. + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `opt_expr.ys' -- + +1. Executing Verilog-2005 frontend: < -Removed 0 unused cells and 17 unused wires. - -17. Executing EXTRACT pass (map subcircuits to cells). - -17.1. Creating graphs for SubCircuit library. Writing dot description to `scrambler_p01.dot'. Dumping module scrambler to page 1. +Optimizing module after. + 6. Generating Graphviz representation of design. + +Removed 0 unused cells and 8 unused wires. + +8. Generating Graphviz representation of design. Writing dot description to `scrambler_p02.dot'. Dumping module xorshift32 to page 1. echo on @@ -32533,32 +32371,72 @@ yosys [xorshift32]> eval -set in 1 -show out 7. Executing EVAL pass (evaluate the circuit given an input). +Removed 0 unused cells and 4 unused wires. + +3. Generating Graphviz representation of design. +Writing dot description to `macc_xilinx_test1b.dot'. +Dumping module test1 to page 1. + +9. Generating Graphviz representation of design. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $or. +No more expansions possible. + + +12. Executing OPT pass (performing simple optimizations). + +12.1. Executing OPT_EXPR pass (perform const folding). Eval result: \out = 270369. yosys [xorshift32]> eval -set in 270369 -show out 8. Executing EVAL pass (evaluate the circuit given an input). +Writing dot description to `opt_expr_full.dot'. +Dumping module after to page 1. +Dumping module uut to page 2. +Writing dot description to `macc_xilinx_test2b.dot'. +Dumping module test2 to page 1. + +End of script. Logfile hash: 1d1df32b64, CPU: user 0.02s system 0.00s, MEM: 8.05 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 44% 1x opt_expr (0 sec), 30% 1x clean (0 sec), ... + +10. Executing TECHMAP pass (map to technology primitives). Eval result: \out = 67634689. yosys [xorshift32]> sat -set out 632435482 9. Executing SAT pass (solving SAT problems in the circuit). -Creating needle graph needle_DSP48_MACC. -Creating haystack graph haystack_$__add_wrapper. -Creating haystack graph haystack_$__mul_wrapper. -Creating haystack graph haystack_DSP48_MACC. -Creating haystack graph haystack_test1. -Creating haystack graph haystack_test2. -17.2. Running solver from SubCircuit library. -Solving for needle_DSP48_MACC in haystack_$__add_wrapper. -Solving for needle_DSP48_MACC in haystack_$__mul_wrapper. -Solving for needle_DSP48_MACC in haystack_DSP48_MACC. -Solving for needle_DSP48_MACC in haystack_test1. -Solving for needle_DSP48_MACC in haystack_test2. -Found 3 matches. +10.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v +gvpack -u -o opt_expr.dot opt_expr_full.dot +Optimizing module counter. + -17.3. Substitute SubCircuits with cells. +12.2. Executing OPT_MERGE pass (detect identical cells). +Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. +Generating RTLIL representation for module `\mul_wrap'. +Generating RTLIL representation for module `\add_wrap'. +Successfully finished Verilog frontend. + +10.2. Continuing TECHMAP pass. +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. +Performed a total of 0 changes. + +12.5. Executing OPT_MERGE pass (detect identical cells). Setting up SAT problem: Import set-constraint: \out = 632435482 @@ -32566,33 +32444,15 @@ Imported 3 cells to SAT database. Solving problem with 665 variables and 1735 clauses.. +Finding identical cells in module `\counter'. +Removed a total of 0 cells. -Match #0: (needle_DSP48_MACC in haystack_test1) - $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$3 \A:\B \B:\A \Y:\Y - $const$0 -> $const$0 \Y:\Y - $const$1 -> $const$1 \Y:\Y - $const$x -> $const$x \Y:\Y - $const$z -> $const$z \Y:\Y - $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$2 \A:\A \B:\B \Y:\Y - new cell: $extract$\DSP48_MACC$35 - -Match #1: (needle_DSP48_MACC in haystack_test1) - $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$5 \A:\B \B:\A \Y:\Y - $const$0 -> $const$0 \Y:\Y - $const$1 -> $const$1 \Y:\Y - $const$x -> $const$x \Y:\Y - $const$z -> $const$z \Y:\Y - $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$4 \A:\A \B:\B \Y:\Y - new cell: $extract$\DSP48_MACC$36 +12.6. Executing OPT_DFF pass (perform DFF optimizations). +Warning: node n1 in graph[1] uut already defined +Some nodes will be renamed. -Match #2: (needle_DSP48_MACC in haystack_test2) - $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:12$9 \A:\A \B:\B \Y:\Y - $const$0 -> $const$0 \Y:\Y - $const$1 -> $const$1 \Y:\Y - $const$x -> $const$x \Y:\Y - $const$z -> $const$z \Y:\Y - $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:12$7 \A:\A \B:\B \Y:\Y - new cell: $extract$\DSP48_MACC$37 +12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/opt' SAT solving finished - model found: Signal Name Dec Hex Bin @@ -32600,94 +32460,47 @@ \in 745495504 2c6f5bd0 00101100011011110101101111010000 \out 632435482 25b2331a 00100101101100100011001100011010 -End of script. Logfile hash: 759d6d2a7e, CPU: user 0.05s system 0.01s, MEM: 10.40 MB peak +End of script. Logfile hash: 759d6d2a7e, CPU: user 0.05s system 0.01s, MEM: 10.39 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 22% 1x sat (0 sec), 21% 1x submod (0 sec), ... -Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 -ABC: ABC command line: "source /abc.script". -ABC: -ABC: + read_blif /input.blif -ABC: + read_lib -w /docs/source/code_examples/intro/mycells.lib -ABC: Parsing finished successfully. Parsing time = 0.00 sec -ABC: Warning: Templates are not defined. -ABC: Liberty parser cannot read "time_unit". Assuming time_unit : "1ns". -ABC: Liberty parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). -ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". -ABC: Library "demo" from "/docs/source/code_examples/intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec -ABC: Memory = 0.00 MB. Time = 0.00 sec -ABC: + strash -ABC: + &get -n -ABC: + &fraig -x -ABC: + &put -ABC: + scorr -ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). -ABC: + dc2 -ABC: + dretime -ABC: + strash -ABC: + &get -n -ABC: + &dch -f -ABC: + &nf -ABC: + &put -ABC: + write_blif /output.blif +Finding unused cells or wires in module \counter.. +Removed 1 unused cells and 32 unused wires. + -16.1.2. Re-integrating ABC results. -ABC RESULTS: NAND cells: 4 -ABC RESULTS: NOR cells: 4 -ABC RESULTS: NOT cells: 3 -ABC RESULTS: internal signals: 5 -ABC RESULTS: input signals: 4 -ABC RESULTS: output signals: 2 -Removing temp directory. +12.8. Executing OPT_EXPR pass (perform const folding). ../../../../yosys scrambler.ys -Removed 0 unused cells and 10 unused wires. - -17. Generating Graphviz representation of design. -Removed 0 unused cells and 6 unused wires. - -18. Generating Graphviz representation of design. +Optimizing module counter. -17.1. Executing Verilog-2005 frontend: mycells.v -Parsing Verilog input from `mycells.v' to AST representation. -Generating RTLIL representation for module `\NOT'. -Generating RTLIL representation for module `\NAND'. -Generating RTLIL representation for module `\NOR'. -Generating RTLIL representation for module `\DFF'. -Successfully finished Verilog frontend. +12.9. Rerunning OPT passes. (Maybe there is more to do..) -17.2. Continuing show pass. -Writing dot description to `macc_xilinx_test1d.dot'. -Dumping module test1 to page 1. +12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. -19. Generating Graphviz representation of design. -Writing dot description to `counter_03.dot'. -Dumping module counter to page 1. +12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. +Performed a total of 0 changes. -18. Executing Verilog backend. +12.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\counter'. +Removed a total of 0 cells. -18.1. Executing BMUXMAP pass. +12.13. Executing OPT_DFF pass (perform DFF optimizations). -18.2. Executing DEMUXMAP pass. -Writing dot description to `macc_xilinx_test2d.dot'. -Dumping module test2 to page 1. +12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \counter.. -20. Executing TECHMAP pass (map to technology primitives). +12.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module counter. -20.1. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v -Dumping module `\counter'. +12.16. Finished OPT passes. (There is nothing left to do.) -End of script. Logfile hash: 22b20c9afa, CPU: user 0.19s system 0.02s, MEM: 12.58 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 46% 1x abc (0 sec), 13% 13x opt_expr (0 sec), ... -Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. -Generating RTLIL representation for module `\$__mul_wrapper'. -Generating RTLIL representation for module `\$__add_wrapper'. -Successfully finished Verilog frontend. +13. Executing SPLITNETS pass (splitting up multi-bit signals). +Removed 0 unused cells and 2 unused wires. -20.2. Continuing TECHMAP pass. -Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\$__mul_wrapper for cells of type $__mul_wrapper. -../../../../yosys counter.ys -Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\$__add_wrapper for cells of type $__add_wrapper. -No more expansions possible. +14. Generating Graphviz representation of design. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -32699,18 +32512,58 @@ -- Executing script file `scrambler.ys' -- 1. Executing Verilog-2005 frontend: scrambler.v +Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\mul_wrap for cells of type $mul. +Writing dot description to `counter_02.dot'. +Dumping module counter to page 1. + +15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). Parsing Verilog input from `scrambler.v' to AST representation. Generating RTLIL representation for module `\scrambler'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). + cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. + final dff cell mappings: + unmapped dff cell: $_DFF_N_ + \DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); + unmapped dff cell: $_DFF_NN0_ + unmapped dff cell: $_DFF_NN1_ + unmapped dff cell: $_DFF_NP0_ + unmapped dff cell: $_DFF_NP1_ + unmapped dff cell: $_DFF_PN0_ + unmapped dff cell: $_DFF_PN1_ + unmapped dff cell: $_DFF_PP0_ + unmapped dff cell: $_DFF_PP1_ + unmapped dff cell: $_DFFE_NN_ + unmapped dff cell: $_DFFE_NP_ + unmapped dff cell: $_DFFE_PN_ + unmapped dff cell: $_DFFE_PP_ + unmapped dff cell: $_DFFSR_NNN_ + unmapped dff cell: $_DFFSR_NNP_ + unmapped dff cell: $_DFFSR_NPN_ + unmapped dff cell: $_DFFSR_NPP_ + unmapped dff cell: $_DFFSR_PNN_ + unmapped dff cell: $_DFFSR_PNP_ + unmapped dff cell: $_DFFSR_PPN_ + unmapped dff cell: $_DFFSR_PPP_ + +15.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). +Mapping DFF cells in module `\counter': + mapped 2 $_DFF_P_ cells to \DFF cells. + +16. Executing ABC pass (technology mapping using ABC). 3. Executing PROC pass (convert processes to netlists). +16.1. Extracting gate netlist of module `\counter' to `/input.blif'.. + 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Extracted 6 gates and 11 wires to a netlist network with 4 inputs and 2 outputs. + +16.1.1. Executing ABC. Marked 1 switch rules as full_case in process $proc$scrambler.v:6$1 in module scrambler. Removed a total of 0 dead cases. @@ -32746,139 +32599,19 @@ Cleaned up 1 empty switch. 3.12. Executing OPT_EXPR pass (perform const folding). - -Removed 0 unused cells and 14 unused wires. - -21. Generating Graphviz representation of design. - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `counter.ys' -- - -1. Executing Verilog-2005 frontend: counter.v -Writing dot description to `macc_xilinx_test1e.dot'. -Dumping module test1 to page 1. - -22. Generating Graphviz representation of design. -Parsing Verilog input from `counter.v' to AST representation. -Generating RTLIL representation for module `\counter'. -Successfully finished Verilog frontend. - -2. Executing HIERARCHY pass (managing design hierarchy). - -2.1. Analyzing design hierarchy.. -Top module: \counter - -2.2. Analyzing design hierarchy.. -Top module: \counter -Removed 0 unused modules. - -3. Generating Graphviz representation of design. Optimizing module scrambler. -Writing dot description to `macc_xilinx_test2e.dot'. -Dumping module test2 to page 1. - -23. Generating Graphviz representation of design. -Writing dot description to `counter_00.dot'. -Dumping module counter to page 1. - -4. Executing PROC pass (convert processes to netlists). - -4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 1 switch rules as full_case in process $proc$counter.v:6$1 in module counter. -Removed a total of 0 dead cases. - -4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. - -4.4. Executing PROC_INIT pass (extract init attributes). - -4.5. Executing PROC_ARST pass (detect async resets in processes). - -4.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - - -4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\counter.$proc$counter.v:6$1'. - 1/1: $0\count[1:0] - -4.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -4.9. Executing PROC_DFF pass (convert process syncs to FFs). -Writing dot description to `macc_xilinx_xmap.dot'. -Dumping module DSP48_MACC to page 1. -Creating register for signal `\counter.\count' using process `\counter.$proc$counter.v:6$1'. - created $dff cell `$procdff$8' with positive edge clock. - -4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 2 empty switches in `\counter.$proc$counter.v:6$1'. -Removing empty process `counter.$proc$counter.v:6$1'. -Cleaned up 2 empty switches. - -4.12. Executing OPT_EXPR pass (perform const folding). - -End of script. Logfile hash: 750c951a95, CPU: user 0.24s system 0.00s, MEM: 10.62 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 42% 12x clean (0 sec), 16% 5x techmap (0 sec), ... -Optimizing module counter. - -5. Executing OPT pass (performing simple optimizations). - -5.1. Executing OPT_EXPR pass (perform const folding). -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' +Using template $paramod$48197a291a9e3825142389e9d2e41385cae2467c\mul_wrap for cells of type $mul. Removed 0 unused cells and 5 unused wires. 4. Executing SUBMOD pass (moving cells to submodules as requested). -Optimizing module counter. - -5.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. - -5.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -5.6. Executing OPT_DFF pass (perform DFF optimizations). 4.1. Executing OPT_CLEAN pass (remove unused cells and wires). -Adding SRST signal on $procdff$8 ($dff) from module counter (D = $procmux$3_Y, Q = \count, rval = 2'00). -Adding EN signal on $auto$ff.cc:266:slice$9 ($sdff) from module counter (D = $add$counter.v:10$2_Y, Q = \count). - -5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' +../../../../yosys select.ys Finding unused cells or wires in module \scrambler.. 4.2. Continuing SUBMOD pass. -Finding unused cells or wires in module \counter.. -Removed 2 unused cells and 5 unused wires. - - -5.8. Executing OPT_EXPR pass (perform const folding). Creating submodule xorshift32 (\xorshift32) of module \scrambler. signal $0\xs[31:0]: output \n1 signal $1\xs[31:0]: input \n2 @@ -32893,27 +32626,13 @@ 5. Generating Graphviz representation of design. Writing dot description to `scrambler_p01.dot'. Dumping module scrambler to page 1. -Optimizing module counter. 6. Generating Graphviz representation of design. +Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\add_wrap for cells of type $add. +No more expansions possible. + -5.9. Rerunning OPT passes. (Maybe there is more to do..) - -5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. - -5.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -5.13. Executing OPT_DFF pass (perform DFF optimizations). +11. Executing CONNWRAPPERS pass (connect extended ports of wrapper cells). Writing dot description to `scrambler_p02.dot'. Dumping module xorshift32 to page 1. echo on @@ -32929,8 +32648,6 @@ yosys [xorshift32]> eval -set in 1 -show out 7. Executing EVAL pass (evaluate the circuit given an input). - -5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Eval result: \out = 270369. yosys [xorshift32]> eval -set in 270369 -show out @@ -32941,140 +32658,6 @@ yosys [xorshift32]> sat -set out 632435482 9. Executing SAT pass (solving SAT problems in the circuit). -Finding unused cells or wires in module \counter.. - -5.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. - -5.16. Finished OPT passes. (There is nothing left to do.) - -6. Executing MEMORY pass. - -6.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. - -6.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). -Performed a total of 0 transformations. - -6.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). - -Setting up SAT problem: -Import set-constraint: \out = 632435482 -Final constraint equation: \out = 632435482 -Imported 3 cells to SAT database. - -Solving problem with 665 variables and 1735 clauses.. - -6.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). - -6.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). - -6.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \counter.. -SAT solving finished - model found: - - Signal Name Dec Hex Bin - --------------- ----------- --------- ----------------------------------- - \in 745495504 2c6f5bd0 00101100011011110101101111010000 - \out 632435482 25b2331a 00100101101100100011001100011010 - -End of script. Logfile hash: 759d6d2a7e, CPU: user 0.05s system 0.00s, MEM: 10.40 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 22% 1x sat (0 sec), 20% 1x submod (0 sec), ... - -6.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). - -6.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). -Performed a total of 0 transformations. - -6.9. Executing OPT_CLEAN pass (remove unused cells and wires). -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' -Finding unused cells or wires in module \counter.. - -6.10. Executing MEMORY_COLLECT pass (generating $mem cells). - -6.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). - -7. Executing OPT pass (performing simple optimizations). - -7.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. - -7.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. - -7.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -7.6. Executing OPT_DFF pass (perform DFF optimizations). - -7.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \counter.. - -7.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. - -7.9. Finished OPT passes. (There is nothing left to do.) - -8. Executing FSM pass (extract and optimize FSM). - -8.1. Executing FSM_DETECT pass (finding FSMs in design). - -8.2. Executing FSM_EXTRACT pass (extracting FSM from design). - -8.3. Executing FSM_OPT pass (simple optimizations of FSMs). - -8.4. Executing OPT_CLEAN pass (remove unused cells and wires). -make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' -../../../../yosys select.ys -Finding unused cells or wires in module \counter.. - -8.5. Executing FSM_OPT pass (simple optimizations of FSMs). - -8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). - -8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). - -8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). - -9. Executing OPT pass (performing simple optimizations). - -9.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. - -9.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. - -9.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -9.6. Executing OPT_DFF pass (perform DFF optimizations). - -9.7. Executing OPT_CLEAN pass (remove unused cells and wires). /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -33086,9 +32669,6 @@ -- Executing script file `select.ys' -- 1. Executing Verilog-2005 frontend: select.v -Finding unused cells or wires in module \counter.. - -9.8. Executing OPT_EXPR pass (perform const folding). Parsing Verilog input from `select.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. @@ -33137,42 +32717,83 @@ 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Optimizing module counter. Removing empty process `test.$proc$select.v:7$1'. Cleaned up 0 empty switches. 2.2.12. Executing OPT_EXPR pass (perform const folding). -9.9. Finished OPT passes. (There is nothing left to do.) - -10. Generating Graphviz representation of design. -Writing dot description to `counter_01.dot'. -Dumping module counter to page 1. - -11. Executing TECHMAP pass (map to technology primitives). +Setting up SAT problem: +Import set-constraint: \out = 632435482 +Final constraint equation: \out = 632435482 +Imported 3 cells to SAT database. -11.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v +Solving problem with 665 variables and 1735 clauses.. Optimizing module test. 2.3. Executing FUTURE pass. +SAT solving finished - model found: + + Signal Name Dec Hex Bin + --------------- ----------- --------- ----------------------------------- + \in 745495504 2c6f5bd0 00101100011011110101101111010000 + \out 632435482 25b2331a 00100101101100100011001100011010 + +End of script. Logfile hash: 759d6d2a7e, CPU: user 0.06s system 0.00s, MEM: 10.39 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 21% 1x sat (0 sec), 20% 1x submod (0 sec), ... 2.4. Executing OPT_EXPR pass (perform const folding). +Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:A: { 6'000000 $add$macc_xilinx_test.v:5$3_Y } -> { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } +Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:B: { 6'000000 $mul$macc_xilinx_test.v:5$4_Y } -> { $techmap25$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y } +Connected extended bits of test1.$add$macc_xilinx_test.v:5$3:B: { 6'000000 $mul$macc_xilinx_test.v:5$2_Y } -> { $techmap23$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y } +Connected extended bits of test2.$add$macc_xilinx_test.v:12$10:B: { 6'000000 $add$macc_xilinx_test.v:12$9_Y } -> { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } +Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:A: { 6'000000 $mul$macc_xilinx_test.v:12$7_Y } -> { $techmap19$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y } +Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:B: { 6'000000 $mul$macc_xilinx_test.v:12$8_Y } -> { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } +Removed 0 unused cells and 56 unused wires. + +12. Generating Graphviz representation of design. +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/scrambler' Optimizing module test. 2.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Writing dot description to `macc_xilinx_test1c.dot'. +Dumping module test1 to page 1. + +13. Generating Graphviz representation of design. +Writing dot description to `macc_xilinx_test2c.dot'. +Dumping module test2 to page 1. + +14. Executing Verilog-2005 frontend: macc_xilinx_xmap.v Finding unused cells or wires in module \test.. Removed 1 unused cells and 6 unused wires. 2.6. Executing CHECK pass (checking for obvious problems). -../../../../yosys memdemo.ys +Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. +Generating RTLIL representation for module `\DSP48_MACC'. +Successfully finished Verilog frontend. + +15. Executing TECHMAP pass (map to technology primitives). + +15.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v +Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. +Generating RTLIL representation for module `\mul_swap_ports'. +Successfully finished Verilog frontend. + +15.2. Continuing TECHMAP pass. Checking module test... Found and reported 0 problems. 2.7. Executing OPT pass (performing simple optimizations). 2.7.1. Executing OPT_EXPR pass (perform const folding). +No more expansions possible. + + +16. Executing TECHMAP pass (map to technology primitives). + +16.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v Optimizing module test. 2.7.2. Executing OPT_MERGE pass (detect identical cells). @@ -33189,6 +32810,12 @@ 2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. +Generating RTLIL representation for module `\mul_wrap'. +Generating RTLIL representation for module `\add_wrap'. +Successfully finished Verilog frontend. + +16.2. Continuing TECHMAP pass. Optimizing cells in module \test. Performed a total of 0 changes. @@ -33202,17 +32829,6 @@ 2.7.7. Executing OPT_EXPR pass (perform const folding). - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `memdemo.ys' -- - -1. Executing Verilog-2005 frontend: memdemo.v Optimizing module test. 2.7.8. Rerunning OPT passes. (Maybe there is more to do..) @@ -33234,128 +32850,19 @@ Removed a total of 0 cells. 2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). -Parsing Verilog input from `memdemo.v' to AST representation. -Generating RTLIL representation for module `\memdemo'. -Successfully finished Verilog frontend. - -2. Executing PREP pass. - -2.1. Executing HIERARCHY pass (managing design hierarchy). - -2.1.1. Analyzing design hierarchy.. -Top module: \memdemo - -2.1.2. Analyzing design hierarchy.. -Top module: \memdemo -Removed 0 unused modules. - -2.2. Executing PROC pass (convert processes to netlists). - -2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/show' +../../../../yosys -p 'prep -top splice_demo; show -format dot -prefix splice' splice.v Finding unused cells or wires in module \test.. -Cleaned up 0 empty switches. - -2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2.7.13. Executing OPT_EXPR pass (perform const folding). -Removed 0 redundant assignments. -Promoted 14 assignments to connections. - -2.2.4. Executing PROC_INIT pass (extract init attributes). - -2.2.5. Executing PROC_ARST pass (detect async resets in processes). - -2.2.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - -2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\memdemo.$proc$memdemo.v:11$7'. - -2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\memdemo.\y' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$35' with positive edge clock. -Creating register for signal `\memdemo.\i' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$36' with positive edge clock. -Creating register for signal `\memdemo.\s1' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$37' with positive edge clock. -Creating register for signal `\memdemo.\s2' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$38' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$39' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$40' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$41' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$42' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$43' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$44' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$45' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$46' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_ADDR' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$47' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$48' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$49' with positive edge clock. - -2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +Using template $paramod$81421da67e3cf07e7ac8b39f28efc75ee750e82a\mul_wrap for cells of type $mul. Optimizing module test. -2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `memdemo.$proc$memdemo.v:11$7'. -Cleaned up 0 empty switches. - -2.2.12. Executing OPT_EXPR pass (perform const folding). -Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu_brent_kung'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod_trunc'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\$__div_mod_floor'. -Generating RTLIL representation for module `\_90_divfloor'. -Generating RTLIL representation for module `\_90_modfloor'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_demux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -11.2. Continuing TECHMAP pass. - 2.7.14. Finished OPT passes. (There is nothing left to do.) 2.8. Executing WREDUCE pass (reducing word size of cells). 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. -Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. -Using extmapper simplemap for cells of type $sdffe. -Optimizing module memdemo. - -2.3. Executing FUTURE pass. Finding unused cells or wires in module \test.. 2.10. Executing MEMORY_COLLECT pass (generating $mem cells). @@ -33363,25 +32870,17 @@ 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). -Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. -Using extmapper simplemap for cells of type $xor. -Using extmapper simplemap for cells of type $and. Optimizing module test. 2.11.2. Executing OPT_MERGE pass (detect identical cells). - -2.4. Executing OPT_EXPR pass (perform const folding). Finding identical cells in module `\test'. Removed a total of 0 cells. 2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module memdemo. Finding unused cells or wires in module \test.. 2.11.4. Finished fast OPT passes. -2.5. Executing OPT_CLEAN pass (remove unused cells and wires). - 2.12. Printing statistics. === test === @@ -33405,87 +32904,121 @@ 2.13. Executing CHECK pass (checking for obvious problems). Checking module test... Found and reported 0 problems. -Finding unused cells or wires in module \memdemo.. -Removed 12 unused cells and 26 unused wires. - -2.6. Executing CHECK pass (checking for obvious problems). + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Parsing `splice.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: splice.v +Using template $paramod$88aad6f8473fb7e4e5fbfb8335ddebad03429eaa\add_wrap for cells of type $add. +No more expansions possible. +Parsing Verilog input from `splice.v' to AST representation. +Storing AST representation for module `$abstract\splice_demo'. +Successfully finished Verilog frontend. + +-- Running command `prep -top splice_demo; show -format dot -prefix splice' -- + +2. Executing PREP pass. + +2.1. Executing HIERARCHY pass (managing design hierarchy). + +2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\splice_demo'. +Generating RTLIL representation for module `\splice_demo'. + +2.2.1. Analyzing design hierarchy.. +Top module: \splice_demo + +2.2.2. Analyzing design hierarchy.. +Top module: \splice_demo +Removing unused module `$abstract\splice_demo'. +Removed 1 unused modules. + +2.3. Executing PROC pass (convert processes to netlists). + +2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 3. Generating Graphviz representation of design. -Checking module memdemo... -Found and reported 0 problems. +Cleaned up 0 empty switches. -2.7. Executing OPT pass (performing simple optimizations). +2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. -2.7.1. Executing OPT_EXPR pass (perform const folding). +2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +2.3.4. Executing PROC_INIT pass (extract init attributes). + +2.3.5. Executing PROC_ARST pass (detect async resets in processes). + +2.3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Writing dot description to `select.dot'. Dumping module test to page 1. -End of script. Logfile hash: f11d6793ac, CPU: user 0.06s system 0.01s, MEM: 8.84 MB peak +End of script. Logfile hash: f11d6793ac, CPU: user 0.06s system 0.01s, MEM: 8.83 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 30% 6x opt_expr (0 sec), 29% 5x opt_clean (0 sec), ... -Optimizing module memdemo. -2.7.2. Executing OPT_MERGE pass (detect identical cells). -../../../../yosys memdemo.ys -Finding identical cells in module `\memdemo'. - -Removed a total of 4 cells. +2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \memdemo.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - +2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. -2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. -Performed a total of 0 changes. +2.3.12. Executing OPT_EXPR pass (perform const folding). + +Removed 0 unused cells and 17 unused wires. -2.7.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +17. Executing EXTRACT pass (map subcircuits to cells). -2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 4 unused wires. - +17.1. Creating graphs for SubCircuit library. +../../../../yosys memdemo.ys +Optimizing module splice_demo. -2.7.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. +2.4. Executing FUTURE pass. -2.7.8. Rerunning OPT passes. (Maybe there is more to do..) +2.5. Executing OPT_EXPR pass (perform const folding). +Optimizing module splice_demo. -2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \memdemo.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. +2.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \splice_demo.. +Removed 0 unused cells and 2 unused wires. -2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. -Performed a total of 0 changes. +2.7. Executing CHECK pass (checking for obvious problems). +Checking module splice_demo... +Found and reported 0 problems. -2.7.11. Executing OPT_MERGE pass (detect identical cells). -Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. -Using extmapper simplemap for cells of type $pos. -Using extmapper simplemap for cells of type $mux. -Using extmapper simplemap for cells of type $not. -Using extmapper simplemap for cells of type $or. -No more expansions possible. - +2.8. Executing OPT pass (performing simple optimizations). -12. Executing OPT pass (performing simple optimizations). +2.8.1. Executing OPT_EXPR pass (perform const folding). +Creating needle graph needle_DSP48_MACC. +Creating haystack graph haystack_$__add_wrapper. +Creating haystack graph haystack_$__mul_wrapper. +Creating haystack graph haystack_DSP48_MACC. +Creating haystack graph haystack_test1. +Creating haystack graph haystack_test2. -12.1. Executing OPT_EXPR pass (perform const folding). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +17.2. Running solver from SubCircuit library. +Solving for needle_DSP48_MACC in haystack_$__add_wrapper. +Solving for needle_DSP48_MACC in haystack_$__mul_wrapper. +Solving for needle_DSP48_MACC in haystack_DSP48_MACC. +Solving for needle_DSP48_MACC in haystack_test1. +Solving for needle_DSP48_MACC in haystack_test2. +Found 3 matches. -2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). +17.3. Substitute SubCircuits with cells. /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -33497,42 +33030,54 @@ -- Executing script file `memdemo.ys' -- 1. Executing Verilog-2005 frontend: memdemo.v -Finding unused cells or wires in module \memdemo.. +Optimizing module splice_demo. -2.7.13. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. - +2.8.2. Executing OPT_MERGE pass (detect identical cells). -12.2. Executing OPT_MERGE pass (detect identical cells). -Optimizing module memdemo. +Match #0: (needle_DSP48_MACC in haystack_test1) + $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$3 \A:\B \B:\A \Y:\Y + $const$0 -> $const$0 \Y:\Y + $const$1 -> $const$1 \Y:\Y + $const$x -> $const$x \Y:\Y + $const$z -> $const$z \Y:\Y + $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$2 \A:\A \B:\B \Y:\Y + new cell: $extract$\DSP48_MACC$35 -2.7.14. Finished OPT passes. (There is nothing left to do.) +Match #1: (needle_DSP48_MACC in haystack_test1) + $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$5 \A:\B \B:\A \Y:\Y + $const$0 -> $const$0 \Y:\Y + $const$1 -> $const$1 \Y:\Y + $const$x -> $const$x \Y:\Y + $const$z -> $const$z \Y:\Y + $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$4 \A:\A \B:\B \Y:\Y + new cell: $extract$\DSP48_MACC$36 -2.8. Executing WREDUCE pass (reducing word size of cells). -Finding identical cells in module `\counter'. +Match #2: (needle_DSP48_MACC in haystack_test2) + $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:12$9 \A:\A \B:\B \Y:\Y + $const$0 -> $const$0 \Y:\Y + $const$1 -> $const$1 \Y:\Y + $const$x -> $const$x \Y:\Y + $const$z -> $const$z \Y:\Y + $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:12$7 \A:\A \B:\B \Y:\Y + new cell: $extract$\DSP48_MACC$37 +Finding identical cells in module `\splice_demo'. Removed a total of 0 cells. -12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$50 (mem). -Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$51 (mem). -Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$52 (mem). -Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$53 (mem). -Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$19 (mem). -Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$20 (mem). -Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$23 (mem). -Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$26 (mem). - -2.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Running muxtree optimizer on module \counter.. +2.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \splice_demo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. -12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. +2.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \splice_demo. Performed a total of 0 changes. -12.5. Executing OPT_MERGE pass (detect identical cells). +2.8.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\splice_demo'. +Removed a total of 0 cells. + +2.8.6. Executing OPT_CLEAN pass (remove unused cells and wires). Parsing Verilog input from `memdemo.v' to AST representation. Generating RTLIL representation for module `\memdemo'. Successfully finished Verilog frontend. @@ -33571,15 +33116,11 @@ Creating decoders for process `\memdemo.$proc$memdemo.v:11$7'. 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -12.6. Executing OPT_DFF pass (perform DFF optimizations). 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -Finding unused cells or wires in module \memdemo.. +Finding unused cells or wires in module \splice_demo.. -2.10. Executing MEMORY_COLLECT pass (generating $mem cells). +2.8.7. Executing OPT_EXPR pass (perform const folding). Creating register for signal `\memdemo.\y' using process `\memdemo.$proc$memdemo.v:11$7'. created $dff cell `$procdff$35' with positive edge clock. Creating register for signal `\memdemo.\i' using process `\memdemo.$proc$memdemo.v:11$7'. @@ -33613,151 +33154,112 @@ 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -2.11. Executing OPT pass (performing simple optimizations). - -2.11.1. Executing OPT_EXPR pass (perform const folding). - 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `memdemo.$proc$memdemo.v:11$7'. Cleaned up 0 empty switches. 2.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module splice_demo. +Removed 0 unused cells and 6 unused wires. -12.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module memdemo. +18. Generating Graphviz representation of design. -2.11.2. Executing OPT_MERGE pass (detect identical cells). +2.8.8. Finished OPT passes. (There is nothing left to do.) Optimizing module memdemo. +2.9. Executing WREDUCE pass (reducing word size of cells). + 2.3. Executing FUTURE pass. -Finding unused cells or wires in module \counter.. -Removed 1 unused cells and 32 unused wires. - -12.8. Executing OPT_EXPR pass (perform const folding). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +2.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Writing dot description to `macc_xilinx_test1d.dot'. +Dumping module test1 to page 1. -2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +19. Generating Graphviz representation of design. 2.4. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \memdemo.. - -2.11.4. Finished fast OPT passes. - -2.12. Printing statistics. - -=== memdemo === - - Number of wires: 18 - Number of wire bits: 58 - Number of public wires: 5 - Number of public wire bits: 13 - Number of ports: 3 - Number of port bits: 9 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 11 - $add 4 - $dff 3 - $mem_v2 1 - $mux 1 - $reduce_bool 1 - $xor 1 - -2.13. Executing CHECK pass (checking for obvious problems). -Optimizing module counter. - -12.9. Rerunning OPT passes. (Maybe there is more to do..) +Finding unused cells or wires in module \splice_demo.. -12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \counter.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. +2.11. Executing MEMORY_COLLECT pass (generating $mem cells). -12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \counter. -Performed a total of 0 changes. +2.12. Executing OPT pass (performing simple optimizations). -12.12. Executing OPT_MERGE pass (detect identical cells). -Checking module memdemo... -Found and reported 0 problems. +2.12.1. Executing OPT_EXPR pass (perform const folding). +Writing dot description to `macc_xilinx_test2d.dot'. +Dumping module test2 to page 1. -3. Executing MEMORY pass. +20. Executing TECHMAP pass (map to technology primitives). -3.1. Executing OPT_MEM pass (optimize memories). +20.1. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v Optimizing module memdemo. -Performed a total of 0 transformations. - -3.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 2.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding identical cells in module `\counter'. -Removed a total of 0 cells. - -12.13. Executing OPT_DFF pass (perform DFF optimizations). - -12.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Performed a total of 6 transformations. - -3.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). - Analyzing memdemo.mem write port 0. - Analyzing memdemo.mem write port 1. - Analyzing memdemo.mem write port 2. - Analyzing memdemo.mem write port 3. - Analyzing memdemo.mem write port 4. +Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. +Generating RTLIL representation for module `\$__mul_wrapper'. +Generating RTLIL representation for module `\$__add_wrapper'. +Successfully finished Verilog frontend. -3.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). +20.2. Continuing TECHMAP pass. +Optimizing module splice_demo. -3.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Finding unused cells or wires in module \counter.. +2.12.2. Executing OPT_MERGE pass (detect identical cells). +Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\$__mul_wrapper for cells of type $__mul_wrapper. +Finding identical cells in module `\splice_demo'. +Removed a total of 0 cells. -12.15. Executing OPT_EXPR pass (perform const folding). +2.12.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\$__add_wrapper for cells of type $__add_wrapper. +No more expansions possible. Finding unused cells or wires in module \memdemo.. Removed 12 unused cells and 26 unused wires. 2.6. Executing CHECK pass (checking for obvious problems). +Finding unused cells or wires in module \splice_demo.. + +2.12.4. Finished fast OPT passes. + +2.13. Printing statistics. + +=== splice_demo === + + Number of wires: 8 + Number of wire bits: 26 + Number of public wires: 8 + Number of public wire bits: 26 + Number of ports: 8 + Number of port bits: 26 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + $neg 1 + $not 1 + +2.14. Executing CHECK pass (checking for obvious problems). +Checking module splice_demo... +Found and reported 0 problems. + +3. Generating Graphviz representation of design. Checking module memdemo... Found and reported 0 problems. 2.7. Executing OPT pass (performing simple optimizations). 2.7.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module counter. -Checking read port `\mem'[0] in module `\memdemo': merging output FF to cell. - Write port 0: non-transparent. - Write port 1: non-transparent. - Write port 2: non-transparent. - Write port 3: non-transparent. - Write port 4: non-transparent. -Checking read port `\mem'[1] in module `\memdemo': no output FF found. -Checking read port `\mem'[2] in module `\memdemo': no output FF found. -Checking read port `\mem'[3] in module `\memdemo': no output FF found. -Checking read port `\mem'[4] in module `\memdemo': no output FF found. -Checking read port address `\mem'[1] in module `\memdemo': no address FF found. -Checking read port address `\mem'[2] in module `\memdemo': no address FF found. -Checking read port address `\mem'[3] in module `\memdemo': no address FF found. -Checking read port address `\mem'[4] in module `\memdemo': no address FF found. - -3.6. Executing OPT_CLEAN pass (remove unused cells and wires). - -12.16. Finished OPT passes. (There is nothing left to do.) - -13. Executing SPLITNETS pass (splitting up multi-bit signals). +Writing dot description to `splice.dot'. +Dumping module splice_demo to page 1. Optimizing module memdemo. 2.7.2. Executing OPT_MERGE pass (detect identical cells). -Finding unused cells or wires in module \memdemo.. -Removed 1 unused cells and 5 unused wires. - -3.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). -Removed 0 unused cells and 2 unused wires. +End of script. Logfile hash: 2eeb6955f1, CPU: user 0.04s system 0.01s, MEM: 8.59 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 36% 5x opt_expr (0 sec), 26% 4x opt_clean (0 sec), ... + +Removed 0 unused cells and 14 unused wires. -14. Generating Graphviz representation of design. +21. Generating Graphviz representation of design. Finding identical cells in module `\memdemo'. Removed a total of 4 cells. @@ -33775,85 +33277,30 @@ Performed a total of 0 changes. 2.7.5. Executing OPT_MERGE pass (detect identical cells). -Consolidating read ports of memory memdemo.mem by address: - Merging ports 1, 4 (address 2'00). - Merging ports 2, 3 (address 2'11). -Consolidating read ports of memory memdemo.mem by address: - Merging ports 1, 2 (address 2'00). -Consolidating read ports of memory memdemo.mem by address: -Consolidating write ports of memory memdemo.mem by address: - Merging ports 0, 1 (address 2'00). - Merging ports 0, 2 (address 2'00). -Consolidating write ports of memory memdemo.mem by address: - -3.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). -Performed a total of 0 transformations. - -3.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Writing dot description to `counter_02.dot'. -Dumping module counter to page 1. - -15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). - cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. - final dff cell mappings: - unmapped dff cell: $_DFF_N_ - \DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); - unmapped dff cell: $_DFF_NN0_ - unmapped dff cell: $_DFF_NN1_ - unmapped dff cell: $_DFF_NP0_ - unmapped dff cell: $_DFF_NP1_ - unmapped dff cell: $_DFF_PN0_ - unmapped dff cell: $_DFF_PN1_ - unmapped dff cell: $_DFF_PP0_ - unmapped dff cell: $_DFF_PP1_ - unmapped dff cell: $_DFFE_NN_ - unmapped dff cell: $_DFFE_NP_ - unmapped dff cell: $_DFFE_PN_ - unmapped dff cell: $_DFFE_PP_ - unmapped dff cell: $_DFFSR_NNN_ - unmapped dff cell: $_DFFSR_NNP_ - unmapped dff cell: $_DFFSR_NPN_ - unmapped dff cell: $_DFFSR_NPP_ - unmapped dff cell: $_DFFSR_PNN_ - unmapped dff cell: $_DFFSR_PNP_ - unmapped dff cell: $_DFFSR_PPN_ - unmapped dff cell: $_DFFSR_PPP_ +../../../../yosys example.ys +Writing dot description to `macc_xilinx_test1e.dot'. +Dumping module test1 to page 1. -15.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). +22. Generating Graphviz representation of design. Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Mapping DFF cells in module `\counter': - mapped 2 $_DFF_P_ cells to \DFF cells. - -16. Executing ABC pass (technology mapping using ABC). - -16.1. Extracting gate netlist of module `\counter' to `/input.blif'.. -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 5 unused wires. - - -3.10. Executing MEMORY_COLLECT pass (generating $mem cells). - -3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). -Extracted 6 gates and 11 wires to a netlist network with 4 inputs and 2 outputs. - -16.1.1. Executing ABC. -Mapping memory \mem in module \memdemo: - created 4 $dff cells and 0 static cells of width 4. -Extracted data FF from read port 0 of memdemo.mem: $\mem$rdreg[0] - read interface: 1 $dff and 3 $mux cells. - write interface: 12 write mux blocks. - -4. Executing OPT pass (performing simple optimizations). +Writing dot description to `macc_xilinx_test2e.dot'. +Dumping module test2 to page 1. -4.1. Executing OPT_EXPR pass (perform const folding). +23. Generating Graphviz representation of design. Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 4 unused wires. 2.7.7. Executing OPT_EXPR pass (perform const folding). +Writing dot description to `macc_xilinx_xmap.dot'. +Dumping module DSP48_MACC to page 1. + +End of script. Logfile hash: 750c951a95, CPU: user 0.23s system 0.01s, MEM: 10.61 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 42% 12x clean (0 sec), 16% 5x techmap (0 sec), ... Optimizing module memdemo. 2.7.8. Rerunning OPT passes. (Maybe there is more to do..) @@ -33871,40 +33318,26 @@ Performed a total of 0 changes. 2.7.11. Executing OPT_MERGE pass (detect identical cells). +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/macc' Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module memdemo. - - -4.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. - -4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \memdemo.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. -Performed a total of 0 changes. - -4.5. Executing OPT_MERGE pass (detect identical cells). Finding unused cells or wires in module \memdemo.. 2.7.13. Executing OPT_EXPR pass (perform const folding). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. - -4.6. Executing OPT_DFF pass (perform DFF optimizations). Optimizing module memdemo. -4.7. Executing OPT_CLEAN pass (remove unused cells and wires). + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `example.ys' -- + +1. Executing Verilog-2005 frontend: example.v 2.7.14. Finished OPT passes. (There is nothing left to do.) @@ -33919,56 +33352,109 @@ Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$26 (mem). 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 28 unused wires. - +Parsing Verilog input from `example.v' to AST representation. +Generating RTLIL representation for module `\example'. +Successfully finished Verilog frontend. -4.8. Executing OPT_EXPR pass (perform const folding). +2. Generating Graphviz representation of design. +Writing dot description to `example_first.dot'. +Dumping module example to page 1. Finding unused cells or wires in module \memdemo.. 2.10. Executing MEMORY_COLLECT pass (generating $mem cells). +3. Executing PROC pass (convert processes to netlists). + +3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). + 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. +Removed a total of 0 dead cases. -4.9. Rerunning OPT passes. (Maybe there is more to do..) +3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. -4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \memdemo.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - +3.4. Executing PROC_INIT pass (extract init attributes). -4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. -Performed a total of 0 changes. +3.5. Executing PROC_ARST pass (detect async resets in processes). -4.12. Executing OPT_MERGE pass (detect identical cells). +3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\example.$proc$example.v:3$1'. + 1/1: $0\y[1:0] + +3.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.9. Executing PROC_DFF pass (convert process syncs to FFs). Optimizing module memdemo. 2.11.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +Creating register for signal `\example.\y' using process `\example.$proc$example.v:3$1'. + created $dff cell `$procdff$6' with positive edge clock. -4.13. Executing OPT_DFF pass (perform DFF optimizations). +3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\example.$proc$example.v:3$1'. +Removing empty process `example.$proc$example.v:3$1'. +Cleaned up 1 empty switch. + +3.12. Executing OPT_EXPR pass (perform const folding). Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_blif /input.blif +ABC: + read_lib -w /docs/source/code_examples/intro/mycells.lib +ABC: Parsing finished successfully. Parsing time = 0.00 sec +ABC: Warning: Templates are not defined. +ABC: Liberty parser cannot read "time_unit". Assuming time_unit : "1ns". +ABC: Liberty parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). +ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". +ABC: Library "demo" from "/docs/source/code_examples/intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec +ABC: Memory = 0.00 MB. Time = 0.00 sec +ABC: + strash +ABC: + &get -n +ABC: + &fraig -x +ABC: + &put +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + &get -n +ABC: + &dch -f +ABC: + &nf +ABC: + &put +ABC: + write_blif /output.blif -4.14. Executing OPT_CLEAN pass (remove unused cells and wires). +16.1.2. Re-integrating ABC results. +Optimizing module example. +ABC RESULTS: NAND cells: 4 +ABC RESULTS: NOR cells: 4 +ABC RESULTS: NOT cells: 3 +ABC RESULTS: internal signals: 5 +ABC RESULTS: input signals: 4 +ABC RESULTS: output signals: 2 +Removing temp directory. + +4. Generating Graphviz representation of design. Finding unused cells or wires in module \memdemo.. 2.11.4. Finished fast OPT passes. 2.12. Printing statistics. -Finding unused cells or wires in module \memdemo.. - -4.15. Executing OPT_EXPR pass (perform const folding). === memdemo === @@ -33999,11 +33485,25 @@ Performed a total of 0 transformations. 3.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). -Optimizing module memdemo. +Removed 0 unused cells and 10 unused wires. -4.16. Finished OPT passes. (There is nothing left to do.) +17. Generating Graphviz representation of design. -5. Generating Graphviz representation of design. +17.1. Executing Verilog-2005 frontend: mycells.v +Writing dot description to `example_second.dot'. +Dumping module example to page 1. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). +Parsing Verilog input from `mycells.v' to AST representation. +Generating RTLIL representation for module `\NOT'. +Generating RTLIL representation for module `\NAND'. +Generating RTLIL representation for module `\NOR'. +Generating RTLIL representation for module `\DFF'. +Successfully finished Verilog frontend. + +17.2. Continuing show pass. Performed a total of 6 transformations. 3.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). @@ -34016,14 +33516,22 @@ 3.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 3.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Writing dot description to `memdemo_00.dot'. -Dumping module memdemo to page 1. +Writing dot description to `counter_03.dot'. +Dumping module counter to page 1. -6. Generating Graphviz representation of design. -Writing dot description to `memdemo_01.dot'. -Dumping selected parts of module memdemo to page 1. +18. Executing Verilog backend. -7. Generating Graphviz representation of design. +18.1. Executing BMUXMAP pass. + +18.2. Executing DEMUXMAP pass. +Optimizing module example. + +5.2. Executing OPT_MERGE pass (detect identical cells). +Dumping module `\counter'. + +End of script. Logfile hash: 22b20c9afa, CPU: user 0.21s system 0.01s, MEM: 12.57 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 46% 1x abc (0 sec), 13% 13x opt_expr (0 sec), ... Checking read port `\mem'[0] in module `\memdemo': merging output FF to cell. Write port 0: non-transparent. Write port 1: non-transparent. @@ -34040,15 +33548,36 @@ Checking read port address `\mem'[4] in module `\memdemo': no address FF found. 3.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding identical cells in module `\example'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \example.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $ternary$example.v:5$3. +Removed 1 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \example. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\example'. +Removed a total of 0 cells. + +5.6. Executing OPT_DFF pass (perform DFF optimizations). Finding unused cells or wires in module \memdemo.. Removed 1 unused cells and 5 unused wires. -Writing dot description to `memdemo_02.dot'. -Dumping selected parts of module memdemo to page 1. +../../../../yosys counter.ys 3.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Adding EN signal on $procdff$6 ($dff) from module example (D = $ternary$example.v:5$3_Y, Q = \y). -8. Generating Graphviz representation of design. +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Consolidating read ports of memory memdemo.mem by address: Merging ports 1, 4 (address 2'00). Merging ports 2, 3 (address 2'11). @@ -34064,10 +33593,6 @@ Performed a total of 0 transformations. 3.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Writing dot description to `memdemo_03.dot'. -Dumping selected parts of module memdemo to page 1. - -9. Generating Graphviz representation of design. Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 5 unused wires. @@ -34075,8 +33600,11 @@ 3.10. Executing MEMORY_COLLECT pass (generating $mem cells). 3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). -Writing dot description to `memdemo_04.dot'. -Dumping selected parts of module memdemo to page 1. +Finding unused cells or wires in module \example.. +Removed 1 unused cells and 4 unused wires. + + +5.8. Executing OPT_EXPR pass (perform const folding). Mapping memory \mem in module \memdemo: created 4 $dff cells and 0 static cells of width 4. Extracted data FF from read port 0 of memdemo.mem: $\mem$rdreg[0] @@ -34085,47 +33613,22 @@ 4. Executing OPT pass (performing simple optimizations). -10. Generating Graphviz representation of design. - 4.1. Executing OPT_EXPR pass (perform const folding). -Writing dot description to `memdemo_05.dot'. -Dumping selected parts of module memdemo to page 1. - -End of script. Logfile hash: ade9f67caf, CPU: user 0.15s system 0.00s, MEM: 10.37 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 23% 9x opt_expr (0 sec), 22% 9x opt_clean (0 sec), ... -Optimizing module memdemo. - +Optimizing module example. -4.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +5.9. Rerunning OPT passes. (Maybe there is more to do..) -4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -../../../../yosys submod.ys -Running muxtree optimizer on module \memdemo.. +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \example.. Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. + No muxes found in this module. Removed 0 multiplexer ports. - -4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \example. Performed a total of 0 changes. -4.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. - -4.6. Executing OPT_DFF pass (perform DFF optimizations). - -4.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 28 unused wires. - - -4.8. Executing OPT_EXPR pass (perform const folding). +5.12. Executing OPT_MERGE pass (detect identical cells). /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -34134,239 +33637,429 @@ \----------------------------------------------------------------------------/ Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) --- Executing script file `submod.ys' -- - -1. Executing Verilog-2005 frontend: memdemo.v -Optimizing module memdemo. - -4.9. Rerunning OPT passes. (Maybe there is more to do..) - -4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \memdemo.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. -Performed a total of 0 changes. +-- Executing script file `counter.ys' -- -4.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. +1. Executing Verilog-2005 frontend: counter.v +Finding identical cells in module `\example'. Removed a total of 0 cells. -4.13. Executing OPT_DFF pass (perform DFF optimizations). -Parsing Verilog input from `memdemo.v' to AST representation. -Generating RTLIL representation for module `\memdemo'. +5.13. Executing OPT_DFF pass (perform DFF optimizations). +Parsing Verilog input from `counter.v' to AST representation. +Generating RTLIL representation for module `\counter'. Successfully finished Verilog frontend. -2. Executing PREP pass. - -2.1. Executing HIERARCHY pass (managing design hierarchy). +2. Executing HIERARCHY pass (managing design hierarchy). -2.1.1. Analyzing design hierarchy.. -Top module: \memdemo +2.1. Analyzing design hierarchy.. +Top module: \counter -2.1.2. Analyzing design hierarchy.. -Top module: \memdemo +2.2. Analyzing design hierarchy.. +Top module: \counter Removed 0 unused modules. -2.2. Executing PROC pass (convert processes to netlists). +3. Generating Graphviz representation of design. +Optimizing module memdemo. + -2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +4.2. Executing OPT_MERGE pass (detect identical cells). +Writing dot description to `counter_00.dot'. +Dumping module counter to page 1. + +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). + +4. Executing PROC pass (convert processes to netlists). + +4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. -2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. + +4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Marked 1 switch rules as full_case in process $proc$counter.v:6$1 in module counter. Removed a total of 0 dead cases. -2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. -Promoted 14 assignments to connections. +Promoted 0 assignments to connections. -2.2.4. Executing PROC_INIT pass (extract init attributes). +4.4. Executing PROC_INIT pass (extract init attributes). -2.2.5. Executing PROC_ARST pass (detect async resets in processes). +4.5. Executing PROC_ARST pass (detect async resets in processes). -2.2.6. Executing PROC_ROM pass (convert switches to ROMs). +4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. + -2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\memdemo.$proc$memdemo.v:11$7'. +4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Running muxtree optimizer on module \memdemo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + -2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Creating decoders for process `\counter.$proc$counter.v:6$1'. + 1/1: $0\count[1:0] + +4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + Optimizing cells in module \memdemo. +Performed a total of 0 changes. + +4.5. Executing OPT_MERGE pass (detect identical cells). + +4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\counter.\count' using process `\counter.$proc$counter.v:6$1'. + created $dff cell `$procdff$8' with positive edge clock. + +4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 2 empty switches in `\counter.$proc$counter.v:6$1'. +Removing empty process `counter.$proc$counter.v:6$1'. +Cleaned up 2 empty switches. + +4.12. Executing OPT_EXPR pass (perform const folding). +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. + +4.6. Executing OPT_DFF pass (perform DFF optimizations). +Finding unused cells or wires in module \example.. + +5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module counter. + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). + +4.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Optimizing module example. + +5.16. Finished OPT passes. (There is nothing left to do.) +Optimizing module counter. + +6. Generating Graphviz representation of design. + +5.2. Executing OPT_MERGE pass (detect identical cells). +Finding unused cells or wires in module \memdemo.. +Removed 0 unused cells and 28 unused wires. + + +4.8. Executing OPT_EXPR pass (perform const folding). +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. +Performed a total of 0 changes. + +5.5. Executing OPT_MERGE pass (detect identical cells). +Writing dot description to `example_third.dot'. +Dumping module example to page 1. + +End of script. Logfile hash: 1968fcbfd1, CPU: user 0.05s system 0.00s, MEM: 8.88 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 35% 4x opt_expr (0 sec), 16% 3x show (0 sec), ... +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +5.6. Executing OPT_DFF pass (perform DFF optimizations). +Optimizing module memdemo. + +4.9. Rerunning OPT passes. (Maybe there is more to do..) +Adding SRST signal on $procdff$8 ($dff) from module counter (D = $procmux$3_Y, Q = \count, rval = 2'00). +Adding EN signal on $auto$ff.cc:266:slice$9 ($sdff) from module counter (D = $add$counter.v:10$2_Y, Q = \count). + +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memdemo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memdemo. +Performed a total of 0 changes. + +4.12. Executing OPT_MERGE pass (detect identical cells). +../../../../yosys example.ys +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. + +4.13. Executing OPT_DFF pass (perform DFF optimizations). +Finding unused cells or wires in module \counter.. +Removed 2 unused cells and 5 unused wires. + + +5.8. Executing OPT_EXPR pass (perform const folding). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Optimizing module counter. -2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\memdemo.\y' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$35' with positive edge clock. -Creating register for signal `\memdemo.\i' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$36' with positive edge clock. -Creating register for signal `\memdemo.\s1' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$37' with positive edge clock. -Creating register for signal `\memdemo.\s2' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$38' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$39' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$40' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$41' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$42' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$43' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$44' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$45' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$46' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_ADDR' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$47' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$48' with positive edge clock. -Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_EN' using process `\memdemo.$proc$memdemo.v:11$7'. - created $dff cell `$procdff$49' with positive edge clock. +5.9. Rerunning OPT passes. (Maybe there is more to do..) -2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. -2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `memdemo.$proc$memdemo.v:11$7'. -Cleaned up 0 empty switches. +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. +Performed a total of 0 changes. -2.2.12. Executing OPT_EXPR pass (perform const folding). +5.12. Executing OPT_MERGE pass (detect identical cells). Finding unused cells or wires in module \memdemo.. 4.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. +Finding identical cells in module `\counter'. +Removed a total of 0 cells. -2.3. Executing FUTURE pass. +5.13. Executing OPT_DFF pass (perform DFF optimizations). + +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \counter.. + +5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module memdemo. 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. +Optimizing module counter. -2.4. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. +5.16. Finished OPT passes. (There is nothing left to do.) + +6. Executing MEMORY pass. + +6.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +6.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Writing dot description to `memdemo_00.dot'. Dumping module memdemo to page 1. -2.5. Executing OPT_CLEAN pass (remove unused cells and wires). - 6. Generating Graphviz representation of design. +Performed a total of 0 transformations. + +6.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +6.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +6.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `example.ys' -- + +1. Executing Verilog-2005 frontend: example.v + +6.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Parsing Verilog input from `example.v' to AST representation. +Generating RTLIL representation for module `\example'. +Successfully finished Verilog frontend. + +2. Generating Graphviz representation of design. +make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/stubnets' +make[6]: Nothing to be done for 'dots'. +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/stubnets' Writing dot description to `memdemo_01.dot'. Dumping selected parts of module memdemo to page 1. 7. Generating Graphviz representation of design. -Finding unused cells or wires in module \memdemo.. -Removed 12 unused cells and 26 unused wires. - +Finding unused cells or wires in module \counter.. -2.6. Executing CHECK pass (checking for obvious problems). -Checking module memdemo... -Found and reported 0 problems. +6.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Writing dot description to `example_first.dot'. +Dumping module example to page 1. -2.7. Executing OPT pass (performing simple optimizations). +6.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. -2.7.1. Executing OPT_EXPR pass (perform const folding). +6.9. Executing OPT_CLEAN pass (remove unused cells and wires). + +3. Executing PROC pass (convert processes to netlists). + +3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Writing dot description to `memdemo_02.dot'. Dumping selected parts of module memdemo to page 1. +Removed a total of 0 dead cases. + +3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 8. Generating Graphviz representation of design. -Optimizing module memdemo. +Removed 0 redundant assignments. +Promoted 0 assignments to connections. -2.7.2. Executing OPT_MERGE pass (detect identical cells). +3.4. Executing PROC_INIT pass (extract init attributes). + +3.5. Executing PROC_ARST pass (detect async resets in processes). + +3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Finding unused cells or wires in module \counter.. + +6.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +6.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +7. Executing OPT pass (performing simple optimizations). + +7.1. Executing OPT_EXPR pass (perform const folding). +Creating decoders for process `\example.$proc$example.v:3$1'. + 1/1: $0\y[1:0] + +3.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\example.\y' using process `\example.$proc$example.v:3$1'. + created $dff cell `$procdff$6' with positive edge clock. + +3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\example.$proc$example.v:3$1'. +Removing empty process `example.$proc$example.v:3$1'. +Cleaned up 1 empty switch. + +3.12. Executing OPT_EXPR pass (perform const folding). Writing dot description to `memdemo_03.dot'. Dumping selected parts of module memdemo to page 1. -Finding identical cells in module `\memdemo'. - -Removed a total of 4 cells. - -2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 9. Generating Graphviz representation of design. -Running muxtree optimizer on module \memdemo.. +Optimizing module counter. + +7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. + No muxes found in this module. Removed 0 multiplexer ports. - -2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. +7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. Performed a total of 0 changes. -2.7.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. +7.5. Executing OPT_MERGE pass (detect identical cells). +Optimizing module example. +Finding identical cells in module `\counter'. Removed a total of 0 cells. -2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). +7.6. Executing OPT_DFF pass (perform DFF optimizations). Writing dot description to `memdemo_04.dot'. Dumping selected parts of module memdemo to page 1. +4. Generating Graphviz representation of design. + 10. Generating Graphviz representation of design. -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 4 unused wires. - -2.7.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. +7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Writing dot description to `example_second.dot'. +Dumping module example to page 1. +make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' +../../../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format dot' -2.7.8. Rerunning OPT passes. (Maybe there is more to do..) +5. Executing OPT pass (performing simple optimizations). +Finding unused cells or wires in module \counter.. -2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \memdemo.. +7.8. Executing OPT_EXPR pass (perform const folding). + +5.1. Executing OPT_EXPR pass (perform const folding). +Writing dot description to `memdemo_05.dot'. +Dumping selected parts of module memdemo to page 1. + +End of script. Logfile hash: ade9f67caf, CPU: user 0.15s system 0.01s, MEM: 10.36 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 23% 9x opt_expr (0 sec), 22% 9x opt_clean (0 sec), ... +Optimizing module counter. + +7.9. Finished OPT passes. (There is nothing left to do.) + +8. Executing FSM pass (extract and optimize FSM). + +8.1. Executing FSM_DETECT pass (finding FSMs in design). +Optimizing module example. + +5.2. Executing OPT_MERGE pass (detect identical cells). + +8.2. Executing FSM_EXTRACT pass (extracting FSM from design). +../../../../yosys memdemo.ys + +8.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +8.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding identical cells in module `\example'. +Removed a total of 0 cells. + +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \example.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. -Removed 0 multiplexer ports. + dead port 2/2 on $mux $ternary$example.v:5$3. +Removed 1 multiplexer ports. -2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \example. Performed a total of 0 changes. -2.7.11. Executing OPT_MERGE pass (detect identical cells). -Writing dot description to `memdemo_05.dot'. -Dumping selected parts of module memdemo to page 1. +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding unused cells or wires in module \counter.. -End of script. Logfile hash: ade9f67caf, CPU: user 0.15s system 0.00s, MEM: 10.37 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 23% 9x opt_expr (0 sec), 22% 9x opt_clean (0 sec), ... -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +8.5. Executing FSM_OPT pass (simple optimizations of FSMs). -2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -../../../../yosys submod.ys +8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). -2.7.13. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. +8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). -2.7.14. Finished OPT passes. (There is nothing left to do.) +8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). -2.8. Executing WREDUCE pass (reducing word size of cells). -Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$50 (mem). -Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$51 (mem). -Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$52 (mem). -Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$53 (mem). -Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$19 (mem). -Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$20 (mem). -Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$23 (mem). -Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$26 (mem). +9. Executing OPT pass (performing simple optimizations). -2.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. +9.1. Executing OPT_EXPR pass (perform const folding). +Finding identical cells in module `\example'. +Removed a total of 0 cells. -2.10. Executing MEMORY_COLLECT pass (generating $mem cells). +5.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $procdff$6 ($dff) from module example (D = $ternary$example.v:5$3_Y, Q = \y). -2.11. Executing OPT pass (performing simple optimizations). +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Optimizing module counter. -2.11.1. Executing OPT_EXPR pass (perform const folding). +9.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -34375,63 +34068,131 @@ \----------------------------------------------------------------------------/ Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) --- Executing script file `submod.ys' -- +-- Running command `script proc_01.ys; show -notitle -prefix proc_01 -format dot' -- -1. Executing Verilog-2005 frontend: memdemo.v -Optimizing module memdemo. +-- Executing script file `proc_01.ys' -- -2.11.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. +1. Executing Verilog-2005 frontend: proc_01.v +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. +Performed a total of 0 changes. + +9.5. Executing OPT_MERGE pass (detect identical cells). +Parsing Verilog input from `proc_01.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. +Top module: \test + +2.2. Analyzing design hierarchy.. +Top module: \test +Removed 0 unused modules. + +3. Executing PROC pass (convert processes to netlists). + +3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$proc_01.v:2$1 in module test. +Removed a total of 0 dead cases. + +3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 1 redundant assignment. +Promoted 0 assignments to connections. + +3.4. Executing PROC_INIT pass (extract init attributes). + +3.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \R in `\test.$proc$proc_01.v:2$1'. + +3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\test.$proc$proc_01.v:2$1'. + 1/1: $0\Q[0:0] + +3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +Finding identical cells in module `\counter'. Removed a total of 0 cells. -2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. +9.6. Executing OPT_DFF pass (perform DFF optimizations). -2.11.4. Finished fast OPT passes. +3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Finding unused cells or wires in module \example.. +Removed 1 unused cells and 4 unused wires. + -2.12. Printing statistics. +5.8. Executing OPT_EXPR pass (perform const folding). +Creating register for signal `\test.\Q' using process `\test.$proc$proc_01.v:2$1'. + created $adff cell `$procdff$4' with positive edge clock and positive level reset. -=== memdemo === +3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - Number of wires: 18 - Number of wire bits: 58 - Number of public wires: 5 - Number of public wire bits: 13 - Number of ports: 3 - Number of port bits: 9 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 11 - $add 4 - $dff 3 - $mem_v2 1 - $mux 1 - $reduce_bool 1 - $xor 1 +3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `test.$proc$proc_01.v:2$1'. +Cleaned up 0 empty switches. -2.13. Executing CHECK pass (checking for obvious problems). +3.12. Executing OPT_EXPR pass (perform const folding). + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `memdemo.ys' -- + +1. Executing Verilog-2005 frontend: memdemo.v + +9.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \counter.. + +9.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module test. + +Optimizing module example. + +5.9. Rerunning OPT passes. (Maybe there is more to do..) + +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \example.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \example. +Performed a total of 0 changes. + +5.12. Executing OPT_MERGE pass (detect identical cells). +Optimizing module counter. Parsing Verilog input from `memdemo.v' to AST representation. Generating RTLIL representation for module `\memdemo'. Successfully finished Verilog frontend. 2. Executing PREP pass. -Checking module memdemo... -Found and reported 0 problems. - -3. Executing MEMORY pass. - -3.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. - -3.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 2.1. Executing HIERARCHY pass (managing design hierarchy). 2.1.1. Analyzing design hierarchy.. + +9.9. Finished OPT passes. (There is nothing left to do.) Top module: \memdemo 2.1.2. Analyzing design hierarchy.. + +10. Generating Graphviz representation of design. Top module: \memdemo Removed 0 unused modules. @@ -34458,20 +34219,23 @@ Creating decoders for process `\memdemo.$proc$memdemo.v:11$7'. 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +Removed 0 unused cells and 2 unused wires. -2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -Performed a total of 6 transformations. +4. Generating Graphviz representation of design. +Finding identical cells in module `\example'. +Removed a total of 0 cells. -3.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). - Analyzing memdemo.mem write port 0. - Analyzing memdemo.mem write port 1. - Analyzing memdemo.mem write port 2. - Analyzing memdemo.mem write port 3. - Analyzing memdemo.mem write port 4. +5.13. Executing OPT_DFF pass (perform DFF optimizations). -3.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). +2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Writing dot description to `counter_01.dot'. +Dumping module counter to page 1. -3.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +11. Executing TECHMAP pass (map to technology primitives). + +11.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v +Writing dot description to `proc_01.dot'. +Dumping module test to page 1. Creating register for signal `\memdemo.\y' using process `\memdemo.$proc$memdemo.v:11$7'. created $dff cell `$procdff$35' with positive edge clock. Creating register for signal `\memdemo.\i' using process `\memdemo.$proc$memdemo.v:11$7'. @@ -34505,140 +34269,120 @@ 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +End of script. Logfile hash: 4fe5064e83, CPU: user 0.02s system 0.00s, MEM: 8.82 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 31% 1x opt_expr (0 sec), 26% 1x clean (0 sec), ... + 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `memdemo.$proc$memdemo.v:11$7'. Cleaned up 0 empty switches. 2.2.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. -Checking read port `\mem'[0] in module `\memdemo': merging output FF to cell. - Write port 0: non-transparent. - Write port 1: non-transparent. - Write port 2: non-transparent. - Write port 3: non-transparent. - Write port 4: non-transparent. -Checking read port `\mem'[1] in module `\memdemo': no output FF found. -Checking read port `\mem'[2] in module `\memdemo': no output FF found. -Checking read port `\mem'[3] in module `\memdemo': no output FF found. -Checking read port `\mem'[4] in module `\memdemo': no output FF found. -Checking read port address `\mem'[1] in module `\memdemo': no address FF found. -Checking read port address `\mem'[2] in module `\memdemo': no address FF found. -Checking read port address `\mem'[3] in module `\memdemo': no address FF found. -Checking read port address `\mem'[4] in module `\memdemo': no address FF found. -3.6. Executing OPT_CLEAN pass (remove unused cells and wires). +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +../../../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format dot' +Optimizing module memdemo. 2.3. Executing FUTURE pass. -Finding unused cells or wires in module \memdemo.. -Removed 1 unused cells and 5 unused wires. - +Finding unused cells or wires in module \example.. -3.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +5.15. Executing OPT_EXPR pass (perform const folding). 2.4. Executing OPT_EXPR pass (perform const folding). -Consolidating read ports of memory memdemo.mem by address: - Merging ports 1, 4 (address 2'00). - Merging ports 2, 3 (address 2'11). -Consolidating read ports of memory memdemo.mem by address: - Merging ports 1, 2 (address 2'00). -Consolidating read ports of memory memdemo.mem by address: -Consolidating write ports of memory memdemo.mem by address: - Merging ports 0, 1 (address 2'00). - Merging ports 0, 2 (address 2'00). -Consolidating write ports of memory memdemo.mem by address: +Optimizing module example. -3.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). -Optimizing module memdemo. -Performed a total of 0 transformations. +5.16. Finished OPT passes. (There is nothing left to do.) -3.9. Executing OPT_CLEAN pass (remove unused cells and wires). +6. Generating Graphviz representation of design. +Optimizing module memdemo. 2.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 5 unused wires. - - -3.10. Executing MEMORY_COLLECT pass (generating $mem cells). - -3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). -Mapping memory \mem in module \memdemo: - created 4 $dff cells and 0 static cells of width 4. -Extracted data FF from read port 0 of memdemo.mem: $\mem$rdreg[0] - read interface: 1 $dff and 3 $mux cells. - write interface: 12 write mux blocks. - -4. Executing OPT pass (performing simple optimizations). +Writing dot description to `example_third.dot'. +Dumping module example to page 1. -4.1. Executing OPT_EXPR pass (perform const folding). +End of script. Logfile hash: 1968fcbfd1, CPU: user 0.05s system 0.00s, MEM: 8.88 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 36% 4x opt_expr (0 sec), 16% 3x show (0 sec), ... +../../../../yosys cmos.ys Finding unused cells or wires in module \memdemo.. Removed 12 unused cells and 26 unused wires. 2.6. Executing CHECK pass (checking for obvious problems). + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Running command `script proc_02.ys; show -notitle -prefix proc_02 -format dot' -- + +-- Executing script file `proc_02.ys' -- + +1. Executing Verilog-2005 frontend: proc_02.v Checking module memdemo... Found and reported 0 problems. 2.7. Executing OPT pass (performing simple optimizations). 2.7.1. Executing OPT_EXPR pass (perform const folding). -Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 -ABC: ABC command line: "source /abc.script". -ABC: -ABC: + read_blif /input.blif -ABC: + read_lib -w /docs/source/code_examples/intro/mycells.lib -ABC: Parsing finished successfully. Parsing time = 0.00 sec -ABC: Warning: Templates are not defined. -ABC: Liberty parser cannot read "time_unit". Assuming time_unit : "1ns". -ABC: Liberty parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). -ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". -ABC: Library "demo" from "/docs/source/code_examples/intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec -ABC: Memory = 0.00 MB. Time = 0.00 sec -ABC: + strash -ABC: + &get -n -ABC: + &fraig -x -ABC: + &put -ABC: + scorr -ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). -ABC: + dc2 -ABC: + dretime -ABC: + strash -ABC: + &get -n -ABC: + &dch -f -ABC: + &nf -ABC: + &put -ABC: + write_blif /output.blif +Parsing Verilog input from `proc_02.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. -16.1.2. Re-integrating ABC results. -Optimizing module memdemo. - +2. Executing HIERARCHY pass (managing design hierarchy). -4.2. Executing OPT_MERGE pass (detect identical cells). -Optimizing module memdemo. +2.1. Analyzing design hierarchy.. +Top module: \test -2.7.2. Executing OPT_MERGE pass (detect identical cells). -ABC RESULTS: NAND cells: 4 -ABC RESULTS: NOR cells: 4 -ABC RESULTS: NOT cells: 3 -ABC RESULTS: internal signals: 5 -ABC RESULTS: input signals: 4 -ABC RESULTS: output signals: 2 -Removing temp directory. -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +2.2. Analyzing design hierarchy.. +Top module: \test +Removed 0 unused modules. -4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \memdemo.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - +3. Executing PROC pass (convert processes to netlists). -4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. -Performed a total of 0 changes. +3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. -4.5. Executing OPT_MERGE pass (detect identical cells). +3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$proc_02.v:3$1 in module test. +Removed a total of 0 dead cases. + +3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 1 redundant assignment. +Promoted 0 assignments to connections. + +3.4. Executing PROC_INIT pass (extract init attributes). + +3.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \R in `\test.$proc$proc_02.v:3$1'. + +3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\test.$proc$proc_02.v:3$1'. + 1/1: $0\Q[0:0] + +3.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\test.\Q' using process `\test.$proc$proc_02.v:3$1'. +Warning: Async reset value `\RV' is not constant! + created $aldff cell `$procdff$4' with positive edge clock and positive level non-const reset. + +3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `test.$proc$proc_02.v:3$1'. +Cleaned up 0 empty switches. + +3.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module memdemo. + +2.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\memdemo'. Removed a total of 4 cells. @@ -34652,57 +34396,44 @@ 2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Optimizing module test. + Optimizing cells in module \memdemo. Performed a total of 0 changes. 2.7.5. Executing OPT_MERGE pass (detect identical cells). -Removed 0 unused cells and 10 unused wires. - -17. Generating Graphviz representation of design. -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. - -4.6. Executing OPT_DFF pass (perform DFF optimizations). - -17.1. Executing Verilog-2005 frontend: mycells.v Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Parsing Verilog input from `mycells.v' to AST representation. -Generating RTLIL representation for module `\NOT'. -Generating RTLIL representation for module `\NAND'. -Generating RTLIL representation for module `\NOR'. -Generating RTLIL representation for module `\DFF'. -Successfully finished Verilog frontend. - -17.2. Continuing show pass. - -4.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Writing dot description to `counter_03.dot'. -Dumping module counter to page 1. - -18. Executing Verilog backend. +Removed 0 unused cells and 2 unused wires. -18.1. Executing BMUXMAP pass. +4. Generating Graphviz representation of design. +Writing dot description to `proc_02.dot'. +Dumping module test to page 1. -18.2. Executing DEMUXMAP pass. +Warnings: 1 unique messages, 1 total +End of script. Logfile hash: c4b4f83334, CPU: user 0.02s system 0.00s, MEM: 8.88 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 32% 1x opt_expr (0 sec), 24% 1x clean (0 sec), ... Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 4 unused wires. 2.7.7. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 28 unused wires. - -4.8. Executing OPT_EXPR pass (perform const folding). -Dumping module `\counter'. + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -End of script. Logfile hash: 22b20c9afa, CPU: user 0.20s system 0.01s, MEM: 12.58 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 45% 1x abc (0 sec), 13% 13x opt_expr (0 sec), ... +-- Executing script file `cmos.ys' -- + +1. Executing Verilog-2005 frontend: cmos.v Optimizing module memdemo. +../../../../yosys -p 'script proc_03.ys; show -notitle -prefix proc_03 -format dot' 2.7.8. Rerunning OPT passes. (Maybe there is more to do..) @@ -34719,42 +34450,101 @@ Performed a total of 0 changes. 2.7.11. Executing OPT_MERGE pass (detect identical cells). -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' +Parsing Verilog input from `cmos.v' to AST representation. +Generating RTLIL representation for module `\cmos_demo'. +Successfully finished Verilog frontend. + +2. Executing PREP pass. + +2.1. Executing HIERARCHY pass (managing design hierarchy). + +2.1.1. Analyzing design hierarchy.. +Top module: \cmos_demo + +2.1.2. Analyzing design hierarchy.. +Top module: \cmos_demo +Removed 0 unused modules. + +2.2. Executing PROC pass (convert processes to netlists). + +2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +2.2.4. Executing PROC_INIT pass (extract init attributes). + +2.2.5. Executing PROC_ARST pass (detect async resets in processes). Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module memdemo. -4.9. Rerunning OPT passes. (Maybe there is more to do..) +2.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. -4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \memdemo.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - +2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \memdemo. -Performed a total of 0 changes. +2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). -4.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. -4.13. Executing OPT_DFF pass (perform DFF optimizations). +11.2. Continuing TECHMAP pass. + +2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.2.12. Executing OPT_EXPR pass (perform const folding). +Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Finding unused cells or wires in module \memdemo.. 2.7.13. Executing OPT_EXPR pass (perform const folding). - -4.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +Using extmapper simplemap for cells of type $sdffe. Optimizing module memdemo. +Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $and. +Optimizing module cmos_demo. 2.7.14. Finished OPT passes. (There is nothing left to do.) 2.8. Executing WREDUCE pass (reducing word size of cells). + +2.3. Executing FUTURE pass. Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$50 (mem). Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$51 (mem). Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$52 (mem). @@ -34765,9 +34555,8 @@ Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$26 (mem). 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -4.15. Executing OPT_EXPR pass (perform const folding). +2.4. Executing OPT_EXPR pass (perform const folding). Finding unused cells or wires in module \memdemo.. 2.10. Executing MEMORY_COLLECT pass (generating $mem cells). @@ -34775,16 +34564,91 @@ 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. -4.16. Finished OPT passes. (There is nothing left to do.) + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Running command `script proc_03.ys; show -notitle -prefix proc_03 -format dot' -- + +-- Executing script file `proc_03.ys' -- + +1. Executing Verilog-2005 frontend: proc_03.v +Optimizing module cmos_demo. + +2.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Parsing Verilog input from `proc_03.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. +Top module: \test + +2.2. Analyzing design hierarchy.. +Top module: \test +Removed 0 unused modules. + +3. Executing PROC pass (convert processes to netlists). + +3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +3.4. Executing PROC_INIT pass (extract init attributes). + +3.5. Executing PROC_ARST pass (detect async resets in processes). + +3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\test.$proc$proc_03.v:3$1'. + 1/1: $0\Y[0:0] + +3.8. Executing PROC_DLATCH pass (convert process syncs to latches). Optimizing module memdemo. 2.11.2. Executing OPT_MERGE pass (detect identical cells). +No latch inferred for signal `\test.\Y' from process `\test.$proc$proc_03.v:3$1'. + +3.9. Executing PROC_DFF pass (convert process syncs to FFs). + +3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 2 empty switches in `\test.$proc$proc_03.v:3$1'. +Removing empty process `test.$proc$proc_03.v:3$1'. +Cleaned up 2 empty switches. + +3.12. Executing OPT_EXPR pass (perform const folding). Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \cmos_demo.. +Removed 0 unused cells and 1 unused wires. + + +2.6. Executing CHECK pass (checking for obvious problems). +Checking module cmos_demo... +Found and reported 0 problems. + +2.7. Executing OPT pass (performing simple optimizations). +Optimizing module test. + +2.7.1. Executing OPT_EXPR pass (perform const folding). Finding unused cells or wires in module \memdemo.. 2.11.4. Finished fast OPT passes. @@ -34820,10 +34684,18 @@ Performed a total of 0 transformations. 3.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Removed 0 unused cells and 4 unused wires. -5. Executing SUBMOD pass (moving cells to submodules as requested). +4. Generating Graphviz representation of design. +Optimizing module cmos_demo. -5.1. Executing OPT_CLEAN pass (remove unused cells and wires). +2.7.2. Executing OPT_MERGE pass (detect identical cells). +Writing dot description to `proc_03.dot'. +Dumping module test to page 1. + +End of script. Logfile hash: 5a538b5f7f, CPU: user 0.01s system 0.01s, MEM: 8.94 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 26% 1x clean (0 sec), 24% 1x opt_expr (0 sec), ... Performed a total of 6 transformations. 3.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). @@ -34836,53 +34708,25 @@ 3.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 3.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Finding unused cells or wires in module \memdemo.. +Finding identical cells in module `\cmos_demo'. +Removed a total of 0 cells. -5.2. Continuing SUBMOD pass. -Creating submodule scramble (\scramble) of module \memdemo. - signal \clk: input \clk - signal \d: input \d - signal \mem[2]: output \mem[2] - signal $auto$rtlil.cc:2826:And$129: internal - signal $memory\mem$wrmux[1][2][0]$y$119: internal - signal \mem[1]: output \mem[1] - signal $auto$rtlil.cc:2826:And$141: internal - signal \mem[3]: output \mem[3] - signal $0$memwr$\mem$memdemo.v:13$2_DATA[3:0]$8: internal - signal $0$memwr$\mem$memdemo.v:13$3_DATA[3:0]$10: internal - signal $0$memwr$\mem$memdemo.v:13$4_DATA[3:0]$12: internal - signal $0$memwr$\mem$memdemo.v:13$5_DATA[3:0]$14: internal - signal $0$memwr$\mem$memdemo.v:15$6_ADDR[1:0]$16: input \n1 - signal $auto$rtlil.cc:2826:And$117: internal - signal $memory\mem$wrmux[3][2][0]$y$143: internal - signal $memory\mem$wrmux[2][2][0]$y$131: internal - signal $auto$rtlil.cc:2826:And$103: internal - signal $memory\mem$wrmux[0][2][0]$y$105: internal - signal $auto$rtlil.cc:2833:Eq$99: internal - signal \mem[0]: output \mem[0] - signal $auto$rtlil.cc:2833:Eq$101: internal - cell $memory\mem[3]$77 ($dff) - cell $memory\mem[2]$75 ($dff) - cell $memory\mem[1]$73 ($dff) - cell $memory\mem[0]$71 ($dff) - cell $memory\mem$wrmux[3][2][0]$142 ($mux) - cell $memory\mem$wrmux[2][2][0]$130 ($mux) - cell $memory\mem$wrmux[1][2][0]$118 ($mux) - cell $memory\mem$wrmux[0][2][0]$104 ($mux) - cell $auto$memory_map.cc:97:addr_decode$140 ($and) - cell $auto$memory_map.cc:97:addr_decode$128 ($and) - cell $auto$memory_map.cc:97:addr_decode$116 ($and) - cell $auto$memory_map.cc:97:addr_decode$102 ($and) - cell $auto$memory_map.cc:92:addr_decode$98 ($not) - cell $auto$memory_map.cc:92:addr_decode$100 ($not) - cell $add$memdemo.v:13$30 ($add) - cell $add$memdemo.v:13$27 ($add) - cell $add$memdemo.v:13$24 ($add) - cell $add$memdemo.v:13$21 ($add) +2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \cmos_demo.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. -6. Executing SUBMOD pass (moving cells to submodules as requested). +2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \cmos_demo. +Performed a total of 0 changes. -6.1. Executing OPT_CLEAN pass (remove unused cells and wires). +2.7.5. Executing OPT_MERGE pass (detect identical cells). +../../../../yosys -p 'script memory_01.ys; show -notitle -prefix memory_01 -format dot' +Finding identical cells in module `\cmos_demo'. +Removed a total of 0 cells. + +2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). Checking read port `\mem'[0] in module `\memdemo': merging output FF to cell. Write port 0: non-transparent. Write port 1: non-transparent. @@ -34899,37 +34743,21 @@ Checking read port address `\mem'[4] in module `\memdemo': no address FF found. 3.6. Executing OPT_CLEAN pass (remove unused cells and wires). -make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/show' -../../../../yosys -p 'prep -top splice_demo; show -format dot -prefix splice' splice.v -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 14 unused wires. - - -6.2. Continuing SUBMOD pass. -Creating submodule outstage (\outstage) of module \memdemo. - signal \clk: input \clk - signal \mem[2]: input \mem[2] - signal $\mem$rdreg[0]$d: internal - signal $memory\mem$rdmux[0][0][0]$a$80: internal - signal \mem[1]: input \mem[1] - signal \y: output \y - signal \mem[3]: input \mem[3] - signal $0\s2[1:0]: input \n1 - signal \mem[0]: input \mem[0] - signal $memory\mem$rdmux[0][0][0]$b$81: internal - cell $memory\mem$rdmux[0][1][1]$85 ($mux) - cell $memory\mem$rdmux[0][1][0]$82 ($mux) - cell $memory\mem$rdmux[0][0][0]$79 ($mux) - cell $\mem$rdreg[0] ($dff) +Finding unused cells or wires in module \cmos_demo.. -7. Executing SUBMOD pass (moving cells to submodules as requested). +2.7.7. Executing OPT_EXPR pass (perform const folding). Finding unused cells or wires in module \memdemo.. Removed 1 unused cells and 5 unused wires. 3.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Optimizing module cmos_demo. -7.1. Executing OPT_CLEAN pass (remove unused cells and wires). +2.7.8. Finished OPT passes. (There is nothing left to do.) + +2.8. Executing WREDUCE pass (reducing word size of cells). + +2.9. Executing OPT_CLEAN pass (remove unused cells and wires). Consolidating read ports of memory memdemo.mem by address: Merging ports 1, 4 (address 2'00). Merging ports 2, 3 (address 2'11). @@ -34945,24 +34773,24 @@ Performed a total of 0 transformations. 3.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 3 unused wires. - +Finding unused cells or wires in module \cmos_demo.. -7.2. Continuing SUBMOD pass. -Creating submodule selstage (\selstage) of module \memdemo. - signal \d: input \d - signal \s1: input \s1 - signal \s2: input \s2 - signal $0\s2[1:0]: output \n1 - signal $0$memwr$\mem$memdemo.v:15$6_ADDR[1:0]$16: output \n2 - signal $xor$memdemo.v:14$31_Y: internal - signal $reduce_bool$memdemo.v:14$32_Y: internal - cell $xor$memdemo.v:14$31 ($xor) - cell $ternary$memdemo.v:14$33 ($mux) - cell $reduce_bool$memdemo.v:14$32 ($reduce_bool) +2.10. Executing MEMORY_COLLECT pass (generating $mem cells). -8. Generating Graphviz representation of design. +2.11. Executing OPT pass (performing simple optimizations). + +2.11.1. Executing OPT_EXPR pass (perform const folding). +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $or. +No more expansions possible. + + +12. Executing OPT pass (performing simple optimizations). + +12.1. Executing OPT_EXPR pass (perform const folding). Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 5 unused wires. @@ -34970,8 +34798,6 @@ 3.10. Executing MEMORY_COLLECT pass (generating $mem cells). 3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). -Writing dot description to `submod_00.dot'. -Dumping module memdemo to page 1. Mapping memory \mem in module \memdemo: created 4 $dff cells and 0 static cells of width 4. Extracted data FF from read port 0 of memdemo.mem: $\mem$rdreg[0] @@ -34981,8 +34807,9 @@ 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module cmos_demo. -9. Generating Graphviz representation of design. +2.11.2. Executing OPT_MERGE pass (detect identical cells). /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -34991,82 +34818,127 @@ \----------------------------------------------------------------------------/ Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) --- Parsing `splice.v' using frontend ` -vlog2k' -- - -1. Executing Verilog-2005 frontend: splice.v -Writing dot description to `submod_01.dot'. -Dumping module scramble to page 1. -Parsing Verilog input from `splice.v' to AST representation. -Storing AST representation for module `$abstract\splice_demo'. -Successfully finished Verilog frontend. - --- Running command `prep -top splice_demo; show -format dot -prefix splice' -- +-- Running command `script memory_01.ys; show -notitle -prefix memory_01 -format dot' -- -2. Executing PREP pass. +-- Executing script file `memory_01.ys' -- -2.1. Executing HIERARCHY pass (managing design hierarchy). +1. Executing Verilog-2005 frontend: memory_01.v +Finding identical cells in module `\cmos_demo'. +Removed a total of 0 cells. -2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\splice_demo'. +2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Parsing Verilog input from `memory_01.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. -10. Generating Graphviz representation of design. -Generating RTLIL representation for module `\splice_demo'. +2. Executing HIERARCHY pass (managing design hierarchy). -2.2.1. Analyzing design hierarchy.. -Top module: \splice_demo +2.1. Analyzing design hierarchy.. +Top module: \test -2.2.2. Analyzing design hierarchy.. -Top module: \splice_demo -Removing unused module `$abstract\splice_demo'. -Removed 1 unused modules. +2.2. Analyzing design hierarchy.. +Top module: \test +Removed 0 unused modules. -2.3. Executing PROC pass (convert processes to netlists). +3. Executing PROC pass (convert processes to netlists). -2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. -2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. -2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. -Promoted 0 assignments to connections. +Promoted 4 assignments to connections. -2.3.4. Executing PROC_INIT pass (extract init attributes). +3.4. Executing PROC_INIT pass (extract init attributes). -2.3.5. Executing PROC_ARST pass (detect async resets in processes). +3.5. Executing PROC_ARST pass (detect async resets in processes). -2.3.6. Executing PROC_ROM pass (convert switches to ROMs). +3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. -2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\test.$proc$memory_01.v:5$2'. -2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +Optimizing module counter. + -2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Writing dot description to `submod_02.dot'. -Dumping module outstage to page 1. +12.2. Executing OPT_MERGE pass (detect identical cells). -11. Generating Graphviz representation of design. +3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\test.\DOUT' using process `\test.$proc$memory_01.v:5$2'. + created $dff cell `$procdff$7' with positive edge clock. +Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_ADDR' using process `\test.$proc$memory_01.v:5$2'. + created $dff cell `$procdff$8' with positive edge clock. +Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_DATA' using process `\test.$proc$memory_01.v:5$2'. + created $dff cell `$procdff$9' with positive edge clock. +Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_EN' using process `\test.$proc$memory_01.v:5$2'. + created $dff cell `$procdff$10' with positive edge clock. -2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `test.$proc$memory_01.v:5$2'. Cleaned up 0 empty switches. -2.3.12. Executing OPT_EXPR pass (perform const folding). +3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module memdemo. +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 4.2. Executing OPT_MERGE pass (detect identical cells). -Writing dot description to `submod_03.dot'. -Dumping module selstage to page 1. -Optimizing module splice_demo. +Running muxtree optimizer on module \counter.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. -2.4. Executing FUTURE pass. +12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Finding unused cells or wires in module \cmos_demo.. + +2.11.4. Finished fast OPT passes. + Optimizing cells in module \counter. +Performed a total of 0 changes. + +12.5. Executing OPT_MERGE pass (detect identical cells). + +2.12. Printing statistics. + +=== cmos_demo === + + Number of wires: 3 + Number of wire bits: 4 + Number of public wires: 3 + Number of public wire bits: 4 + Number of ports: 3 + Number of port bits: 4 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1 + $add 1 + +2.13. Executing CHECK pass (checking for obvious problems). +Checking module cmos_demo... +Found and reported 0 problems. + +3. Executing TECHMAP pass (map to technology primitives). +Optimizing module test. Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). + +3.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +12.6. Executing OPT_DFF pass (perform DFF optimizations). Running muxtree optimizer on module \memdemo.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. @@ -35080,63 +34952,79 @@ 4.5. Executing OPT_MERGE pass (detect identical cells). -End of script. Logfile hash: ff5e3e9659, CPU: user 0.16s system 0.00s, MEM: 10.37 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 27% 12x opt_clean (0 sec), 21% 9x opt_expr (0 sec), ... - -2.5. Executing OPT_EXPR pass (perform const folding). +12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 4.6. Executing OPT_DFF pass (perform DFF optimizations). -Optimizing module splice_demo. +Removed 3 unused cells and 7 unused wires. -2.6. Executing OPT_CLEAN pass (remove unused cells and wires). +4. Executing MEMORY pass. + +4.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). -../../../../yosys example.ys -Finding unused cells or wires in module \splice_demo.. -Removed 0 unused cells and 2 unused wires. - +Performed a total of 0 transformations. -2.7. Executing CHECK pass (checking for obvious problems). -Checking module splice_demo... -Found and reported 0 problems. +4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing test.mem write port 0. -2.8. Executing OPT pass (performing simple optimizations). +4.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). -2.8.1. Executing OPT_EXPR pass (perform const folding). +4.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Finding unused cells or wires in module \counter.. +Removed 1 unused cells and 32 unused wires. + + +12.8. Executing OPT_EXPR pass (perform const folding). +Checking read port `\mem'[0] in module `\test': merging output FF to cell. + Write port 0: non-transparent. + +4.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 28 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module splice_demo. +Optimizing module counter. -2.8.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\splice_demo'. -Removed a total of 0 cells. +12.9. Rerunning OPT passes. (Maybe there is more to do..) -2.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \splice_demo.. +12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. -2.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \splice_demo. +12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \counter. Performed a total of 0 changes. -2.8.5. Executing OPT_MERGE pass (detect identical cells). +12.12. Executing OPT_MERGE pass (detect identical cells). +Finding unused cells or wires in module \test.. +Removed 1 unused cells and 9 unused wires. + + +4.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Finding identical cells in module `\counter'. +Removed a total of 0 cells. + +12.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.9. Executing OPT_CLEAN pass (remove unused cells and wires). + +12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Optimizing module memdemo. 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Finding identical cells in module `\splice_demo'. -Removed a total of 0 cells. - -2.8.6. Executing OPT_CLEAN pass (remove unused cells and wires). Running muxtree optimizer on module \memdemo.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. @@ -35145,504 +35033,247 @@ 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Finding unused cells or wires in module \test.. Optimizing cells in module \memdemo. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. - -4.13. Executing OPT_DFF pass (perform DFF optimizations). -Finding unused cells or wires in module \splice_demo.. - -2.8.7. Executing OPT_EXPR pass (perform const folding). - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) --- Executing script file `example.ys' -- - -1. Executing Verilog-2005 frontend: example.v -Parsing Verilog input from `example.v' to AST representation. -Generating RTLIL representation for module `\example'. -Successfully finished Verilog frontend. - -2. Generating Graphviz representation of design. - -4.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module splice_demo. - -2.8.8. Finished OPT passes. (There is nothing left to do.) -Writing dot description to `example_first.dot'. -Dumping module example to page 1. - -2.9. Executing WREDUCE pass (reducing word size of cells). - -2.10. Executing OPT_CLEAN pass (remove unused cells and wires). - -3. Executing PROC pass (convert processes to netlists). - -3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. - -3.4. Executing PROC_INIT pass (extract init attributes). - -3.5. Executing PROC_ARST pass (detect async resets in processes). - -3.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - - -3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\example.$proc$example.v:3$1'. - 1/1: $0\y[1:0] - -3.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\example.\y' using process `\example.$proc$example.v:3$1'. - created $dff cell `$procdff$6' with positive edge clock. - -3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -Finding unused cells or wires in module \memdemo.. - -4.15. Executing OPT_EXPR pass (perform const folding). - -3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\example.$proc$example.v:3$1'. -Removing empty process `example.$proc$example.v:3$1'. -Cleaned up 1 empty switch. - -3.12. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \splice_demo.. - -2.11. Executing MEMORY_COLLECT pass (generating $mem cells). - -2.12. Executing OPT pass (performing simple optimizations). - -2.12.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module example. -Optimizing module splice_demo. - -4. Generating Graphviz representation of design. - -2.12.2. Executing OPT_MERGE pass (detect identical cells). -Optimizing module memdemo. - -4.16. Finished OPT passes. (There is nothing left to do.) -Finding identical cells in module `\splice_demo'. -Removed a total of 0 cells. +4.10. Executing MEMORY_COLLECT pass (generating $mem cells). -2.12.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Writing dot description to `example_second.dot'. -Dumping module example to page 1. +4.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). +Mapping memory \mem in module \test: + created 2 $dff cells and 0 static cells of width 8. +Extracted data FF from read port 0 of test.mem: $\mem$rdreg[0] + read interface: 1 $dff and 1 $mux cells. + write interface: 2 write mux blocks. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \splice_demo.. +Finding unused cells or wires in module \counter.. -2.12.4. Finished fast OPT passes. +12.15. Executing OPT_EXPR pass (perform const folding). +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. -2.13. Printing statistics. +4.13. Executing OPT_DFF pass (perform DFF optimizations). +Optimizing module counter. -=== splice_demo === +4.14. Executing OPT_CLEAN pass (remove unused cells and wires). - Number of wires: 8 - Number of wire bits: 26 - Number of public wires: 8 - Number of public wire bits: 26 - Number of ports: 8 - Number of port bits: 26 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 2 - $neg 1 - $not 1 +12.16. Finished OPT passes. (There is nothing left to do.) -2.14. Executing CHECK pass (checking for obvious problems). -Checking module splice_demo... -Found and reported 0 problems. +13. Executing SPLITNETS pass (splitting up multi-bit signals). +Removed 0 unused cells and 2 unused wires. -3. Generating Graphviz representation of design. -Optimizing module example. +14. Generating Graphviz representation of design. +Optimizing module test. + 5.2. Executing OPT_MERGE pass (detect identical cells). -Writing dot description to `splice.dot'. -Dumping module splice_demo to page 1. +Finding unused cells or wires in module \memdemo.. -End of script. Logfile hash: 2eeb6955f1, CPU: user 0.03s system 0.02s, MEM: 8.60 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 35% 5x opt_expr (0 sec), 26% 4x opt_clean (0 sec), ... -Finding identical cells in module `\example'. +4.15. Executing OPT_EXPR pass (perform const folding). +Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \example.. +Writing dot description to `counter_02.dot'. +Dumping module counter to page 1. +Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. - dead port 2/2 on $mux $ternary$example.v:5$3. -Removed 1 multiplexer ports. - +Removed 0 multiplexer ports. + 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \example. + Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\example'. + +15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). + cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. + final dff cell mappings: + unmapped dff cell: $_DFF_N_ + \DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); + unmapped dff cell: $_DFF_NN0_ + unmapped dff cell: $_DFF_NN1_ + unmapped dff cell: $_DFF_NP0_ + unmapped dff cell: $_DFF_NP1_ + unmapped dff cell: $_DFF_PN0_ + unmapped dff cell: $_DFF_PN1_ + unmapped dff cell: $_DFF_PP0_ + unmapped dff cell: $_DFF_PP1_ + unmapped dff cell: $_DFFE_NN_ + unmapped dff cell: $_DFFE_NP_ + unmapped dff cell: $_DFFE_PN_ + unmapped dff cell: $_DFFE_PP_ + unmapped dff cell: $_DFFSR_NNN_ + unmapped dff cell: $_DFFSR_NNP_ + unmapped dff cell: $_DFFSR_NPN_ + unmapped dff cell: $_DFFSR_NPP_ + unmapped dff cell: $_DFFSR_PNN_ + unmapped dff cell: $_DFFSR_PNP_ + unmapped dff cell: $_DFFSR_PPN_ + unmapped dff cell: $_DFFSR_PPP_ + +15.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). +Mapping DFF cells in module `\counter': + mapped 2 $_DFF_P_ cells to \DFF cells. + +16. Executing ABC pass (technology mapping using ABC). + +16.1. Extracting gate netlist of module `\counter' to `/input.blif'.. +Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). -../../../../yosys example.ys -Adding EN signal on $procdff$6 ($dff) from module example (D = $ternary$example.v:5$3_Y, Q = \y). +Extracted 6 gates and 11 wires to a netlist network with 4 inputs and 2 outputs. -5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +16.1.1. Executing ABC. +Optimizing module memdemo. -5. Executing SUBMOD pass (moving cells to submodules as requested). +4.16. Finished OPT passes. (There is nothing left to do.) -5.1. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \example.. -Removed 1 unused cells and 4 unused wires. +5. Generating Graphviz representation of design. + +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Writing dot description to `memdemo_00.dot'. +Dumping module memdemo to page 1. + +6. Generating Graphviz representation of design. +Finding unused cells or wires in module \test.. +Removed 1 unused cells and 6 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \memdemo.. - -5.2. Continuing SUBMOD pass. -Creating submodule scramble (\scramble) of module \memdemo. - signal \clk: input \clk - signal \d: input \d - signal \mem[2]: output \mem[2] - signal $auto$rtlil.cc:2826:And$129: internal - signal $memory\mem$wrmux[1][2][0]$y$119: internal - signal \mem[1]: output \mem[1] - signal $auto$rtlil.cc:2826:And$141: internal - signal \mem[3]: output \mem[3] - signal $0$memwr$\mem$memdemo.v:13$2_DATA[3:0]$8: internal - signal $0$memwr$\mem$memdemo.v:13$3_DATA[3:0]$10: internal - signal $0$memwr$\mem$memdemo.v:13$4_DATA[3:0]$12: internal - signal $0$memwr$\mem$memdemo.v:13$5_DATA[3:0]$14: internal - signal $0$memwr$\mem$memdemo.v:15$6_ADDR[1:0]$16: input \n1 - signal $auto$rtlil.cc:2826:And$117: internal - signal $memory\mem$wrmux[3][2][0]$y$143: internal - signal $memory\mem$wrmux[2][2][0]$y$131: internal - signal $auto$rtlil.cc:2826:And$103: internal - signal $memory\mem$wrmux[0][2][0]$y$105: internal - signal $auto$rtlil.cc:2833:Eq$99: internal - signal \mem[0]: output \mem[0] - signal $auto$rtlil.cc:2833:Eq$101: internal - cell $memory\mem[3]$77 ($dff) - cell $memory\mem[2]$75 ($dff) - cell $memory\mem[1]$73 ($dff) - cell $memory\mem[0]$71 ($dff) - cell $memory\mem$wrmux[3][2][0]$142 ($mux) - cell $memory\mem$wrmux[2][2][0]$130 ($mux) - cell $memory\mem$wrmux[1][2][0]$118 ($mux) - cell $memory\mem$wrmux[0][2][0]$104 ($mux) - cell $auto$memory_map.cc:97:addr_decode$140 ($and) - cell $auto$memory_map.cc:97:addr_decode$128 ($and) - cell $auto$memory_map.cc:97:addr_decode$116 ($and) - cell $auto$memory_map.cc:97:addr_decode$102 ($and) - cell $auto$memory_map.cc:92:addr_decode$98 ($not) - cell $auto$memory_map.cc:92:addr_decode$100 ($not) - cell $add$memdemo.v:13$30 ($add) - cell $add$memdemo.v:13$27 ($add) - cell $add$memdemo.v:13$24 ($add) - cell $add$memdemo.v:13$21 ($add) -Optimizing module example. +Writing dot description to `memdemo_01.dot'. +Dumping selected parts of module memdemo to page 1. -6. Executing SUBMOD pass (moving cells to submodules as requested). +7. Generating Graphviz representation of design. +Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \example.. +Running muxtree optimizer on module \test.. Creating internal representation of mux trees. - No muxes found in this module. + Evaluating internal representation of mux trees. + Analyzing evaluation results. Removed 0 multiplexer ports. + 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \example. + Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). - -6.1. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding identical cells in module `\example'. +Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). +Writing dot description to `memdemo_02.dot'. +Dumping selected parts of module memdemo to page 1. - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `example.ys' -- - -1. Executing Verilog-2005 frontend: example.v +8. Generating Graphviz representation of design. +Adding EN signal on $memory\mem[1]$23 ($dff) from module test (D = \DIN, Q = \mem[1]). +Adding EN signal on $memory\mem[0]$21 ($dff) from module test (D = \DIN, Q = \mem[0]). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 14 unused wires. - - -6.2. Continuing SUBMOD pass. -Parsing Verilog input from `example.v' to AST representation. -Generating RTLIL representation for module `\example'. -Successfully finished Verilog frontend. - -2. Generating Graphviz representation of design. -Finding unused cells or wires in module \example.. +Finding unused cells or wires in module \test.. +Removed 2 unused cells and 2 unused wires. + 5.15. Executing OPT_EXPR pass (perform const folding). -Creating submodule outstage (\outstage) of module \memdemo. - signal \clk: input \clk - signal \mem[2]: input \mem[2] - signal $\mem$rdreg[0]$d: internal - signal $memory\mem$rdmux[0][0][0]$a$80: internal - signal \mem[1]: input \mem[1] - signal \y: output \y - signal \mem[3]: input \mem[3] - signal $0\s2[1:0]: input \n1 - signal \mem[0]: input \mem[0] - signal $memory\mem$rdmux[0][0][0]$b$81: internal - cell $memory\mem$rdmux[0][1][1]$85 ($mux) - cell $memory\mem$rdmux[0][1][0]$82 ($mux) - cell $memory\mem$rdmux[0][0][0]$79 ($mux) - cell $\mem$rdreg[0] ($dff) -Writing dot description to `example_first.dot'. -Dumping module example to page 1. - -7. Executing SUBMOD pass (moving cells to submodules as requested). - -7.1. Executing OPT_CLEAN pass (remove unused cells and wires). - -3. Executing PROC pass (convert processes to netlists). - -3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. - -3.4. Executing PROC_INIT pass (extract init attributes). - -3.5. Executing PROC_ARST pass (detect async resets in processes). - -3.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - - -3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\example.$proc$example.v:3$1'. - 1/1: $0\y[1:0] - -3.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\example.\y' using process `\example.$proc$example.v:3$1'. - created $dff cell `$procdff$6' with positive edge clock. - -3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\example.$proc$example.v:3$1'. -Removing empty process `example.$proc$example.v:3$1'. -Cleaned up 1 empty switch. - -3.12. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \memdemo.. -Removed 0 unused cells and 3 unused wires. - - -7.2. Continuing SUBMOD pass. -Optimizing module example. - -5.16. Finished OPT passes. (There is nothing left to do.) - -6. Generating Graphviz representation of design. -Creating submodule selstage (\selstage) of module \memdemo. - signal \d: input \d - signal \s1: input \s1 - signal \s2: input \s2 - signal $0\s2[1:0]: output \n1 - signal $0$memwr$\mem$memdemo.v:15$6_ADDR[1:0]$16: output \n2 - signal $xor$memdemo.v:14$31_Y: internal - signal $reduce_bool$memdemo.v:14$32_Y: internal - cell $xor$memdemo.v:14$31 ($xor) - cell $ternary$memdemo.v:14$33 ($mux) - cell $reduce_bool$memdemo.v:14$32 ($reduce_bool) -Writing dot description to `example_third.dot'. -Dumping module example to page 1. - -8. Generating Graphviz representation of design. -Optimizing module example. - -4. Generating Graphviz representation of design. - -End of script. Logfile hash: 1968fcbfd1, CPU: user 0.04s system 0.01s, MEM: 8.89 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 37% 4x opt_expr (0 sec), 15% 3x show (0 sec), ... -Writing dot description to `submod_00.dot'. -Dumping module memdemo to page 1. -Writing dot description to `example_second.dot'. -Dumping module example to page 1. - -5. Executing OPT pass (performing simple optimizations). +Writing dot description to `memdemo_03.dot'. +Dumping selected parts of module memdemo to page 1. 9. Generating Graphviz representation of design. +Optimizing module test. -5.1. Executing OPT_EXPR pass (perform const folding). -../../../../yosys example.ys -Writing dot description to `submod_01.dot'. -Dumping module scramble to page 1. - -10. Generating Graphviz representation of design. -Optimizing module example. - -5.2. Executing OPT_MERGE pass (detect identical cells). -Writing dot description to `submod_02.dot'. -Dumping module outstage to page 1. - -11. Generating Graphviz representation of design. -Finding identical cells in module `\example'. -Removed a total of 0 cells. +5.16. Rerunning OPT passes. (Maybe there is more to do..) -5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \example.. +5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. - dead port 2/2 on $mux $ternary$example.v:5$3. -Removed 1 multiplexer ports. +Removed 0 multiplexer ports. -5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \example. +5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \test. Performed a total of 0 changes. -5.5. Executing OPT_MERGE pass (detect identical cells). -Writing dot description to `submod_03.dot'. -Dumping module selstage to page 1. -Finding identical cells in module `\example'. -Removed a total of 0 cells. - -5.6. Executing OPT_DFF pass (perform DFF optimizations). - -End of script. Logfile hash: ff5e3e9659, CPU: user 0.15s system 0.02s, MEM: 10.38 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 27% 12x opt_clean (0 sec), 21% 9x opt_expr (0 sec), ... -Adding EN signal on $procdff$6 ($dff) from module example (D = $ternary$example.v:5$3_Y, Q = \y). - -5.7. Executing OPT_CLEAN pass (remove unused cells and wires). -../../../../yosys submod.ys -Finding unused cells or wires in module \example.. -Removed 1 unused cells and 4 unused wires. - - -5.8. Executing OPT_EXPR pass (perform const folding). - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `example.ys' -- - -1. Executing Verilog-2005 frontend: example.v -Parsing Verilog input from `example.v' to AST representation. -Generating RTLIL representation for module `\example'. +5.19. Executing OPT_MERGE pass (detect identical cells). +Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. -2. Generating Graphviz representation of design. -Optimizing module example. - -5.9. Rerunning OPT passes. (Maybe there is more to do..) - -5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \example.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \example. -Performed a total of 0 changes. - -5.12. Executing OPT_MERGE pass (detect identical cells). -Writing dot description to `example_first.dot'. -Dumping module example to page 1. - -3. Executing PROC pass (convert processes to netlists). - -3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. - -3.4. Executing PROC_INIT pass (extract init attributes). - -3.5. Executing PROC_ARST pass (detect async resets in processes). - -3.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - - -3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\example.$proc$example.v:3$1'. - 1/1: $0\y[1:0] +3.2. Continuing TECHMAP pass. +Writing dot description to `memdemo_04.dot'. +Dumping selected parts of module memdemo to page 1. -3.8. Executing PROC_DLATCH pass (convert process syncs to latches). -Finding identical cells in module `\example'. +10. Generating Graphviz representation of design. +Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +Finding identical cells in module `\test'. Removed a total of 0 cells. -5.13. Executing OPT_DFF pass (perform DFF optimizations). +5.20. Executing OPT_DFF pass (perform DFF optimizations). +Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. -3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\example.\y' using process `\example.$proc$example.v:3$1'. - created $dff cell `$procdff$6' with positive edge clock. +5.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $and. +Writing dot description to `memdemo_05.dot'. +Dumping selected parts of module memdemo to page 1. +Finding unused cells or wires in module \test.. -3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +5.22. Executing OPT_EXPR pass (perform const folding). -3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\example.$proc$example.v:3$1'. -Removing empty process `example.$proc$example.v:3$1'. -Cleaned up 1 empty switch. +End of script. Logfile hash: ade9f67caf, CPU: user 0.14s system 0.01s, MEM: 10.36 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 23% 9x opt_expr (0 sec), 22% 9x opt_clean (0 sec), ... +Optimizing module test. -3.12. Executing OPT_EXPR pass (perform const folding). +5.23. Finished OPT passes. (There is nothing left to do.) -5.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \example.. +6. Generating Graphviz representation of design. +Writing dot description to `memory_01.dot'. +Dumping module test to page 1. -5.15. Executing OPT_EXPR pass (perform const folding). +End of script. Logfile hash: 3f34ade637, CPU: user 0.08s system 0.00s, MEM: 9.68 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 32% 5x opt_expr (0 sec), 20% 5x opt_clean (0 sec), ... +../../../../yosys submod.ys +../../../../yosys -p 'script memory_02.ys; show -notitle -prefix memory_02 -format dot' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -35654,22 +35285,19 @@ -- Executing script file `submod.ys' -- 1. Executing Verilog-2005 frontend: memdemo.v -Optimizing module example. - -4. Generating Graphviz representation of design. -Writing dot description to `example_second.dot'. -Dumping module example to page 1. -Optimizing module example. -5. Executing OPT pass (performing simple optimizations). + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -5.1. Executing OPT_EXPR pass (perform const folding). +-- Running command `script memory_02.ys; show -notitle -prefix memory_02 -format dot' -- -5.16. Finished OPT passes. (There is nothing left to do.) +-- Executing script file `memory_02.ys' -- -6. Generating Graphviz representation of design. -Writing dot description to `example_third.dot'. -Dumping module example to page 1. +1. Executing Verilog-2005 frontend: memory_02.v Parsing Verilog input from `memdemo.v' to AST representation. Generating RTLIL representation for module `\memdemo'. Successfully finished Verilog frontend. @@ -35682,10 +35310,6 @@ Top module: \memdemo 2.1.2. Analyzing design hierarchy.. - -End of script. Logfile hash: 1968fcbfd1, CPU: user 0.04s system 0.01s, MEM: 8.89 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 37% 4x opt_expr (0 sec), 16% 3x show (0 sec), ... Top module: \memdemo Removed 0 unused modules. @@ -35706,7 +35330,6 @@ 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). -Optimizing module example. Converted 0 switches. 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). @@ -35714,23 +35337,31 @@ 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). -5.2. Executing OPT_MERGE pass (detect identical cells). - 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -Finding identical cells in module `\example'. -Removed a total of 0 cells. +Parsing Verilog input from `memory_02.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. -5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -../../../../yosys cmos.ys -Running muxtree optimizer on module \example.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. - dead port 2/2 on $mux $ternary$example.v:5$3. -Removed 1 multiplexer ports. - +2. Executing HIERARCHY pass (managing design hierarchy). -5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +2.1. Analyzing design hierarchy.. +Top module: \test + +2.2. Analyzing design hierarchy.. +Top module: \test +Removed 0 unused modules. + +3. Executing PROC pass (convert processes to netlists). + +3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$memory_02.v:17$10 in module test. +Marked 1 switch rules as full_case in process $proc$memory_02.v:13$3 in module test. +Removed a total of 0 dead cases. + +3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Creating register for signal `\memdemo.\y' using process `\memdemo.$proc$memdemo.v:11$7'. created $dff cell `$procdff$35' with positive edge clock. Creating register for signal `\memdemo.\i' using process `\memdemo.$proc$memdemo.v:11$7'. @@ -35765,139 +35396,128 @@ 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). - Optimizing cells in module \example. -Performed a total of 0 changes. - -5.5. Executing OPT_MERGE pass (detect identical cells). Removing empty process `memdemo.$proc$memdemo.v:11$7'. Cleaned up 0 empty switches. 2.2.12. Executing OPT_EXPR pass (perform const folding). -Finding identical cells in module `\example'. -Removed a total of 0 cells. - -5.6. Executing OPT_DFF pass (perform DFF optimizations). -Optimizing module memdemo. -Adding EN signal on $procdff$6 ($dff) from module example (D = $ternary$example.v:5$3_Y, Q = \y). +Removed 0 redundant assignments. +Promoted 8 assignments to connections. -5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +3.4. Executing PROC_INIT pass (extract init attributes). -2.3. Executing FUTURE pass. +3.5. Executing PROC_ARST pass (detect async resets in processes). -2.4. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \example.. -Removed 1 unused cells and 4 unused wires. +3.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. -5.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module memdemo. - -2.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module example. - -5.9. Rerunning OPT passes. (Maybe there is more to do..) - -5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \example.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \example. -Performed a total of 0 changes. - -5.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\example'. -Removed a total of 0 cells. - -5.13. Executing OPT_DFF pass (perform DFF optimizations). - -5.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \memdemo.. -Removed 12 unused cells and 26 unused wires. - +3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\test.$proc$memory_02.v:24$19'. +Creating decoders for process `\test.$proc$memory_02.v:21$17'. +Creating decoders for process `\test.$proc$memory_02.v:17$10'. + 1/3: $1$memwr$\memory$memory_02.v:19$2_EN[7:0]$16 + 2/3: $1$memwr$\memory$memory_02.v:19$2_DATA[7:0]$15 + 3/3: $1$memwr$\memory$memory_02.v:19$2_ADDR[7:0]$14 +Creating decoders for process `\test.$proc$memory_02.v:13$3'. + 1/3: $1$memwr$\memory$memory_02.v:15$1_EN[7:0]$9 + 2/3: $1$memwr$\memory$memory_02.v:15$1_DATA[7:0]$8 + 3/3: $1$memwr$\memory$memory_02.v:15$1_ADDR[7:0]$7 -2.6. Executing CHECK pass (checking for obvious problems). +3.8. Executing PROC_DLATCH pass (convert process syncs to latches). - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\test.\RD2_DATA' using process `\test.$proc$memory_02.v:24$19'. + created $dff cell `$procdff$39' with positive edge clock. +Creating register for signal `\test.\RD1_DATA' using process `\test.$proc$memory_02.v:21$17'. + created $dff cell `$procdff$40' with positive edge clock. +Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_ADDR' using process `\test.$proc$memory_02.v:17$10'. + created $dff cell `$procdff$41' with positive edge clock. +Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_DATA' using process `\test.$proc$memory_02.v:17$10'. + created $dff cell `$procdff$42' with positive edge clock. +Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_EN' using process `\test.$proc$memory_02.v:17$10'. + created $dff cell `$procdff$43' with positive edge clock. +Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_ADDR' using process `\test.$proc$memory_02.v:13$3'. + created $dff cell `$procdff$44' with positive edge clock. +Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_DATA' using process `\test.$proc$memory_02.v:13$3'. + created $dff cell `$procdff$45' with positive edge clock. +Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_EN' using process `\test.$proc$memory_02.v:13$3'. + created $dff cell `$procdff$46' with positive edge clock. --- Executing script file `cmos.ys' -- +3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -1. Executing Verilog-2005 frontend: cmos.v -Finding unused cells or wires in module \example.. +3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Optimizing module memdemo. +Removing empty process `test.$proc$memory_02.v:24$19'. +Removing empty process `test.$proc$memory_02.v:21$17'. +Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:17$10'. +Removing empty process `test.$proc$memory_02.v:17$10'. +Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:13$3'. +Removing empty process `test.$proc$memory_02.v:13$3'. +Cleaned up 2 empty switches. -5.15. Executing OPT_EXPR pass (perform const folding). -Parsing Verilog input from `cmos.v' to AST representation. -Generating RTLIL representation for module `\cmos_demo'. -Successfully finished Verilog frontend. +3.12. Executing OPT_EXPR pass (perform const folding). -2. Executing PREP pass. +2.3. Executing FUTURE pass. +Optimizing module test. -2.1. Executing HIERARCHY pass (managing design hierarchy). +2.4. Executing OPT_EXPR pass (perform const folding). +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $or. +No more expansions possible. + -2.1.1. Analyzing design hierarchy.. -Top module: \cmos_demo +4. Executing ABC pass (technology mapping using ABC). -2.1.2. Analyzing design hierarchy.. -Top module: \cmos_demo -Removed 0 unused modules. +4.1. Extracting gate netlist of module `\cmos_demo' to `/input.blif'.. +Optimizing module memdemo. -2.2. Executing PROC pass (convert processes to netlists). +2.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs. -2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. +4.1.1. Executing ABC. +Removed 6 unused cells and 26 unused wires. -2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. +4. Executing MEMORY pass. -2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. +4.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. -2.2.4. Executing PROC_INIT pass (extract init attributes). +4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. -2.2.5. Executing PROC_ARST pass (detect async resets in processes). +4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing test.memory write port 0. + Analyzing test.memory write port 1. -2.2.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. +4.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). -2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +4.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Finding unused cells or wires in module \memdemo.. +Removed 12 unused cells and 26 unused wires. + -2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +2.6. Executing CHECK pass (checking for obvious problems). Checking module memdemo... Found and reported 0 problems. 2.7. Executing OPT pass (performing simple optimizations). 2.7.1. Executing OPT_EXPR pass (perform const folding). +Checking read port `\memory'[0] in module `\test': merging output FF to cell. +Checking read port `\memory'[1] in module `\test': merging output FF to cell. -2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). - -2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -2.2.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module example. +4.6. Executing OPT_CLEAN pass (remove unused cells and wires). Optimizing module memdemo. -5.16. Finished OPT passes. (There is nothing left to do.) - 2.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding unused cells or wires in module \test.. +Removed 2 unused cells and 18 unused wires. + -6. Generating Graphviz representation of design. -Optimizing module cmos_demo. - -2.3. Executing FUTURE pass. -Writing dot description to `example_third.dot'. -Dumping module example to page 1. +4.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Finding identical cells in module `\memdemo'. Removed a total of 4 cells. @@ -35911,40 +35531,34 @@ 2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - -End of script. Logfile hash: 1968fcbfd1, CPU: user 0.04s system 0.01s, MEM: 8.89 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 36% 4x opt_expr (0 sec), 16% 3x show (0 sec), ... Optimizing cells in module \memdemo. Performed a total of 0 changes. 2.7.5. Executing OPT_MERGE pass (detect identical cells). +Consolidating read ports of memory test.memory by address: +Consolidating write ports of memory test.memory by address: +Consolidating write ports of memory test.memory using sat-based resource sharing: -2.4. Executing OPT_EXPR pass (perform const folding). +4.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). -../../../../yosys cmos.ys -Optimizing module cmos_demo. +Finding unused cells or wires in module \test.. -2.5. Executing OPT_CLEAN pass (remove unused cells and wires). +4.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +5. Executing OPT pass (performing simple optimizations). + +5.1. Executing OPT_EXPR pass (perform const folding). Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 4 unused wires. 2.7.7. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \cmos_demo.. -Removed 0 unused cells and 1 unused wires. - - -2.6. Executing CHECK pass (checking for obvious problems). -Checking module cmos_demo... -Found and reported 0 problems. - -2.7. Executing OPT pass (performing simple optimizations). - -2.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module memdemo. 2.7.8. Rerunning OPT passes. (Maybe there is more to do..) @@ -35962,47 +35576,53 @@ Performed a total of 0 changes. 2.7.11. Executing OPT_MERGE pass (detect identical cells). -Optimizing module cmos_demo. +Optimizing module test. + -2.7.2. Executing OPT_MERGE pass (detect identical cells). +5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding identical cells in module `\cmos_demo'. +Finding identical cells in module `\test'. Removed a total of 0 cells. -2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \cmos_demo.. +5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \test.. Creating internal representation of mux trees. - No muxes found in this module. + Evaluating internal representation of mux trees. + Analyzing evaluation results. Removed 0 multiplexer ports. + -2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \cmos_demo. -Performed a total of 0 changes. +5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \test. + Consolidated identical input bits for $mux cell $procmux$31: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] + New connections: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [7:1] = { $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] } + Consolidated identical input bits for $mux cell $procmux$22: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] + New connections: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [7:1] = { $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] } + Optimizing cells in module \test. +Performed a total of 2 changes. -2.7.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\cmos_demo'. +5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\test'. Removed a total of 0 cells. -2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). +5.6. Executing OPT_DFF pass (perform DFF optimizations). Finding unused cells or wires in module \memdemo.. 2.7.13. Executing OPT_EXPR pass (perform const folding). -Finding unused cells or wires in module \cmos_demo.. -2.7.7. Executing OPT_EXPR pass (perform const folding). +5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Optimizing module memdemo. 2.7.14. Finished OPT passes. (There is nothing left to do.) 2.8. Executing WREDUCE pass (reducing word size of cells). -Optimizing module cmos_demo. - -2.7.8. Finished OPT passes. (There is nothing left to do.) - -2.8. Executing WREDUCE pass (reducing word size of cells). Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$50 (mem). Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$51 (mem). Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$52 (mem). @@ -36013,127 +35633,49 @@ Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$26 (mem). 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \test.. +Removed 0 unused cells and 4 unused wires. + -2.9. Executing OPT_CLEAN pass (remove unused cells and wires). - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `cmos.ys' -- - -1. Executing Verilog-2005 frontend: cmos.v -Finding unused cells or wires in module \cmos_demo.. - -2.10. Executing MEMORY_COLLECT pass (generating $mem cells). - -2.11. Executing OPT pass (performing simple optimizations). - -2.11.1. Executing OPT_EXPR pass (perform const folding). -Parsing Verilog input from `cmos.v' to AST representation. -Generating RTLIL representation for module `\cmos_demo'. -Successfully finished Verilog frontend. - -2. Executing PREP pass. - -2.1. Executing HIERARCHY pass (managing design hierarchy). - -2.1.1. Analyzing design hierarchy.. -Top module: \cmos_demo - -2.1.2. Analyzing design hierarchy.. -Top module: \cmos_demo -Removed 0 unused modules. +5.8. Executing OPT_EXPR pass (perform const folding). Finding unused cells or wires in module \memdemo.. -2.2. Executing PROC pass (convert processes to netlists). - -2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. - -2.2.4. Executing PROC_INIT pass (extract init attributes). - -2.2.5. Executing PROC_ARST pass (detect async resets in processes). - -2.2.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - -2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). - 2.10. Executing MEMORY_COLLECT pass (generating $mem cells). -2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). - 2.11. Executing OPT pass (performing simple optimizations). 2.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module test. + -2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -Optimizing module cmos_demo. +5.9. Rerunning OPT passes. (Maybe there is more to do..) -2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \test.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. -2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. +5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \test. +Performed a total of 0 changes. -2.2.12. Executing OPT_EXPR pass (perform const folding). +5.12. Executing OPT_MERGE pass (detect identical cells). +Optimizing module memdemo. 2.11.2. Executing OPT_MERGE pass (detect identical cells). -Optimizing module memdemo. -Finding identical cells in module `\cmos_demo'. +Finding identical cells in module `\test'. Removed a total of 0 cells. -2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). - -2.11.2. Executing OPT_MERGE pass (detect identical cells). +5.13. Executing OPT_DFF pass (perform DFF optimizations). Finding identical cells in module `\memdemo'. Removed a total of 0 cells. 2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \cmos_demo.. - -2.11.4. Finished fast OPT passes. - -2.12. Printing statistics. -Optimizing module cmos_demo. - -=== cmos_demo === - Number of wires: 3 - Number of wire bits: 4 - Number of public wires: 3 - Number of public wire bits: 4 - Number of ports: 3 - Number of port bits: 4 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 1 - $add 1 - -2.13. Executing CHECK pass (checking for obvious problems). -Checking module cmos_demo... -Found and reported 0 problems. - -3. Executing TECHMAP pass (map to technology primitives). - -2.3. Executing FUTURE pass. - -3.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v +5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \memdemo.. -2.4. Executing OPT_EXPR pass (perform const folding). - 2.11.4. Finished fast OPT passes. 2.12. Printing statistics. @@ -36164,12 +35706,29 @@ 3. Executing MEMORY pass. 3.1. Executing OPT_MEM pass (optimize memories). +Finding unused cells or wires in module \test.. +Removed 0 unused cells and 2 unused wires. + + +5.15. Executing OPT_EXPR pass (perform const folding). Performed a total of 0 transformations. 3.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). -Optimizing module cmos_demo. +Optimizing module test. -2.5. Executing OPT_CLEAN pass (remove unused cells and wires). +5.16. Rerunning OPT passes. (Maybe there is more to do..) + +5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \test.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \test. +Performed a total of 0 changes. + +5.19. Executing OPT_MERGE pass (detect identical cells). Performed a total of 6 transformations. 3.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). @@ -36182,17 +35741,12 @@ 3.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 3.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Finding unused cells or wires in module \cmos_demo.. -Removed 0 unused cells and 1 unused wires. - - -2.6. Executing CHECK pass (checking for obvious problems). -Checking module cmos_demo... -Found and reported 0 problems. +Finding identical cells in module `\test'. +Removed a total of 0 cells. -2.7. Executing OPT pass (performing simple optimizations). +5.20. Executing OPT_DFF pass (perform DFF optimizations). -2.7.1. Executing OPT_EXPR pass (perform const folding). +5.21. Executing OPT_CLEAN pass (remove unused cells and wires). Checking read port `\mem'[0] in module `\memdemo': merging output FF to cell. Write port 0: non-transparent. Write port 1: non-transparent. @@ -36209,32 +35763,19 @@ Checking read port address `\mem'[4] in module `\memdemo': no address FF found. 3.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module cmos_demo. - -2.7.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\cmos_demo'. -Removed a total of 0 cells. - -2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \cmos_demo.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \cmos_demo. -Performed a total of 0 changes. +Finding unused cells or wires in module \test.. -2.7.5. Executing OPT_MERGE pass (detect identical cells). +5.22. Executing OPT_EXPR pass (perform const folding). Finding unused cells or wires in module \memdemo.. Removed 1 unused cells and 5 unused wires. 3.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). -Finding identical cells in module `\cmos_demo'. -Removed a total of 0 cells. +Optimizing module test. -2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). +5.23. Finished OPT passes. (There is nothing left to do.) + +6. Generating Graphviz representation of design. Consolidating read ports of memory memdemo.mem by address: Merging ports 1, 4 (address 2'00). Merging ports 2, 3 (address 2'11). @@ -36250,9 +35791,12 @@ Performed a total of 0 transformations. 3.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \cmos_demo.. +Writing dot description to `memory_02.dot'. +Dumping module test to page 1. -2.7.7. Executing OPT_EXPR pass (perform const folding). +End of script. Logfile hash: da34c3e279, CPU: user 0.07s system 0.01s, MEM: 8.95 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 27% 5x opt_expr (0 sec), 21% 5x opt_clean (0 sec), ... Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 5 unused wires. @@ -36260,9 +35804,6 @@ 3.10. Executing MEMORY_COLLECT pass (generating $mem cells). 3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). -Optimizing module cmos_demo. - -2.7.8. Finished OPT passes. (There is nothing left to do.) Mapping memory \mem in module \memdemo: created 4 $dff cells and 0 static cells of width 4. Extracted data FF from read port 0 of memdemo.mem: $\mem$rdreg[0] @@ -36272,28 +35813,11 @@ 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). - -2.8. Executing WREDUCE pass (reducing word size of cells). - -2.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \cmos_demo.. - -2.10. Executing MEMORY_COLLECT pass (generating $mem cells). - -2.11. Executing OPT pass (performing simple optimizations). - -2.11.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module cmos_demo. - -2.11.2. Executing OPT_MERGE pass (detect identical cells). +../../../../yosys -p 'script techmap_01.ys; show -notitle -prefix techmap_01 -format dot' Optimizing module memdemo. 4.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\cmos_demo'. -Removed a total of 0 cells. - -2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding identical cells in module `\memdemo'. Removed a total of 0 cells. @@ -36310,77 +35834,53 @@ Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). -Finding unused cells or wires in module \cmos_demo.. +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. -2.11.4. Finished fast OPT passes. +4.6. Executing OPT_DFF pass (perform DFF optimizations). -2.12. Printing statistics. +4.7. Executing OPT_CLEAN pass (remove unused cells and wires). -=== cmos_demo === + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - Number of wires: 3 - Number of wire bits: 4 - Number of public wires: 3 - Number of public wire bits: 4 - Number of ports: 3 - Number of port bits: 4 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 1 - $add 1 +-- Running command `script techmap_01.ys; show -notitle -prefix techmap_01 -format dot' -- -2.13. Executing CHECK pass (checking for obvious problems). -Checking module cmos_demo... -Found and reported 0 problems. +-- Executing script file `techmap_01.ys' -- -3. Executing TECHMAP pass (map to technology primitives). +1. Executing Verilog-2005 frontend: techmap_01.v +Parsing Verilog input from `techmap_01.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. -3.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v -Finding identical cells in module `\memdemo'. -Removed a total of 0 cells. +2. Executing HIERARCHY pass (managing design hierarchy). -4.6. Executing OPT_DFF pass (perform DFF optimizations). -Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu_brent_kung'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod_trunc'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\$__div_mod_floor'. -Generating RTLIL representation for module `\_90_divfloor'. -Generating RTLIL representation for module `\_90_modfloor'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_demux'. -Generating RTLIL representation for module `\_90_lut'. +2.1. Analyzing design hierarchy.. +Top module: \test + +2.2. Analyzing design hierarchy.. +Top module: \test +Removed 0 unused modules. + +3. Executing TECHMAP pass (map to technology primitives). + +3.1. Executing Verilog-2005 frontend: techmap_01_map.v +Parsing Verilog input from `techmap_01_map.v' to AST representation. +Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. -Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. - -4.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. -Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. -Using extmapper simplemap for cells of type $xor. -Using extmapper simplemap for cells of type $and. Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 28 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). +Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\$add for cells of type $add. +No more expansions possible. Optimizing module memdemo. 4.9. Rerunning OPT passes. (Maybe there is more to do..) @@ -36402,11 +35902,22 @@ Removed a total of 0 cells. 4.13. Executing OPT_DFF pass (perform DFF optimizations). + +Removed 0 unused cells and 7 unused wires. + +4. Generating Graphviz representation of design. 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Writing dot description to `techmap_01.dot'. +Dumping module test to page 1. + +End of script. Logfile hash: 49c16386d9, CPU: user 0.03s system 0.00s, MEM: 8.99 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 34% 1x techmap (0 sec), 31% 1x clean (0 sec), ... Finding unused cells or wires in module \memdemo.. 4.15. Executing OPT_EXPR pass (perform const folding). +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' Optimizing module memdemo. 4.16. Finished OPT passes. (There is nothing left to do.) @@ -36414,51 +35925,49 @@ 5. Executing SUBMOD pass (moving cells to submodules as requested). 5.1. Executing OPT_CLEAN pass (remove unused cells and wires). -Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. -Using extmapper simplemap for cells of type $pos. -Using extmapper simplemap for cells of type $mux. -Using extmapper simplemap for cells of type $not. -Using extmapper simplemap for cells of type $or. -No more expansions possible. - - -4. Executing ABC pass (technology mapping using ABC). - -4.1. Extracting gate netlist of module `\cmos_demo' to `/input.blif'.. -Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_blif /input.blif +ABC: + read_lib -w /docs/source/code_examples/intro/mycells.lib +ABC: Parsing finished successfully. Parsing time = 0.00 sec +ABC: Warning: Templates are not defined. +ABC: Liberty parser cannot read "time_unit". Assuming time_unit : "1ns". +ABC: Liberty parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). +ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". +ABC: Library "demo" from "/docs/source/code_examples/intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec +ABC: Memory = 0.00 MB. Time = 0.00 sec +ABC: + strash +ABC: + &get -n +ABC: + &fraig -x +ABC: + &put +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + &get -n +ABC: + &dch -f +ABC: + &nf +ABC: + &put +ABC: + write_blif /output.blif -4.1.1. Executing ABC. +16.1.2. Re-integrating ABC results. +ABC RESULTS: NAND cells: 4 +ABC RESULTS: NOR cells: 4 +ABC RESULTS: NOT cells: 3 +ABC RESULTS: internal signals: 5 +ABC RESULTS: input signals: 4 +ABC RESULTS: output signals: 2 +Removing temp directory. Finding unused cells or wires in module \memdemo.. 5.2. Continuing SUBMOD pass. -Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu_brent_kung'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod_trunc'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\$__div_mod_floor'. -Generating RTLIL representation for module `\_90_divfloor'. -Generating RTLIL representation for module `\_90_modfloor'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_demux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. +Removed 0 unused cells and 10 unused wires. -3.2. Continuing TECHMAP pass. +17. Generating Graphviz representation of design. + +17.1. Executing Verilog-2005 frontend: mycells.v Creating submodule scramble (\scramble) of module \memdemo. signal \clk: input \clk signal \d: input \d @@ -36499,15 +36008,26 @@ cell $add$memdemo.v:13$27 ($add) cell $add$memdemo.v:13$24 ($add) cell $add$memdemo.v:13$21 ($add) -Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +Parsing Verilog input from `mycells.v' to AST representation. +Generating RTLIL representation for module `\NOT'. +Generating RTLIL representation for module `\NAND'. +Generating RTLIL representation for module `\NOR'. +Generating RTLIL representation for module `\DFF'. +Successfully finished Verilog frontend. + +17.2. Continuing show pass. 6. Executing SUBMOD pass (moving cells to submodules as requested). -Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. 6.1. Executing OPT_CLEAN pass (remove unused cells and wires). -Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. -Using extmapper simplemap for cells of type $xor. -Using extmapper simplemap for cells of type $and. +Writing dot description to `counter_03.dot'. +Dumping module counter to page 1. + +18. Executing Verilog backend. + +18.1. Executing BMUXMAP pass. + +18.2. Executing DEMUXMAP pass. Finding unused cells or wires in module \memdemo.. Removed 0 unused cells and 14 unused wires. @@ -36528,6 +36048,11 @@ cell $memory\mem$rdmux[0][1][0]$82 ($mux) cell $memory\mem$rdmux[0][0][0]$79 ($mux) cell $\mem$rdreg[0] ($dff) +Dumping module `\counter'. + +End of script. Logfile hash: 22b20c9afa, CPU: user 0.21s system 0.00s, MEM: 12.57 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 46% 1x abc (0 sec), 13% 13x opt_expr (0 sec), ... 7. Executing SUBMOD pass (moving cells to submodules as requested). @@ -36537,6 +36062,7 @@ 7.2. Continuing SUBMOD pass. +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/intro' Creating submodule selstage (\selstage) of module \memdemo. signal \d: input \d signal \s1: input \s1 @@ -36562,32 +36088,15 @@ Dumping module outstage to page 1. 11. Generating Graphviz representation of design. +make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/techmap' +../../../../yosys red_or3x1_test.ys Writing dot description to `submod_03.dot'. Dumping module selstage to page 1. -End of script. Logfile hash: ff5e3e9659, CPU: user 0.15s system 0.01s, MEM: 10.37 MB peak +End of script. Logfile hash: ff5e3e9659, CPU: user 0.16s system 0.00s, MEM: 10.36 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 27% 12x opt_clean (0 sec), 21% 9x opt_expr (0 sec), ... -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' -Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. -Using extmapper simplemap for cells of type $pos. -Using extmapper simplemap for cells of type $mux. -Using extmapper simplemap for cells of type $not. -Using extmapper simplemap for cells of type $or. -No more expansions possible. - - -4. Executing ABC pass (technology mapping using ABC). - -4.1. Extracting gate netlist of module `\cmos_demo' to `/input.blif'.. -Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs. - -4.1.1. Executing ABC. -make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/stubnets' -make[6]: Nothing to be done for 'dots'. -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/stubnets' -make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' -../../../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format dot' +../../../../yosys submod.ys /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -36596,12 +36105,10 @@ \----------------------------------------------------------------------------/ Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) --- Running command `script proc_01.ys; show -notitle -prefix proc_01 -format dot' -- - --- Executing script file `proc_01.ys' -- +-- Executing script file `red_or3x1_test.ys' -- -1. Executing Verilog-2005 frontend: proc_01.v -Parsing Verilog input from `proc_01.v' to AST representation. +1. Executing Verilog-2005 frontend: red_or3x1_test.v +Parsing Verilog input from `red_or3x1_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. @@ -36614,151 +36121,171 @@ Top module: \test Removed 0 unused modules. -3. Executing PROC pass (convert processes to netlists). +3. Executing TECHMAP pass (map to technology primitives). -3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. +3.1. Executing Verilog-2005 frontend: red_or3x1_map.v -3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 1 switch rules as full_case in process $proc$proc_01.v:2$1 in module test. -Removed a total of 0 dead cases. + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 1 redundant assignment. -Promoted 0 assignments to connections. +-- Executing script file `submod.ys' -- -3.4. Executing PROC_INIT pass (extract init attributes). +1. Executing Verilog-2005 frontend: memdemo.v +Parsing Verilog input from `red_or3x1_map.v' to AST representation. +Generating RTLIL representation for module `\$reduce_or'. +Successfully finished Verilog frontend. -3.5. Executing PROC_ARST pass (detect async resets in processes). -Found async reset \R in `\test.$proc$proc_01.v:2$1'. +3.2. Continuing TECHMAP pass. +Using template $paramod$53153ae57fdb25b25475408a64760d7986ecfb0e\$reduce_or for cells of type $reduce_or. +Using template $paramod$fe2472242c070f3b22e97f6c8c19c3569e575d97\$reduce_or for cells of type $reduce_or. +Parsing Verilog input from `memdemo.v' to AST representation. +Generating RTLIL representation for module `\memdemo'. +Successfully finished Verilog frontend. -3.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. +2. Executing PREP pass. -3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\test.$proc$proc_01.v:2$1'. - 1/1: $0\Q[0:0] +2.1. Executing HIERARCHY pass (managing design hierarchy). -3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +2.1.1. Analyzing design hierarchy.. +Top module: \memdemo -3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\test.\Q' using process `\test.$proc$proc_01.v:2$1'. - created $adff cell `$procdff$4' with positive edge clock and positive level reset. +2.1.2. Analyzing design hierarchy.. +Top module: \memdemo +Removed 0 unused modules. -3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +2.2. Executing PROC pass (convert processes to netlists). -3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `test.$proc$proc_01.v:2$1'. +2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. -3.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. - -Removed 0 unused cells and 2 unused wires. +2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. -4. Generating Graphviz representation of design. -Writing dot description to `proc_01.dot'. -Dumping module test to page 1. +2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 14 assignments to connections. -End of script. Logfile hash: 4fe5064e83, CPU: user 0.02s system 0.00s, MEM: 8.83 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 30% 1x opt_expr (0 sec), 26% 1x clean (0 sec), ... -../../../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format dot' -Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 -ABC: ABC command line: "source /abc.script". -ABC: -ABC: + read_blif /input.blif -ABC: + read_lib -w /docs/source/code_examples/show/../intro/mycells.lib -ABC: Parsing finished successfully. Parsing time = 0.00 sec -ABC: Warning: Templates are not defined. -ABC: Liberty parser cannot read "time_unit". Assuming time_unit : "1ns". -ABC: Liberty parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). -ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". -ABC: Library "demo" from "/docs/source/code_examples/show/../intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec -ABC: Memory = 0.00 MB. Time = 0.00 sec -ABC: + strash -ABC: + &get -n -ABC: + &fraig -x -ABC: + &put -ABC: + scorr -ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). -ABC: + dc2 -ABC: + dretime -ABC: + strash -ABC: + &get -n -ABC: + &dch -f -ABC: + &nf -ABC: + &put -ABC: + write_blif /output.blif +2.2.4. Executing PROC_INIT pass (extract init attributes). -4.1.2. Re-integrating ABC results. -ABC RESULTS: NOR cells: 3 -ABC RESULTS: NOT cells: 2 -ABC RESULTS: internal signals: 14 -ABC RESULTS: input signals: 2 -ABC RESULTS: output signals: 2 -Removing temp directory. -Removed 0 unused cells and 36 unused wires. +2.2.5. Executing PROC_ARST pass (detect async resets in processes). -5. Generating Graphviz representation of design. -Writing dot description to `cmos_00.dot'. -Dumping module cmos_demo to page 1. +2.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. -6. Executing Verilog-2005 frontend: cmos.v -Parsing Verilog input from `cmos.v' to AST representation. -Generating RTLIL representation for module `\cmos_demo'. -Successfully finished Verilog frontend. +2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\memdemo.$proc$memdemo.v:11$7'. -7. Executing PREP pass. +2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +cd internals && TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' pdflatex approach_flow.tex --interaction=nonstopmode -7.1. Executing HIERARCHY pass (managing design hierarchy). +2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Using template $paramod$1a3ccc6b2ad940e0a4ee2fb765a3adeb638fb7f0\$reduce_or for cells of type $reduce_or. +No more expansions possible. +Creating register for signal `\memdemo.\y' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$35' with positive edge clock. +Creating register for signal `\memdemo.\i' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$36' with positive edge clock. +Creating register for signal `\memdemo.\s1' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$37' with positive edge clock. +Creating register for signal `\memdemo.\s2' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$38' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$39' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_EN' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$40' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$41' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_EN' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$42' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$43' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_EN' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$44' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$45' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_EN' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$46' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_ADDR' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$47' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_DATA' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$48' with positive edge clock. +Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_EN' using process `\memdemo.$proc$memdemo.v:11$7'. + created $dff cell `$procdff$49' with positive edge clock. -7.1.1. Analyzing design hierarchy.. -Top module: \cmos_demo +2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -7.1.2. Analyzing design hierarchy.. -Top module: \cmos_demo -Removed 0 unused modules. +2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `memdemo.$proc$memdemo.v:11$7'. +Cleaned up 0 empty switches. -7.2. Executing PROC pass (convert processes to netlists). +2.2.12. Executing OPT_EXPR pass (perform const folding). + +Removed 0 unused cells and 18 unused wires. -7.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. +4. Executing SPLITNETS pass (splitting up multi-bit signals). -7.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. +5. Generating Graphviz representation of design. -7.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. +5.1. Executing Verilog-2005 frontend: red_or3x1_cells.v +Optimizing module memdemo. -7.2.4. Executing PROC_INIT pass (extract init attributes). +2.3. Executing FUTURE pass. -7.2.5. Executing PROC_ARST pass (detect async resets in processes). +2.4. Executing OPT_EXPR pass (perform const folding). +Parsing Verilog input from `red_or3x1_cells.v' to AST representation. +Generating RTLIL representation for module `\OR3X1'. +Successfully finished Verilog frontend. -7.2.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. +5.2. Continuing show pass. +Writing dot description to `red_or3x1.dot'. +Dumping module test to page 1. -7.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +End of script. Logfile hash: d6e7304939, CPU: user 0.03s system 0.00s, MEM: 8.41 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 40% 1x techmap (0 sec), 22% 4x read_verilog (0 sec), ... +Optimizing module memdemo. -7.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +2.5. Executing OPT_CLEAN pass (remove unused cells and wires). +../../../../yosys sym_mul_test.ys +Finding unused cells or wires in module \memdemo.. +Removed 12 unused cells and 26 unused wires. + -7.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +2.6. Executing CHECK pass (checking for obvious problems). +Checking module memdemo... +Found and reported 0 problems. -7.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +2.7. Executing OPT pass (performing simple optimizations). -7.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. +2.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memdemo. -7.2.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module cmos_demo. +2.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memdemo'. + +Removed a total of 4 cells. -7.3. Executing FUTURE pass. +2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memdemo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + -7.4. Executing OPT_EXPR pass (perform const folding). -Optimizing module cmos_demo. +2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memdemo. +Performed a total of 0 changes. -7.5. Executing OPT_CLEAN pass (remove unused cells and wires). +2.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. + +2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -36767,132 +36294,154 @@ \----------------------------------------------------------------------------/ Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) --- Running command `script proc_02.ys; show -notitle -prefix proc_02 -format dot' -- - --- Executing script file `proc_02.ys' -- - -1. Executing Verilog-2005 frontend: proc_02.v -Finding unused cells or wires in module \cmos_demo.. -Removed 0 unused cells and 1 unused wires. - +-- Executing script file `sym_mul_test.ys' -- -7.6. Executing CHECK pass (checking for obvious problems). -Parsing Verilog input from `proc_02.v' to AST representation. +1. Executing Verilog-2005 frontend: sym_mul_test.v +Parsing Verilog input from `sym_mul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. -Checking module cmos_demo... -Found and reported 0 problems. - -7.7. Executing OPT pass (performing simple optimizations). - -7.7.1. Executing OPT_EXPR pass (perform const folding). Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. -3. Executing PROC pass (convert processes to netlists). +3. Executing TECHMAP pass (map to technology primitives). -3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. +3.1. Executing Verilog-2005 frontend: sym_mul_map.v +Parsing Verilog input from `sym_mul_map.v' to AST representation. +Generating RTLIL representation for module `\$mul'. +Successfully finished Verilog frontend. -3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 1 switch rules as full_case in process $proc$proc_02.v:3$1 in module test. -Removed a total of 0 dead cases. +3.2. Continuing TECHMAP pass. +Finding unused cells or wires in module \memdemo.. +Removed 0 unused cells and 4 unused wires. + -3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 1 redundant assignment. -Promoted 0 assignments to connections. +2.7.7. Executing OPT_EXPR pass (perform const folding). +Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul. +No more expansions possible. +Optimizing module memdemo. -3.4. Executing PROC_INIT pass (extract init attributes). +2.7.8. Rerunning OPT passes. (Maybe there is more to do..) -3.5. Executing PROC_ARST pass (detect async resets in processes). -Found async reset \R in `\test.$proc$proc_02.v:3$1'. +2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memdemo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + -3.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. +2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memdemo. +Performed a total of 0 changes. -3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\test.$proc$proc_02.v:3$1'. - 1/1: $0\Q[0:0] +2.7.11. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. -3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). + +Removed 0 unused cells and 6 unused wires. -3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Optimizing module cmos_demo. +4. Generating Graphviz representation of design. -7.7.2. Executing OPT_MERGE pass (detect identical cells). -Creating register for signal `\test.\Q' using process `\test.$proc$proc_02.v:3$1'. -Warning: Async reset value `\RV' is not constant! - created $aldff cell `$procdff$4' with positive edge clock and positive level non-const reset. +4.1. Executing Verilog-2005 frontend: sym_mul_cells.v +Parsing Verilog input from `sym_mul_cells.v' to AST representation. +Generating RTLIL representation for module `\MYMUL'. +Successfully finished Verilog frontend. -3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +4.2. Continuing show pass. +Finding unused cells or wires in module \memdemo.. -3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `test.$proc$proc_02.v:3$1'. -Cleaned up 0 empty switches. +2.7.13. Executing OPT_EXPR pass (perform const folding). +Writing dot description to `sym_mul.dot'. +Dumping module test to page 1. -3.12. Executing OPT_EXPR pass (perform const folding). -Finding identical cells in module `\cmos_demo'. -Removed a total of 0 cells. +End of script. Logfile hash: 28982f840f, CPU: user 0.01s system 0.01s, MEM: 9.00 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 33% 1x clean (0 sec), 25% 4x read_verilog (0 sec), ... +Optimizing module memdemo. -7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \cmos_demo.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. +2.7.14. Finished OPT passes. (There is nothing left to do.) -7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \cmos_demo. -Performed a total of 0 changes. +2.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$50 (mem). +Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$51 (mem). +Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$52 (mem). +Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$53 (mem). +Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$19 (mem). +Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$20 (mem). +Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$23 (mem). +Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$26 (mem). -7.7.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\cmos_demo'. +2.9. Executing OPT_CLEAN pass (remove unused cells and wires). +../../../../yosys mymul_test.ys +Finding unused cells or wires in module \memdemo.. + +2.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.11. Executing OPT pass (performing simple optimizations). + +2.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memdemo. + +2.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memdemo'. Removed a total of 0 cells. -7.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module test. - -Finding unused cells or wires in module \cmos_demo.. +2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memdemo.. -7.7.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module cmos_demo. +2.11.4. Finished fast OPT passes. -7.7.8. Finished OPT passes. (There is nothing left to do.) +2.12. Printing statistics. -7.8. Executing WREDUCE pass (reducing word size of cells). +=== memdemo === -7.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Removed 0 unused cells and 2 unused wires. + Number of wires: 18 + Number of wire bits: 58 + Number of public wires: 5 + Number of public wire bits: 13 + Number of ports: 3 + Number of port bits: 9 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 11 + $add 4 + $dff 3 + $mem_v2 1 + $mux 1 + $reduce_bool 1 + $xor 1 -4. Generating Graphviz representation of design. -Finding unused cells or wires in module \cmos_demo.. +2.13. Executing CHECK pass (checking for obvious problems). +Checking module memdemo... +Found and reported 0 problems. -7.10. Executing MEMORY_COLLECT pass (generating $mem cells). +3. Executing MEMORY pass. -7.11. Executing OPT pass (performing simple optimizations). +3.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. -7.11.1. Executing OPT_EXPR pass (perform const folding). -Writing dot description to `proc_02.dot'. -Dumping module test to page 1. +3.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). -Warnings: 1 unique messages, 1 total -End of script. Logfile hash: c4b4f83334, CPU: user 0.01s system 0.01s, MEM: 8.89 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 32% 1x opt_expr (0 sec), 26% 1x clean (0 sec), ... -Optimizing module cmos_demo. + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -7.11.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\cmos_demo'. -Removed a total of 0 cells. +-- Executing script file `mymul_test.ys' -- -7.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). -../../../../yosys -p 'script proc_03.ys; show -notitle -prefix proc_03 -format dot' +1. Executing Verilog-2005 frontend: mymul_test.v Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: @@ -36921,42 +36470,70 @@ ABC: + write_blif /output.blif 4.1.2. Re-integrating ABC results. +Parsing Verilog input from `mymul_test.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. +Top module: \test + +2.2. Analyzing design hierarchy.. +Top module: \test +Removed 0 unused modules. + +3. Executing TECHMAP pass (map to technology primitives). + +3.1. Executing Verilog-2005 frontend: sym_mul_map.v ABC RESULTS: NOR cells: 3 ABC RESULTS: NOT cells: 2 ABC RESULTS: internal signals: 14 ABC RESULTS: input signals: 2 ABC RESULTS: output signals: 2 Removing temp directory. -Finding unused cells or wires in module \cmos_demo.. - -7.11.4. Finished fast OPT passes. - -7.12. Printing statistics. +Performed a total of 6 transformations. -=== cmos_demo === +3.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing memdemo.mem write port 0. + Analyzing memdemo.mem write port 1. + Analyzing memdemo.mem write port 2. + Analyzing memdemo.mem write port 3. + Analyzing memdemo.mem write port 4. - Number of wires: 3 - Number of wire bits: 4 - Number of public wires: 3 - Number of public wire bits: 4 - Number of ports: 3 - Number of port bits: 4 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 1 - $add 1 +3.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). +Parsing Verilog input from `sym_mul_map.v' to AST representation. +Generating RTLIL representation for module `\$mul'. +Successfully finished Verilog frontend. -7.13. Executing CHECK pass (checking for obvious problems). -Checking module cmos_demo... -Found and reported 0 problems. +3.2. Executing Verilog-2005 frontend: mymul_map.v -8. Executing TECHMAP pass (map to technology primitives). +3.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Parsing Verilog input from `mymul_map.v' to AST representation. +Generating RTLIL representation for module `\MYMUL'. +Successfully finished Verilog frontend. -8.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v +3.3. Continuing TECHMAP pass. +Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\$mul for cells of type $mul. Removed 0 unused cells and 36 unused wires. 5. Generating Graphviz representation of design. +Checking read port `\mem'[0] in module `\memdemo': merging output FF to cell. + Write port 0: non-transparent. + Write port 1: non-transparent. + Write port 2: non-transparent. + Write port 3: non-transparent. + Write port 4: non-transparent. +Checking read port `\mem'[1] in module `\memdemo': no output FF found. +Checking read port `\mem'[2] in module `\memdemo': no output FF found. +Checking read port `\mem'[3] in module `\memdemo': no output FF found. +Checking read port `\mem'[4] in module `\memdemo': no output FF found. +Checking read port address `\mem'[1] in module `\memdemo': no address FF found. +Checking read port address `\mem'[2] in module `\memdemo': no address FF found. +Checking read port address `\mem'[3] in module `\memdemo': no address FF found. +Checking read port address `\mem'[4] in module `\memdemo': no address FF found. + +3.6. Executing OPT_CLEAN pass (remove unused cells and wires). Writing dot description to `cmos_00.dot'. Dumping module cmos_demo to page 1. @@ -36970,6 +36547,11 @@ 7.1. Executing HIERARCHY pass (managing design hierarchy). 7.1.1. Analyzing design hierarchy.. +Finding unused cells or wires in module \memdemo.. +Removed 1 unused cells and 5 unused wires. + + +3.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Top module: \cmos_demo 7.1.2. Analyzing design hierarchy.. @@ -37000,6 +36582,21 @@ 7.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 7.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Consolidating read ports of memory memdemo.mem by address: + Merging ports 1, 4 (address 2'00). + Merging ports 2, 3 (address 2'11). +Consolidating read ports of memory memdemo.mem by address: + Merging ports 1, 2 (address 2'00). +Consolidating read ports of memory memdemo.mem by address: +Consolidating write ports of memory memdemo.mem by address: + Merging ports 0, 1 (address 2'00). + Merging ports 0, 2 (address 2'00). +Consolidating write ports of memory memdemo.mem by address: + +3.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +3.9. Executing OPT_CLEAN pass (remove unused cells and wires). 7.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). @@ -37007,97 +36604,111 @@ Cleaned up 0 empty switches. 7.2.12. Executing OPT_EXPR pass (perform const folding). +Finding unused cells or wires in module \memdemo.. +Removed 0 unused cells and 5 unused wires. + - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Running command `script proc_03.ys; show -notitle -prefix proc_03 -format dot' -- - --- Executing script file `proc_03.ys' -- +3.10. Executing MEMORY_COLLECT pass (generating $mem cells). -1. Executing Verilog-2005 frontend: proc_03.v +3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Optimizing module cmos_demo. 7.3. Executing FUTURE pass. -Parsing Verilog input from `proc_03.v' to AST representation. -Generating RTLIL representation for module `\test'. -Successfully finished Verilog frontend. - -2. Executing HIERARCHY pass (managing design hierarchy). +Mapping memory \mem in module \memdemo: + created 4 $dff cells and 0 static cells of width 4. +Extracted data FF from read port 0 of memdemo.mem: $\mem$rdreg[0] + read interface: 1 $dff and 3 $mux cells. + write interface: 12 write mux blocks. -2.1. Analyzing design hierarchy.. -Top module: \test +4. Executing OPT pass (performing simple optimizations). -2.2. Analyzing design hierarchy.. -Top module: \test -Removed 0 unused modules. +4.1. Executing OPT_EXPR pass (perform const folding). -3. Executing PROC pass (convert processes to netlists). +7.4. Executing OPT_EXPR pass (perform const folding). +Optimizing module cmos_demo. -3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. +7.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Using template $paramod\MYMUL\WIDTH=32'00000000000000000000000000000010 for cells of type MYMUL. +No more expansions possible. +Optimizing module memdemo. + -3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. +4.2. Executing OPT_MERGE pass (detect identical cells). +Finding unused cells or wires in module \cmos_demo.. +Removed 0 unused cells and 1 unused wires. + -3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. +7.6. Executing CHECK pass (checking for obvious problems). +Checking module cmos_demo... +Found and reported 0 problems. -3.4. Executing PROC_INIT pass (extract init attributes). +7.7. Executing OPT pass (performing simple optimizations). +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. -3.5. Executing PROC_ARST pass (detect async resets in processes). +4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -3.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - +7.7.1. Executing OPT_EXPR pass (perform const folding). +Running muxtree optimizer on module \memdemo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + -3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\test.$proc$proc_03.v:3$1'. - 1/1: $0\Y[0:0] +4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memdemo. +Performed a total of 0 changes. -3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +4.5. Executing OPT_MERGE pass (detect identical cells). + +Removed 0 unused cells and 10 unused wires. +Renaming module \test to \test_mapped. -7.4. Executing OPT_EXPR pass (perform const folding). -No latch inferred for signal `\test.\Y' from process `\test.$proc$proc_03.v:3$1'. +4. Executing Verilog-2005 frontend: mymul_test.v +Parsing Verilog input from `mymul_test.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. -3.9. Executing PROC_DFF pass (convert process syncs to FFs). +5. Executing MITER pass (creating miter circuit). +Creating miter cell "miter" with gold cell "test" and gate cell "test_mapped". -3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +6. Executing FLATTEN pass (flatten design). + -3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 2 empty switches in `\test.$proc$proc_03.v:3$1'. -Removing empty process `test.$proc$proc_03.v:3$1'. -Cleaned up 2 empty switches. +7. Executing SAT pass (solving SAT problems in the circuit). +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. -3.12. Executing OPT_EXPR pass (perform const folding). +4.6. Executing OPT_DFF pass (perform DFF optimizations). Optimizing module cmos_demo. -7.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Optimizing module test. -Finding unused cells or wires in module \cmos_demo.. -Removed 0 unused cells and 1 unused wires. - +7.7.2. Executing OPT_MERGE pass (detect identical cells). -7.6. Executing CHECK pass (checking for obvious problems). -Checking module cmos_demo... -Found and reported 0 problems. +Setting up SAT problem: +Final constraint equation: { } = { } +Imported 9 cells to SAT database. +Import proof-constraint: \trigger = 1'0 +Final proof equation: \trigger = 1'0 -7.7. Executing OPT pass (performing simple optimizations). +Solving problem with 107 variables and 283 clauses.. -7.7.1. Executing OPT_EXPR pass (perform const folding). -Removed 0 unused cells and 4 unused wires. +4.7. Executing OPT_CLEAN pass (remove unused cells and wires). +SAT proof finished - no model found: SUCCESS! -4. Generating Graphviz representation of design. -Optimizing module cmos_demo. + /$$$$$$ /$$$$$$$$ /$$$$$$$ + /$$__ $$ | $$_____/ | $$__ $$ + | $$ \ $$ | $$ | $$ \ $$ + | $$ | $$ | $$$$$ | $$ | $$ + | $$ | $$ | $$__/ | $$ | $$ + | $$/$$ $$ | $$ | $$ | $$ + | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ + \____ $$$|__/|________/|__/|_______/|__/ + \__/ -7.7.2. Executing OPT_MERGE pass (detect identical cells). -Writing dot description to `proc_03.dot'. -Dumping module test to page 1. +8. Executing SPLITNETS pass (splitting up multi-bit signals). + +9. Generating Graphviz representation of design. Finding identical cells in module `\cmos_demo'. Removed a total of 0 cells. @@ -37112,18 +36723,42 @@ Performed a total of 0 changes. 7.7.5. Executing OPT_MERGE pass (detect identical cells). - -End of script. Logfile hash: 5a538b5f7f, CPU: user 0.02s system 0.00s, MEM: 8.95 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 26% 1x clean (0 sec), 26% 1x opt_expr (0 sec), ... +Writing dot description to `mymul.dot'. +Dumping module test_mapped to page 1. Finding identical cells in module `\cmos_demo'. Removed a total of 0 cells. 7.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). -../../../../yosys -p 'script memory_01.ys; show -notitle -prefix memory_01 -format dot' +Finding unused cells or wires in module \memdemo.. +Removed 0 unused cells and 28 unused wires. + + +4.8. Executing OPT_EXPR pass (perform const folding). + +End of script. Logfile hash: 449524bce2, CPU: user 0.05s system 0.00s, MEM: 10.89 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 28% 2x clean (0 sec), 15% 1x techmap (0 sec), ... Finding unused cells or wires in module \cmos_demo.. 7.7.7. Executing OPT_EXPR pass (perform const folding). +../../../../yosys mulshift_test.ys +Optimizing module memdemo. + +4.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memdemo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memdemo. +Performed a total of 0 changes. + +4.12. Executing OPT_MERGE pass (detect identical cells). Optimizing module cmos_demo. 7.7.8. Finished OPT passes. (There is nothing left to do.) @@ -37131,64 +36766,33 @@ 7.8. Executing WREDUCE pass (reducing word size of cells). 7.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding identical cells in module `\memdemo'. +Removed a total of 0 cells. + +4.13. Executing OPT_DFF pass (perform DFF optimizations). Finding unused cells or wires in module \cmos_demo.. 7.10. Executing MEMORY_COLLECT pass (generating $mem cells). +4.14. Executing OPT_CLEAN pass (remove unused cells and wires). + 7.11. Executing OPT pass (performing simple optimizations). 7.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module cmos_demo. +Finding unused cells or wires in module \memdemo.. -7.11.2. Executing OPT_MERGE pass (detect identical cells). -Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu_brent_kung'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod_trunc'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\$__div_mod_floor'. -Generating RTLIL representation for module `\_90_divfloor'. -Generating RTLIL representation for module `\_90_modfloor'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_demux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. +4.15. Executing OPT_EXPR pass (perform const folding). -8.2. Continuing TECHMAP pass. +7.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cmos_demo'. Removed a total of 0 cells. 7.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. -Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +Optimizing module memdemo. Finding unused cells or wires in module \cmos_demo.. - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Running command `script memory_01.ys; show -notitle -prefix memory_01 -format dot' -- - --- Executing script file `memory_01.ys' -- - -1. Executing Verilog-2005 frontend: memory_01.v +4.16. Finished OPT passes. (There is nothing left to do.) 7.11.4. Finished fast OPT passes. @@ -37212,15 +36816,21 @@ Checking module cmos_demo... Found and reported 0 problems. + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) + +-- Executing script file `mulshift_test.ys' -- + +1. Executing Verilog-2005 frontend: mulshift_test.v + 8. Executing TECHMAP pass (map to technology primitives). 8.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v -Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. -Using extmapper simplemap for cells of type $xor. -Using extmapper simplemap for cells of type $pos. -Using extmapper simplemap for cells of type $not. -Using extmapper simplemap for cells of type $mux. -Parsing Verilog input from `memory_01.v' to AST representation. +Parsing Verilog input from `mulshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. @@ -37233,123 +36843,129 @@ Top module: \test Removed 0 unused modules. -3. Executing PROC pass (convert processes to netlists). - -3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 4 assignments to connections. - -3.4. Executing PROC_INIT pass (extract init attributes). - -3.5. Executing PROC_ARST pass (detect async resets in processes). - -3.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - -3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\test.$proc$memory_01.v:5$2'. - -3.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\test.\DOUT' using process `\test.$proc$memory_01.v:5$2'. - created $dff cell `$procdff$7' with positive edge clock. -Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_ADDR' using process `\test.$proc$memory_01.v:5$2'. - created $dff cell `$procdff$8' with positive edge clock. -Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_DATA' using process `\test.$proc$memory_01.v:5$2'. - created $dff cell `$procdff$9' with positive edge clock. -Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_EN' using process `\test.$proc$memory_01.v:5$2'. - created $dff cell `$procdff$10' with positive edge clock. - -3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `test.$proc$memory_01.v:5$2'. -Cleaned up 0 empty switches. - -3.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. -Removed 3 unused cells and 7 unused wires. +3. Executing TECHMAP pass (map to technology primitives). -4. Executing MEMORY pass. +3.1. Executing Verilog-2005 frontend: sym_mul_map.v +Parsing Verilog input from `sym_mul_map.v' to AST representation. +Generating RTLIL representation for module `\$mul'. +Successfully finished Verilog frontend. -4.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. +3.2. Executing Verilog-2005 frontend: mulshift_map.v +Parsing Verilog input from `mulshift_map.v' to AST representation. +Generating RTLIL representation for module `\MYMUL'. +Successfully finished Verilog frontend. -4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). -Performed a total of 0 transformations. +3.3. Continuing TECHMAP pass. +Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul. -4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). - Analyzing test.mem write port 0. +5. Executing SUBMOD pass (moving cells to submodules as requested). -4.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). +5.1. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memdemo.. -4.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Checking read port `\mem'[0] in module `\test': merging output FF to cell. - Write port 0: non-transparent. +5.2. Continuing SUBMOD pass. +Creating submodule scramble (\scramble) of module \memdemo. + signal \clk: input \clk + signal \d: input \d + signal \mem[2]: output \mem[2] + signal $auto$rtlil.cc:2826:And$129: internal + signal $memory\mem$wrmux[1][2][0]$y$119: internal + signal \mem[1]: output \mem[1] + signal $auto$rtlil.cc:2826:And$141: internal + signal \mem[3]: output \mem[3] + signal $0$memwr$\mem$memdemo.v:13$2_DATA[3:0]$8: internal + signal $0$memwr$\mem$memdemo.v:13$3_DATA[3:0]$10: internal + signal $0$memwr$\mem$memdemo.v:13$4_DATA[3:0]$12: internal + signal $0$memwr$\mem$memdemo.v:13$5_DATA[3:0]$14: internal + signal $0$memwr$\mem$memdemo.v:15$6_ADDR[1:0]$16: input \n1 + signal $auto$rtlil.cc:2826:And$117: internal + signal $memory\mem$wrmux[3][2][0]$y$143: internal + signal $memory\mem$wrmux[2][2][0]$y$131: internal + signal $auto$rtlil.cc:2826:And$103: internal + signal $memory\mem$wrmux[0][2][0]$y$105: internal + signal $auto$rtlil.cc:2833:Eq$99: internal + signal \mem[0]: output \mem[0] + signal $auto$rtlil.cc:2833:Eq$101: internal + cell $memory\mem[3]$77 ($dff) + cell $memory\mem[2]$75 ($dff) + cell $memory\mem[1]$73 ($dff) + cell $memory\mem[0]$71 ($dff) + cell $memory\mem$wrmux[3][2][0]$142 ($mux) + cell $memory\mem$wrmux[2][2][0]$130 ($mux) + cell $memory\mem$wrmux[1][2][0]$118 ($mux) + cell $memory\mem$wrmux[0][2][0]$104 ($mux) + cell $auto$memory_map.cc:97:addr_decode$140 ($and) + cell $auto$memory_map.cc:97:addr_decode$128 ($and) + cell $auto$memory_map.cc:97:addr_decode$116 ($and) + cell $auto$memory_map.cc:97:addr_decode$102 ($and) + cell $auto$memory_map.cc:92:addr_decode$98 ($not) + cell $auto$memory_map.cc:92:addr_decode$100 ($not) + cell $add$memdemo.v:13$30 ($add) + cell $add$memdemo.v:13$27 ($add) + cell $add$memdemo.v:13$24 ($add) + cell $add$memdemo.v:13$21 ($add) -4.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. -Removed 1 unused cells and 9 unused wires. - +6. Executing SUBMOD pass (moving cells to submodules as requested). -4.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +6.1. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memdemo.. +Removed 0 unused cells and 14 unused wires. + -4.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). -Performed a total of 0 transformations. +6.2. Continuing SUBMOD pass. +Creating submodule outstage (\outstage) of module \memdemo. + signal \clk: input \clk + signal \mem[2]: input \mem[2] + signal $\mem$rdreg[0]$d: internal + signal $memory\mem$rdmux[0][0][0]$a$80: internal + signal \mem[1]: input \mem[1] + signal \y: output \y + signal \mem[3]: input \mem[3] + signal $0\s2[1:0]: input \n1 + signal \mem[0]: input \mem[0] + signal $memory\mem$rdmux[0][0][0]$b$81: internal + cell $memory\mem$rdmux[0][1][1]$85 ($mux) + cell $memory\mem$rdmux[0][1][0]$82 ($mux) + cell $memory\mem$rdmux[0][0][0]$79 ($mux) + cell $\mem$rdreg[0] ($dff) -4.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. +7. Executing SUBMOD pass (moving cells to submodules as requested). -4.10. Executing MEMORY_COLLECT pass (generating $mem cells). +7.1. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memdemo.. +Removed 0 unused cells and 3 unused wires. + -4.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). -Mapping memory \mem in module \test: - created 2 $dff cells and 0 static cells of width 8. -Extracted data FF from read port 0 of test.mem: $\mem$rdreg[0] - read interface: 1 $dff and 1 $mux cells. - write interface: 2 write mux blocks. +7.2. Continuing SUBMOD pass. +Creating submodule selstage (\selstage) of module \memdemo. + signal \d: input \d + signal \s1: input \s1 + signal \s2: input \s2 + signal $0\s2[1:0]: output \n1 + signal $0$memwr$\mem$memdemo.v:15$6_ADDR[1:0]$16: output \n2 + signal $xor$memdemo.v:14$31_Y: internal + signal $reduce_bool$memdemo.v:14$32_Y: internal + cell $xor$memdemo.v:14$31 ($xor) + cell $ternary$memdemo.v:14$33 ($mux) + cell $reduce_bool$memdemo.v:14$32 ($reduce_bool) -5. Executing OPT pass (performing simple optimizations). +8. Generating Graphviz representation of design. +Writing dot description to `submod_00.dot'. +Dumping module memdemo to page 1. -5.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. - +9. Generating Graphviz representation of design. +Writing dot description to `submod_01.dot'. +Dumping module scramble to page 1. -5.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\test'. -Removed a total of 0 cells. +10. Generating Graphviz representation of design. +Writing dot description to `submod_02.dot'. +Dumping module outstage to page 1. -5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. -Using extmapper simplemap for cells of type $and. -Using extmapper simplemap for cells of type $or. +11. Generating Graphviz representation of design. +Writing dot description to `submod_03.dot'. +Dumping module selstage to page 1. +Using template $paramod$fb3c811cfd9dc2fc74fe40190dfcd365f04584f7\MYMUL for cells of type MYMUL. No more expansions possible. -Running muxtree optimizer on module \test.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - - -9. Executing SPLITNETS pass (splitting up multi-bit signals). - Optimizing cells in module \test. -Performed a total of 0 changes. - -5.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\test'. -Removed a total of 0 cells. - -5.6. Executing OPT_DFF pass (perform DFF optimizations). Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. @@ -37379,93 +36995,69 @@ 8.2. Continuing TECHMAP pass. -5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +End of script. Logfile hash: ff5e3e9659, CPU: user 0.16s system 0.00s, MEM: 10.36 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 27% 12x opt_clean (0 sec), 21% 9x opt_expr (0 sec), ... Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. + +Removed 0 unused cells and 16 unused wires. -10. Executing ABC pass (technology mapping using ABC). -Finding unused cells or wires in module \test.. -Removed 1 unused cells and 6 unused wires. - - -5.8. Executing OPT_EXPR pass (perform const folding). +4. Generating Graphviz representation of design. -10.1. Extracting gate netlist of module `\cmos_demo' to `/input.blif'.. +4.1. Executing Verilog-2005 frontend: sym_mul_cells.v Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $mux. -Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs. - -10.1.1. Executing ABC. -Optimizing module test. - -5.9. Rerunning OPT passes. (Maybe there is more to do..) - -5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \test.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \test. -Performed a total of 0 changes. - -5.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\test'. -Removed a total of 0 cells. - -5.13. Executing OPT_DFF pass (perform DFF optimizations). -Adding EN signal on $memory\mem[1]$23 ($dff) from module test (D = \DIN, Q = \mem[1]). -Adding EN signal on $memory\mem[0]$21 ($dff) from module test (D = \DIN, Q = \mem[0]). - -5.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. -Removed 2 unused cells and 2 unused wires. - +Parsing Verilog input from `sym_mul_cells.v' to AST representation. +Generating RTLIL representation for module `\MYMUL'. +Successfully finished Verilog frontend. -5.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. +4.2. Continuing show pass. +Writing dot description to `mulshift.dot'. +Dumping module test to page 1. +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/selections' -5.16. Rerunning OPT passes. (Maybe there is more to do..) +End of script. Logfile hash: e40f1e9ccc, CPU: user 0.05s system 0.01s, MEM: 9.66 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 32% 3x clean (0 sec), 22% 1x techmap (0 sec), ... +../../../../yosys addshift_test.ys -5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \test.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2025 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \test. -Performed a total of 0 changes. +-- Executing script file `addshift_test.ys' -- -5.19. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\test'. -Removed a total of 0 cells. +1. Executing Verilog-2005 frontend: addshift_test.v +Parsing Verilog input from `addshift_test.v' to AST representation. +Generating RTLIL representation for module `\test'. +Successfully finished Verilog frontend. -5.20. Executing OPT_DFF pass (perform DFF optimizations). +2. Executing HIERARCHY pass (managing design hierarchy). -5.21. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. +2.1. Analyzing design hierarchy.. +Top module: \test -5.22. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. +2.2. Analyzing design hierarchy.. +Top module: \test +Removed 0 unused modules. -5.23. Finished OPT passes. (There is nothing left to do.) +3. Executing TECHMAP pass (map to technology primitives). -6. Generating Graphviz representation of design. -Writing dot description to `memory_01.dot'. -Dumping module test to page 1. +3.1. Executing Verilog-2005 frontend: addshift_map.v +Parsing Verilog input from `addshift_map.v' to AST representation. +Generating RTLIL representation for module `\$add'. +Successfully finished Verilog frontend. -End of script. Logfile hash: 3f34ade637, CPU: user 0.07s system 0.00s, MEM: 9.69 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 31% 5x opt_expr (0 sec), 20% 5x opt_clean (0 sec), ... +3.2. Continuing TECHMAP pass. +Using template $paramod$ba28896eb640c0d0dd7116971c6c5dc347170a6c\$add for cells of type $add. +No more expansions possible. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $or. @@ -37473,15 +37065,84 @@ 9. Executing SPLITNETS pass (splitting up multi-bit signals). -../../../../yosys -p 'script memory_02.ys; show -notitle -prefix memory_02 -format dot' + +Removed 0 unused cells and 7 unused wires. + +4. Generating Graphviz representation of design. +Writing dot description to `addshift.dot'. +Dumping module test to page 1. + +End of script. Logfile hash: 99575363c1, CPU: user 0.01s system 0.01s, MEM: 9.05 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 33% 1x clean (0 sec), 24% 1x techmap (0 sec), ... 10. Executing ABC pass (technology mapping using ABC). 10.1. Extracting gate netlist of module `\cmos_demo' to `/input.blif'.. +make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/techmap' Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs. 10.1.1. Executing ABC. +cd internals && TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' pdflatex overview_rtlil.tex --interaction=nonstopmode +cd internals && TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' pdflatex verilog_flow.tex --interaction=nonstopmode +This is pdfTeX, Version 3.141592653-2.6-1.40.26 (TeX Live 2025/dev/Debian) (preloaded format=pdflatex) + restricted \write18 enabled. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_blif /input.blif +ABC: + read_lib -w /docs/source/code_examples/show/../intro/mycells.lib +ABC: Parsing finished successfully. Parsing time = 0.00 sec +ABC: Warning: Templates are not defined. +ABC: Liberty parser cannot read "time_unit". Assuming time_unit : "1ns". +ABC: Liberty parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). +ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". +ABC: Library "demo" from "/docs/source/code_examples/show/../intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec +ABC: Memory = 0.00 MB. Time = 0.00 sec +ABC: + strash +ABC: + &get -n +ABC: + &fraig -x +ABC: + &put +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + &get -n +ABC: + &dch -f +ABC: + &nf +ABC: + &put +ABC: + write_blif /output.blif +10.1.2. Re-integrating ABC results. +ABC RESULTS: NOR cells: 3 +ABC RESULTS: NOT cells: 2 +ABC RESULTS: internal signals: 14 +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 2 +Removing temp directory. +Removed 0 unused cells and 1142 unused wires. + +11. Generating Graphviz representation of design. + +11.1. Executing Verilog-2005 frontend: ../intro/mycells.v +Parsing Verilog input from `../intro/mycells.v' to AST representation. +Generating RTLIL representation for module `\NOT'. +Generating RTLIL representation for module `\NAND'. +Generating RTLIL representation for module `\NOR'. +Generating RTLIL representation for module `\DFF'. +Successfully finished Verilog frontend. + +11.2. Continuing show pass. +Writing dot description to `cmos_01.dot'. +Dumping module cmos_demo to page 1. + +End of script. Logfile hash: 30a1c19366, CPU: user 0.22s system 0.03s, MEM: 12.36 MB peak +Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Time spent: 59% 2x abc (0 sec), 12% 7x read_verilog (0 sec), ... +../../../../yosys cmos.ys +entering extended mode +(./approach_flow.tex /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | @@ -37489,339 +37150,235 @@ \----------------------------------------------------------------------------/ Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) --- Running command `script memory_02.ys; show -notitle -prefix memory_02 -format dot' -- - --- Executing script file `memory_02.ys' -- +-- Executing script file `cmos.ys' -- -1. Executing Verilog-2005 frontend: memory_02.v -Parsing Verilog input from `memory_02.v' to AST representation. -Generating RTLIL representation for module `\test'. +1. Executing Verilog-2005 frontend: cmos.v +Parsing Verilog input from `cmos.v' to AST representation. +Generating RTLIL representation for module `\cmos_demo'. Successfully finished Verilog frontend. -2. Executing HIERARCHY pass (managing design hierarchy). +2. Executing PREP pass. -2.1. Analyzing design hierarchy.. -Top module: \test +2.1. Executing HIERARCHY pass (managing design hierarchy). -2.2. Analyzing design hierarchy.. -Top module: \test +2.1.1. Analyzing design hierarchy.. +Top module: \cmos_demo + +2.1.2. Analyzing design hierarchy.. +Top module: \cmos_demo Removed 0 unused modules. -3. Executing PROC pass (convert processes to netlists). +2.2. Executing PROC pass (convert processes to netlists). -3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. -3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 1 switch rules as full_case in process $proc$memory_02.v:17$10 in module test. -Marked 1 switch rules as full_case in process $proc$memory_02.v:13$3 in module test. +2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. -3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. -Promoted 8 assignments to connections. +Promoted 0 assignments to connections. -3.4. Executing PROC_INIT pass (extract init attributes). +2.2.4. Executing PROC_INIT pass (extract init attributes). -3.5. Executing PROC_ARST pass (detect async resets in processes). +2.2.5. Executing PROC_ARST pass (detect async resets in processes). -3.6. Executing PROC_ROM pass (convert switches to ROMs). +2.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. - - -3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\test.$proc$memory_02.v:24$19'. -Creating decoders for process `\test.$proc$memory_02.v:21$17'. -Creating decoders for process `\test.$proc$memory_02.v:17$10'. - 1/3: $1$memwr$\memory$memory_02.v:19$2_EN[7:0]$16 - 2/3: $1$memwr$\memory$memory_02.v:19$2_DATA[7:0]$15 - 3/3: $1$memwr$\memory$memory_02.v:19$2_ADDR[7:0]$14 -Creating decoders for process `\test.$proc$memory_02.v:13$3'. - 1/3: $1$memwr$\memory$memory_02.v:15$1_EN[7:0]$9 - 2/3: $1$memwr$\memory$memory_02.v:15$1_DATA[7:0]$8 - 3/3: $1$memwr$\memory$memory_02.v:15$1_ADDR[7:0]$7 - -3.8. Executing PROC_DLATCH pass (convert process syncs to latches). -3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\test.\RD2_DATA' using process `\test.$proc$memory_02.v:24$19'. - created $dff cell `$procdff$39' with positive edge clock. -Creating register for signal `\test.\RD1_DATA' using process `\test.$proc$memory_02.v:21$17'. - created $dff cell `$procdff$40' with positive edge clock. -Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_ADDR' using process `\test.$proc$memory_02.v:17$10'. - created $dff cell `$procdff$41' with positive edge clock. -Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_DATA' using process `\test.$proc$memory_02.v:17$10'. - created $dff cell `$procdff$42' with positive edge clock. -Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_EN' using process `\test.$proc$memory_02.v:17$10'. - created $dff cell `$procdff$43' with positive edge clock. -Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_ADDR' using process `\test.$proc$memory_02.v:13$3'. - created $dff cell `$procdff$44' with positive edge clock. -Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_DATA' using process `\test.$proc$memory_02.v:13$3'. - created $dff cell `$procdff$45' with positive edge clock. -Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_EN' using process `\test.$proc$memory_02.v:13$3'. - created $dff cell `$procdff$46' with positive edge clock. - -3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `test.$proc$memory_02.v:24$19'. -Removing empty process `test.$proc$memory_02.v:21$17'. -Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:17$10'. -Removing empty process `test.$proc$memory_02.v:17$10'. -Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:13$3'. -Removing empty process `test.$proc$memory_02.v:13$3'. -Cleaned up 2 empty switches. - -3.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. -Removed 6 unused cells and 26 unused wires. - -4. Executing MEMORY pass. - -4.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. - -4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). -Performed a total of 0 transformations. - -4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). - Analyzing test.memory write port 0. - Analyzing test.memory write port 1. +2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -4.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). +2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). -4.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Checking read port `\memory'[0] in module `\test': merging output FF to cell. -Checking read port `\memory'[1] in module `\test': merging output FF to cell. +2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -4.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. -Removed 2 unused cells and 18 unused wires. - +2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -4.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). -Consolidating read ports of memory test.memory by address: -Consolidating write ports of memory test.memory by address: -Consolidating write ports of memory test.memory using sat-based resource sharing: +2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. -4.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). -Performed a total of 0 transformations. +2.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module cmos_demo. -4.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. +2.3. Executing FUTURE pass. -4.10. Executing MEMORY_COLLECT pass (generating $mem cells). +2.4. Executing OPT_EXPR pass (perform const folding). -5. Executing OPT pass (performing simple optimizations). +LaTeX2e <2024-11-01> patch level 2 +L3 programming layer <2025-01-18> +(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.clsOptimizing module cmos_demo. -5.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. - +2.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \cmos_demo.. +Removed 0 unused cells and 1 unused wires. + -5.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\test'. -Removed a total of 0 cells. +2.6. Executing CHECK pass (checking for obvious problems). +Checking module cmos_demo... +Found and reported 0 problems. -5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \test.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - +2.7. Executing OPT pass (performing simple optimizations). -5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \test. - Consolidated identical input bits for $mux cell $procmux$31: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] - New connections: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [7:1] = { $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] } - Consolidated identical input bits for $mux cell $procmux$22: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] - New connections: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [7:1] = { $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] } - Optimizing cells in module \test. -Performed a total of 2 changes. +2.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module cmos_demo. -5.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\test'. +2.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\cmos_demo'. Removed a total of 0 cells. -5.6. Executing OPT_DFF pass (perform DFF optimizations). - -5.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. -Removed 0 unused cells and 4 unused wires. - - -5.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. - - -5.9. Rerunning OPT passes. (Maybe there is more to do..) - -5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \test.. +2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \cmos_demo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. -5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \test. +2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \cmos_demo. Performed a total of 0 changes. -5.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\test'. +2.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\cmos_demo'. Removed a total of 0 cells. -5.13. Executing OPT_DFF pass (perform DFF optimizations). - -5.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. -Removed 0 unused cells and 2 unused wires. - - -5.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. - -5.16. Rerunning OPT passes. (Maybe there is more to do..) - -5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \test.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. +2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \cmos_demo.. -5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \test. -Performed a total of 0 changes. +2.7.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module cmos_demo. -5.19. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\test'. -Removed a total of 0 cells. +2.7.8. Finished OPT passes. (There is nothing left to do.) -5.20. Executing OPT_DFF pass (perform DFF optimizations). +2.8. Executing WREDUCE pass (reducing word size of cells). -5.21. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \test.. +2.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \cmos_demo.. -5.22. Executing OPT_EXPR pass (perform const folding). -Optimizing module test. +2.10. Executing MEMORY_COLLECT pass (generating $mem cells). -5.23. Finished OPT passes. (There is nothing left to do.) +2.11. Executing OPT pass (performing simple optimizations). -6. Generating Graphviz representation of design. -Writing dot description to `memory_02.dot'. -Dumping module test to page 1. +2.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module cmos_demo. -End of script. Logfile hash: da34c3e279, CPU: user 0.08s system 0.01s, MEM: 8.96 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 27% 5x opt_expr (0 sec), 21% 5x opt_clean (0 sec), ... -../../../../yosys -p 'script techmap_01.ys; show -notitle -prefix techmap_01 -format dot' +2.11.2. Executing OPT_MERGE pass (detect identical cells). - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +Document Class: standalone 2025/02/22 v1.5a Class to compile TeX sub-files stan +dalone +(/usr/share/texlive/texmf-dist/tex/latex/tools/shellesc.styFinding identical cells in module `\cmos_demo'. +Removed a total of 0 cells. --- Running command `script techmap_01.ys; show -notitle -prefix techmap_01 -format dot' -- +2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +)Finding unused cells or wires in module \cmos_demo.. --- Executing script file `techmap_01.ys' -- +2.11.4. Finished fast OPT passes. -1. Executing Verilog-2005 frontend: techmap_01.v -Parsing Verilog input from `techmap_01.v' to AST representation. -Generating RTLIL representation for module `\test'. -Successfully finished Verilog frontend. +2.12. Printing statistics. -2. Executing HIERARCHY pass (managing design hierarchy). +=== cmos_demo === -2.1. Analyzing design hierarchy.. -Top module: \test + Number of wires: 3 + Number of wire bits: 4 + Number of public wires: 3 + Number of public wire bits: 4 + Number of ports: 3 + Number of port bits: 4 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1 + $add 1 -2.2. Analyzing design hierarchy.. -Top module: \test -Removed 0 unused modules. +2.13. Executing CHECK pass (checking for obvious problems). +Checking module cmos_demo... +Found and reported 0 problems. 3. Executing TECHMAP pass (map to technology primitives). -3.1. Executing Verilog-2005 frontend: techmap_01_map.v -Parsing Verilog input from `techmap_01_map.v' to AST representation. -Generating RTLIL representation for module `\$add'. +3.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v + +(/usr/share/texlive/texmf-dist/tex/generic/iftex/ifluatex.sty +(/usr/share/texlive/texmf-dist/tex/generic/iftex/iftex.styParsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. -Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\$add for cells of type $add. -No more expansions possible. - -Removed 0 unused cells and 7 unused wires. - -4. Generating Graphviz representation of design. -Writing dot description to `techmap_01.dot'. -Dumping module test to page 1. - -End of script. Logfile hash: 49c16386d9, CPU: user 0.02s system 0.01s, MEM: 9.00 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 33% 1x techmap (0 sec), 32% 1x clean (0 sec), ... -Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 -ABC: ABC command line: "source /abc.script". -ABC: -ABC: + read_blif /input.blif -ABC: + read_lib -w /docs/source/code_examples/show/../intro/mycells.lib -ABC: Parsing finished successfully. Parsing time = 0.00 sec -ABC: Warning: Templates are not defined. -ABC: Liberty parser cannot read "time_unit". Assuming time_unit : "1ns". -ABC: Liberty parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). -ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". -ABC: Library "demo" from "/docs/source/code_examples/show/../intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec -ABC: Memory = 0.00 MB. Time = 0.00 sec -ABC: + strash -ABC: + &get -n -ABC: + &fraig -x -ABC: + &put -ABC: + scorr -ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). -ABC: + dc2 -ABC: + dretime -ABC: + strash -ABC: + &get -n -ABC: + &dch -f -ABC: + &nf -ABC: + &put -ABC: + write_blif /output.blif - -10.1.2. Re-integrating ABC results. -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/synth_flow' -ABC RESULTS: NOR cells: 3 -ABC RESULTS: NOT cells: 2 -ABC RESULTS: internal signals: 14 -ABC RESULTS: input signals: 2 -ABC RESULTS: output signals: 2 -Removing temp directory. -Removed 0 unused cells and 1142 unused wires. +Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +This is pdfTeX, Version 3.141592653-2.6-1.40.26 (TeX Live 2025/dev/Debian) (preloaded format=pdflatex) + restricted \write18 enabled. +Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +)Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $and. +)This is pdfTeX, Version 3.141592653-2.6-1.40.26 (TeX Live 2025/dev/Debian) (preloaded format=pdflatex) + restricted \write18 enabled. -11. Generating Graphviz representation of design. +(/usr/share/texlive/texmf-dist/tex/latex/xkeyval/xkeyval.sty +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkeyval.tex +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkvutils.tex +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/keyval.tex))Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $or. +No more expansions possible. + -11.1. Executing Verilog-2005 frontend: ../intro/mycells.v -Parsing Verilog input from `../intro/mycells.v' to AST representation. -Generating RTLIL representation for module `\NOT'. -Generating RTLIL representation for module `\NAND'. -Generating RTLIL representation for module `\NOR'. -Generating RTLIL representation for module `\DFF'. -Successfully finished Verilog frontend. +4. Executing ABC pass (technology mapping using ABC). -11.2. Continuing show pass. -Writing dot description to `cmos_01.dot'. -Dumping module cmos_demo to page 1. +4.1. Extracting gate netlist of module `\cmos_demo' to `/input.blif'.. +Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs. -End of script. Logfile hash: 30a1c19366, CPU: user 0.22s system 0.02s, MEM: 12.37 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 59% 2x abc (0 sec), 13% 7x read_verilog (0 sec), ... -make[6]: Entering directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/techmap' -../../../../yosys red_or3x1_test.ys -cd primer && TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' pdflatex basics_abstractions.tex --interaction=nonstopmode -Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +4.1.1. Executing ABC. +)) +(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cfg) +(/usr/share/texlive/texmf-dist/tex/latex/base/article.cls +Document Class: article 2024/06/29 v1.4n Standard LaTeX document class +(/usr/share/texlive/texmf-dist/tex/latex/base/size12.clo)entering extended mode +(./overview_rtlil.tex)entering extended mode +(./verilog_flow.tex +LaTeX2e <2024-11-01> patch level 2 +L3 programming layer <2025-01-18> +(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cls +(/usr/share/texlive/texmf-dist/tex/latex/pgf/frontendlayer/tikz.sty +LaTeX2e <2024-11-01> patch level 2 +L3 programming layer <2025-01-18> +(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cls +(/usr/share/texlive/texmf-dist/tex/latex/pgf/basiclayer/pgf.sty +Document Class: standalone 2025/02/22 v1.5a Class to compile TeX sub-files stan +dalone +(/usr/share/texlive/texmf-dist/tex/latex/tools/shellesc.sty) +Document Class: standalone 2025/02/22 v1.5a Class to compile TeX sub-files stan +dalone +(/usr/share/texlive/texmf-dist/tex/latex/tools/shellesc.sty) +(/usr/share/texlive/texmf-dist/tex/latex/pgf/utilities/pgfrcs.sty +(/usr/share/texlive/texmf-dist/tex/generic/pgf/utilities/pgfutil-common.tex +(/usr/share/texlive/texmf-dist/tex/generic/iftex/ifluatex.sty) +(/usr/share/texlive/texmf-dist/tex/generic/pgf/utilities/pgfutil-latex.def +(/usr/share/texlive/texmf-dist/tex/generic/iftex/ifluatex.styRunning ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif @@ -37848,7 +37405,7 @@ ABC: + &put ABC: + write_blif /output.blif -10.1.2. Re-integrating ABC results. +4.1.2. Re-integrating ABC results. ABC RESULTS: NOR cells: 3 ABC RESULTS: NOT cells: 2 ABC RESULTS: internal signals: 14 @@ -37856,470 +37413,344 @@ ABC RESULTS: output signals: 2 Removing temp directory. - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `red_or3x1_test.ys' -- - -1. Executing Verilog-2005 frontend: red_or3x1_test.v -Parsing Verilog input from `red_or3x1_test.v' to AST representation. -Generating RTLIL representation for module `\test'. -Successfully finished Verilog frontend. - -2. Executing HIERARCHY pass (managing design hierarchy). - -2.1. Analyzing design hierarchy.. -Top module: \test - -2.2. Analyzing design hierarchy.. -Top module: \test -Removed 0 unused modules. - -3. Executing TECHMAP pass (map to technology primitives). - -3.1. Executing Verilog-2005 frontend: red_or3x1_map.v -Parsing Verilog input from `red_or3x1_map.v' to AST representation. -Generating RTLIL representation for module `\$reduce_or'. -Successfully finished Verilog frontend. - -3.2. Continuing TECHMAP pass. -Using template $paramod$53153ae57fdb25b25475408a64760d7986ecfb0e\$reduce_or for cells of type $reduce_or. -Using template $paramod$fe2472242c070f3b22e97f6c8c19c3569e575d97\$reduce_or for cells of type $reduce_or. -Removed 0 unused cells and 1142 unused wires. - -11. Generating Graphviz representation of design. - -11.1. Executing Verilog-2005 frontend: ../intro/mycells.v -Using template $paramod$1a3ccc6b2ad940e0a4ee2fb765a3adeb638fb7f0\$reduce_or for cells of type $reduce_or. -No more expansions possible. -Parsing Verilog input from `../intro/mycells.v' to AST representation. -Generating RTLIL representation for module `\NOT'. -Generating RTLIL representation for module `\NAND'. -Generating RTLIL representation for module `\NOR'. -Generating RTLIL representation for module `\DFF'. -Successfully finished Verilog frontend. - -11.2. Continuing show pass. -Writing dot description to `cmos_01.dot'. -Dumping module cmos_demo to page 1. - -End of script. Logfile hash: 30a1c19366, CPU: user 0.23s system 0.02s, MEM: 12.37 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 58% 2x abc (0 sec), 13% 7x read_verilog (0 sec), ... - -Removed 0 unused cells and 18 unused wires. - -4. Executing SPLITNETS pass (splitting up multi-bit signals). +(/usr/share/texlive/texmf-dist/tex/generic/iftex/iftex.styRemoved 0 unused cells and 36 unused wires. 5. Generating Graphviz representation of design. +))Writing dot description to `cmos_00.dot'. +Dumping module cmos_demo to page 1. -5.1. Executing Verilog-2005 frontend: red_or3x1_cells.v -Parsing Verilog input from `red_or3x1_cells.v' to AST representation. -Generating RTLIL representation for module `\OR3X1'. +6. Executing Verilog-2005 frontend: cmos.v +Parsing Verilog input from `cmos.v' to AST representation. +Generating RTLIL representation for module `\cmos_demo'. Successfully finished Verilog frontend. -5.2. Continuing show pass. -Writing dot description to `red_or3x1.dot'. -Dumping module test to page 1. -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/show' - -End of script. Logfile hash: d6e7304939, CPU: user 0.03s system 0.00s, MEM: 8.42 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 38% 1x techmap (0 sec), 22% 4x read_verilog (0 sec), ... -../../../../yosys sym_mul_test.ys - - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) - --- Executing script file `sym_mul_test.ys' -- - -1. Executing Verilog-2005 frontend: sym_mul_test.v -Parsing Verilog input from `sym_mul_test.v' to AST representation. -Generating RTLIL representation for module `\test'. -Successfully finished Verilog frontend. +7. Executing PREP pass. -2. Executing HIERARCHY pass (managing design hierarchy). +7.1. Executing HIERARCHY pass (managing design hierarchy). -2.1. Analyzing design hierarchy.. -Top module: \test +7.1.1. Analyzing design hierarchy.. +Top module: \cmos_demo -2.2. Analyzing design hierarchy.. -Top module: \test +7.1.2. Analyzing design hierarchy.. +Top module: \cmos_demo Removed 0 unused modules. -3. Executing TECHMAP pass (map to technology primitives). - -3.1. Executing Verilog-2005 frontend: sym_mul_map.v -Parsing Verilog input from `sym_mul_map.v' to AST representation. -Generating RTLIL representation for module `\$mul'. -Successfully finished Verilog frontend. - -3.2. Continuing TECHMAP pass. -Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul. -No more expansions possible. - -Removed 0 unused cells and 6 unused wires. +7.2. Executing PROC pass (convert processes to netlists). -4. Generating Graphviz representation of design. +7.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. -4.1. Executing Verilog-2005 frontend: sym_mul_cells.v -Parsing Verilog input from `sym_mul_cells.v' to AST representation. -Generating RTLIL representation for module `\MYMUL'. -Successfully finished Verilog frontend. +7.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. -4.2. Continuing show pass. -Writing dot description to `sym_mul.dot'. -Dumping module test to page 1. +7.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. -End of script. Logfile hash: 28982f840f, CPU: user 0.02s system 0.00s, MEM: 9.01 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 33% 1x clean (0 sec), 25% 4x read_verilog (0 sec), ... -../../../../yosys mymul_test.ys -cd primer && TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' pdflatex basics_parsetree.tex --interaction=nonstopmode +7.2.4. Executing PROC_INIT pass (extract init attributes). - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +7.2.5. Executing PROC_ARST pass (detect async resets in processes). +) +7.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. --- Executing script file `mymul_test.ys' -- +7.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -1. Executing Verilog-2005 frontend: mymul_test.v -Parsing Verilog input from `mymul_test.v' to AST representation. -Generating RTLIL representation for module `\test'. -Successfully finished Verilog frontend. +7.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). -2. Executing HIERARCHY pass (managing design hierarchy). +(/usr/share/texlive/texmf-dist/tex/generic/pgf/utilities/pgfrcs.code.tex +7.2.9. Executing PROC_DFF pass (convert process syncs to FFs). -2.1. Analyzing design hierarchy.. -Top module: \test +7.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -2.2. Analyzing design hierarchy.. -Top module: \test -Removed 0 unused modules. +7.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. -3. Executing TECHMAP pass (map to technology primitives). +7.2.12. Executing OPT_EXPR pass (perform const folding). -3.1. Executing Verilog-2005 frontend: sym_mul_map.v -Parsing Verilog input from `sym_mul_map.v' to AST representation. -Generating RTLIL representation for module `\$mul'. -Successfully finished Verilog frontend. +(/usr/share/texlive/texmf-dist/tex/generic/iftex/iftex.sty +(/usr/share/texlive/texmf-dist/tex/generic/pgf/pgf.revision.tex)Optimizing module cmos_demo. -3.2. Executing Verilog-2005 frontend: mymul_map.v -Parsing Verilog input from `mymul_map.v' to AST representation. -Generating RTLIL representation for module `\MYMUL'. -Successfully finished Verilog frontend. +7.3. Executing FUTURE pass. +))) +7.4. Executing OPT_EXPR pass (perform const folding). +)Optimizing module cmos_demo. -3.3. Continuing TECHMAP pass. -Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\$mul for cells of type $mul. -Using template $paramod\MYMUL\WIDTH=32'00000000000000000000000000000010 for cells of type MYMUL. -No more expansions possible. - -Removed 0 unused cells and 10 unused wires. -Renaming module \test to \test_mapped. +7.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \cmos_demo.. +Removed 0 unused cells and 1 unused wires. + -4. Executing Verilog-2005 frontend: mymul_test.v -Parsing Verilog input from `mymul_test.v' to AST representation. -Generating RTLIL representation for module `\test'. -Successfully finished Verilog frontend. +7.6. Executing CHECK pass (checking for obvious problems). +Checking module cmos_demo... +Found and reported 0 problems. -5. Executing MITER pass (creating miter circuit). -Creating miter cell "miter" with gold cell "test" and gate cell "test_mapped". +7.7. Executing OPT pass (performing simple optimizations). -6. Executing FLATTEN pass (flatten design). - +7.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module cmos_demo. -7. Executing SAT pass (solving SAT problems in the circuit). +7.7.2. Executing OPT_MERGE pass (detect identical cells). -Setting up SAT problem: -Final constraint equation: { } = { } -Imported 9 cells to SAT database. -Import proof-constraint: \trigger = 1'0 -Final proof equation: \trigger = 1'0 +(/usr/share/texlive/texmf-dist/tex/latex/xkeyval/xkeyval.styFinding identical cells in module `\cmos_demo'. +Removed a total of 0 cells. -Solving problem with 107 variables and 283 clauses.. -SAT proof finished - no model found: SUCCESS! +7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \cmos_demo.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. - /$$$$$$ /$$$$$$$$ /$$$$$$$ - /$$__ $$ | $$_____/ | $$__ $$ - | $$ \ $$ | $$ | $$ \ $$ - | $$ | $$ | $$$$$ | $$ | $$ - | $$ | $$ | $$__/ | $$ | $$ - | $$/$$ $$ | $$ | $$ | $$ - | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ - \____ $$$|__/|________/|__/|_______/|__/ - \__/ +7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \cmos_demo. +Performed a total of 0 changes. -8. Executing SPLITNETS pass (splitting up multi-bit signals). +7.7.5. Executing OPT_MERGE pass (detect identical cells). -9. Generating Graphviz representation of design. -Writing dot description to `mymul.dot'. -Dumping module test_mapped to page 1. +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkeyval.texFinding identical cells in module `\cmos_demo'. +Removed a total of 0 cells. -End of script. Logfile hash: 449524bce2, CPU: user 0.04s system 0.00s, MEM: 10.91 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 27% 2x clean (0 sec), 14% 1x techmap (0 sec), ... -../../../../yosys mulshift_test.ys +7.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkvutils.tex +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/keyval.tex)Finding unused cells or wires in module \cmos_demo.. --- Executing script file `mulshift_test.ys' -- +7.7.7. Executing OPT_EXPR pass (perform const folding). +) +(/usr/share/texlive/texmf-dist/tex/latex/pgf/basiclayer/pgfcore.styOptimizing module cmos_demo. -1. Executing Verilog-2005 frontend: mulshift_test.v -Parsing Verilog input from `mulshift_test.v' to AST representation. -Generating RTLIL representation for module `\test'. -Successfully finished Verilog frontend. +7.7.8. Finished OPT passes. (There is nothing left to do.) -2. Executing HIERARCHY pass (managing design hierarchy). +7.8. Executing WREDUCE pass (reducing word size of cells). +) +7.9. Executing OPT_CLEAN pass (remove unused cells and wires). -2.1. Analyzing design hierarchy.. -Top module: \test +(/usr/share/texlive/texmf-dist/tex/latex/xkeyval/xkeyval.sty) +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkeyval.texFinding unused cells or wires in module \cmos_demo.. -2.2. Analyzing design hierarchy.. -Top module: \test -Removed 0 unused modules. +7.10. Executing MEMORY_COLLECT pass (generating $mem cells). -3. Executing TECHMAP pass (map to technology primitives). +7.11. Executing OPT pass (performing simple optimizations). -3.1. Executing Verilog-2005 frontend: sym_mul_map.v -Parsing Verilog input from `sym_mul_map.v' to AST representation. -Generating RTLIL representation for module `\$mul'. -Successfully finished Verilog frontend. +7.11.1. Executing OPT_EXPR pass (perform const folding). -3.2. Executing Verilog-2005 frontend: mulshift_map.v -Parsing Verilog input from `mulshift_map.v' to AST representation. -Generating RTLIL representation for module `\MYMUL'. -Successfully finished Verilog frontend. +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkvutils.tex +(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/keyval.tex)Optimizing module cmos_demo. +) +7.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\cmos_demo'. +Removed a total of 0 cells. -3.3. Continuing TECHMAP pass. -Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul. -Using template $paramod$fb3c811cfd9dc2fc74fe40190dfcd365f04584f7\MYMUL for cells of type MYMUL. -No more expansions possible. - -Removed 0 unused cells and 16 unused wires. +7.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +)Finding unused cells or wires in module \cmos_demo.. -4. Generating Graphviz representation of design. +7.11.4. Finished fast OPT passes. +) +7.12. Printing statistics. -4.1. Executing Verilog-2005 frontend: sym_mul_cells.v -Parsing Verilog input from `sym_mul_cells.v' to AST representation. -Generating RTLIL representation for module `\MYMUL'. -Successfully finished Verilog frontend. +=== cmos_demo === -4.2. Continuing show pass. -Writing dot description to `mulshift.dot'. -Dumping module test to page 1. + Number of wires: 3 + Number of wire bits: 4 + Number of public wires: 3 + Number of public wire bits: 4 + Number of ports: 3 + Number of port bits: 4 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1 + $add 1 -End of script. Logfile hash: e40f1e9ccc, CPU: user 0.05s system 0.00s, MEM: 9.67 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 31% 3x clean (0 sec), 23% 1x techmap (0 sec), ... -../../../../yosys addshift_test.ys +7.13. Executing CHECK pass (checking for obvious problems). +Checking module cmos_demo... +Found and reported 0 problems. - /----------------------------------------------------------------------------\ - | yosys -- Yosys Open SYnthesis Suite | - | Copyright (C) 2012 - 2025 Claire Xenia Wolf | - | Distributed under an ISC-like license, type "license" to see terms | - \----------------------------------------------------------------------------/ - Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) +8. Executing TECHMAP pass (map to technology primitives). --- Executing script file `addshift_test.ys' -- +8.1. Executing Verilog-2005 frontend: /build/reproducible-path/yosys-0.52/share/techmap.v -1. Executing Verilog-2005 frontend: addshift_test.v -Parsing Verilog input from `addshift_test.v' to AST representation. -Generating RTLIL representation for module `\test'. +(/usr/share/texlive/texmf-dist/tex/latex/graphics/graphicx.sty +(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cfg +(/usr/share/texlive/texmf-dist/tex/latex/graphics/graphics.sty) +(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cfg) +(/usr/share/texlive/texmf-dist/tex/latex/graphics/trig.sty)Parsing Verilog input from `/build/reproducible-path/yosys-0.52/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. -2. Executing HIERARCHY pass (managing design hierarchy). - -2.1. Analyzing design hierarchy.. -Top module: \test - -2.2. Analyzing design hierarchy.. -Top module: \test -Removed 0 unused modules. - -3. Executing TECHMAP pass (map to technology primitives). - -3.1. Executing Verilog-2005 frontend: addshift_map.v -Parsing Verilog input from `addshift_map.v' to AST representation. -Generating RTLIL representation for module `\$add'. -Successfully finished Verilog frontend. +8.2. Continuing TECHMAP pass. +Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. +Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $pos. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $mux. -3.2. Continuing TECHMAP pass. -Using template $paramod$ba28896eb640c0d0dd7116971c6c5dc347170a6c\$add for cells of type $add. +(/usr/share/texlive/texmf-dist/tex/latex/graphics-cfg/graphics.cfg +(/usr/share/texlive/texmf-dist/tex/latex/base/article.cls) +Document Class: article 2024/06/29 v1.4n Standard LaTeX document class +(/usr/share/texlive/texmf-dist/tex/latex/base/size12.clo +(/usr/share/texlive/texmf-dist/tex/latex/graphics-def/pdftex.def +(/usr/share/texlive/texmf-dist/tex/latex/base/article.cls) +Document Class: article 2024/06/29 v1.4n Standard LaTeX document class +(/usr/share/texlive/texmf-dist/tex/latex/base/size12.cloUsing template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $or. No more expansions possible. - -Removed 0 unused cells and 7 unused wires. + -4. Generating Graphviz representation of design. -Writing dot description to `addshift.dot'. -Dumping module test to page 1. +9. Executing SPLITNETS pass (splitting up multi-bit signals). +)) +10. Executing ABC pass (technology mapping using ABC). -End of script. Logfile hash: 99575363c1, CPU: user 0.02s system 0.01s, MEM: 9.06 MB peak -Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 33% 1x clean (0 sec), 24% 1x techmap (0 sec), ... -make[6]: Leaving directory '/build/reproducible-path/yosys-0.52/docs/source/code_examples/techmap' -cd primer && TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' pdflatex basics_ast.tex --interaction=nonstopmode -This is pdfTeX, Version 3.141592653-2.6-1.40.26 (TeX Live 2025/dev/Debian) (preloaded format=pdflatex) - restricted \write18 enabled. -This is pdfTeX, Version 3.141592653-2.6-1.40.26 (TeX Live 2025/dev/Debian) (preloaded format=pdflatex) - restricted \write18 enabled. -entering extended mode -(./basics_abstractions.tex -LaTeX2e <2024-11-01> patch level 2 -L3 programming layer <2025-01-18> -(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cls -Document Class: standalone 2025/02/22 v1.5a Class to compile TeX sub-files stan -dalone -(/usr/share/texlive/texmf-dist/tex/latex/tools/shellesc.sty) -(/usr/share/texlive/texmf-dist/tex/generic/iftex/ifluatex.styentering extended mode -(./basics_parsetree.tex -(/usr/share/texlive/texmf-dist/tex/generic/iftex/iftex.sty) -LaTeX2e <2024-11-01> patch level 2 -L3 programming layer <2025-01-18> -(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cls)This is pdfTeX, Version 3.141592653-2.6-1.40.26 (TeX Live 2025/dev/Debian) (preloaded format=pdflatex) - restricted \write18 enabled. +10.1. Extracting gate netlist of module `\cmos_demo' to `/input.blif'.. +Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs. -(/usr/share/texlive/texmf-dist/tex/latex/xkeyval/xkeyval.sty -Document Class: standalone 2025/02/22 v1.5a Class to compile TeX sub-files stan -dalone -(/usr/share/texlive/texmf-dist/tex/latex/tools/shellesc.sty) -(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkeyval.tex -(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkvutils.tex -(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/keyval.tex)))) -(/usr/share/texlive/texmf-dist/tex/generic/iftex/ifluatex.sty -(/usr/share/texlive/texmf-dist/tex/generic/iftex/iftex.sty) -(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cfg)) -(/usr/share/texlive/texmf-dist/tex/latex/xkeyval/xkeyval.sty -(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkeyval.tex -(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/xkvutils.tex -(/usr/share/texlive/texmf-dist/tex/generic/xkeyval/keyval.tex))) -(/usr/share/texlive/texmf-dist/tex/latex/base/article.cls) -Document Class: article 2024/06/29 v1.4n Standard LaTeX document class -(/usr/share/texlive/texmf-dist/tex/latex/base/size12.clo) -(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cfg))entering extended mode -(./basics_ast.tex -(/usr/share/texlive/texmf-dist/tex/latex/pgf/frontendlayer/tikz.sty -(/usr/share/texlive/texmf-dist/tex/latex/base/article.cls -(/usr/share/texlive/texmf-dist/tex/latex/pgf/basiclayer/pgf.sty -LaTeX2e <2024-11-01> patch level 2 -L3 programming layer <2025-01-18> -(/usr/share/texlive/texmf-dist/tex/latex/standalone/standalone.cls -Document Class: article 2024/06/29 v1.4n Standard LaTeX document class -(/usr/share/texlive/texmf-dist/tex/latex/base/size12.clo -(/usr/share/texlive/texmf-dist/tex/latex/pgf/utilities/pgfrcs.sty) -(/usr/share/texlive/texmf-dist/tex/generic/pgf/utilities/pgfutil-common.tex -Document Class: standalone 2025/02/22 v1.5a Class to compile TeX sub-files stan -dalone -(/usr/share/texlive/texmf-dist/tex/latex/tools/shellesc.sty)) -(/usr/share/texlive/texmf-dist/tex/generic/pgf/utilities/pgfutil-latex.def)) -(/usr/share/texlive/texmf-dist/tex/generic/pgf/utilities/pgfrcs.code.tex -(/usr/share/texlive/texmf-dist/tex/generic/pgf/pgf.revision.tex))) -(/usr/share/texlive/texmf-dist/tex/generic/iftex/ifluatex.sty +10.1.1. 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+(/usr/share/texlive/texmf-dist/tex/latex/graphics-def/pdftex.defRunning ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_blif /input.blif +ABC: + read_lib -w /docs/source/code_examples/show/../intro/mycells.lib +ABC: Parsing finished successfully. Parsing time = 0.00 sec +ABC: Warning: Templates are not defined. +ABC: Liberty parser cannot read "time_unit". Assuming time_unit : "1ns". +ABC: Liberty parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). +ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". +ABC: Library "demo" from "/docs/source/code_examples/show/../intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec +ABC: Memory = 0.00 MB. Time = 0.00 sec +ABC: + strash +ABC: + &get -n +ABC: + &fraig -x +ABC: + &put +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + &get -n +ABC: + &dch -f +ABC: + &nf +ABC: + &put +ABC: + write_blif /output.blif + +10.1.2. Re-integrating ABC results. +ABC RESULTS: NOR cells: 3 +ABC RESULTS: NOT cells: 2 +ABC RESULTS: internal signals: 14 +ABC RESULTS: input signals: 2 +ABC RESULTS: output signals: 2 +Removing temp directory. + (/usr/share/texlive/texmf-dist/tex/latex/xcolor/xcolor.styRemoved 0 unused cells and 1142 unused wires. + +11. Generating Graphviz representation of design. + +11.1. Executing Verilog-2005 frontend: ../intro/mycells.v +Parsing Verilog input from `../intro/mycells.v' to AST representation. +Generating RTLIL representation for module `\NOT'. +Generating RTLIL representation for module `\NAND'. +Generating RTLIL representation for module `\NOR'. +Generating RTLIL representation for module `\DFF'. +Successfully finished Verilog frontend. + +11.2. Continuing show pass. +Writing dot description to `cmos_01.dot'. +Dumping module cmos_demo to page 1. + +End of script. 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Leaving directory '/build/reproducible-path/yosys-0.52/docs' make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/docs' @@ -41607,9 +41048,9 @@ checking consistency... done preparing documents... done copying assets... -copying TeX support files... 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[198] LaTeX Warning: Hyper reference `cmd/hierarchy:cmd-hierarchy' on page 199 undefi -ned on input line 13353. +ned on input line 13358. [199] LaTeX Warning: Hyper reference `cmd/read_verilog:cmd-read_verilog' on page 200 -undefined on input line 13381. +undefined on input line 13386. LaTeX Warning: Hyper reference `cmd/read_verilog:cmd-read_verilog' on page 200 -undefined on input line 13433. +undefined on input line 13438. LaTeX Warning: Hyper reference `cmd/read_verilog:cmd-read_verilog' on page 200 -undefined on input line 13465. +undefined on input line 13470. [200] @@ -46316,11 +45757,11 @@ Chapter 5. LaTeX Warning: Hyper reference `appendix/primer:fig-basics-abstractions' on pag -e 205 undefined on input line 13766. +e 205 undefined on input line 13771. LaTeX Warning: Reference `appendix/primer:fig-basics-abstractions' on page 205 -undefined on input line 13766. +undefined on input line 13771. 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[213] LaTeX Warning: Hyper reference `appendix/primer:fig-basics-ast' on page 214 und -efined on input line 14530. +efined on input line 14535. LaTeX Warning: Reference `appendix/primer:fig-basics-ast' on page 214 undefined - on input line 14530. + on input line 14535. LaTeX Warning: Hyper reference `appendix/primer:fig-basics-parsetree' on page 2 -14 undefined on input line 14531. +14 undefined on input line 14536. LaTeX Warning: Reference `appendix/primer:fig-basics-parsetree' on page 214 und -efined on input line 14531. +efined on input line 14536. [214 <./basics_parsetree.pdf> <./basics_ast.pdf>] @@ -46384,29 +45825,29 @@ [218] LaTeX Warning: Hyper reference `yosys_internals/formats/rtlil_rep:sec-rtlil-sig -spec' on page 219 undefined on input line 14925. +spec' on page 219 undefined on input line 14930. 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[259] +LaTeX Warning: Hyper reference `cell/word_mux:mux._mux' on page 260 undefined o +n input line 18471. + + LaTeX Warning: Hyper reference `cell/properties:is_evaluable' on page 260 undef -ined on input line 18614. +ined on input line 18475. -LaTeX Warning: Hyper reference `cell/properties:x-output' on page 260 undefined - on input line 18618. +[260] +LaTeX Warning: Hyper reference `cell/properties:is_evaluable' on page 261 undef +ined on input line 18525. -LaTeX Warning: Hyper reference `cell/properties:is_evaluable' on page 260 undef -ined on input line 18686. +LaTeX Warning: Hyper reference `cell/properties:is_evaluable' on page 261 undef +ined on input line 18575. -[260] -LaTeX Warning: Hyper reference `cell/word_reg:reg._sr' on page 261 undefined on - input line 18724. +[261] +LaTeX Warning: Hyper reference `cell/properties:is_evaluable' on page 262 undef +ined on input line 18624. -LaTeX Warning: Hyper reference `cell/word_reg:reg._sr' on page 261 undefined on - input line 18746. +LaTeX Warning: Hyper reference `cell/properties:x-output' on page 262 undefined + on input line 18628. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dff' on page 261 undefined o -n input line 18750. +LaTeX Warning: Hyper reference `cell/properties:is_evaluable' on page 262 undef +ined on input line 18696. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dff' on page 261 undefined o -n input line 18752. +[262] -LaTeX Warning: Hyper reference `cell/word_reg:reg._adff' on page 261 undefined -on input line 18766. +LaTeX Warning: Hyper reference `cell/word_reg:reg._sr' on page 263 undefined on + input line 18734. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dff' on page 261 undefined o -n input line 18767. +LaTeX Warning: Hyper reference `cell/word_reg:reg._sr' on page 263 undefined on + input line 18756. -LaTeX Warning: Hyper reference `cmd/proc:cmd-proc' on page 261 undefined on inp -ut line 18783. +LaTeX Warning: Hyper reference `cell/word_reg:reg._dff' on page 263 undefined o +n input line 18760. -LaTeX Warning: Hyper reference `cell/word_reg:reg._sdff' on page 261 undefined -on input line 18787. +LaTeX Warning: Hyper reference `cell/word_reg:reg._dff' on page 263 undefined o +n input line 18762. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dff' on page 261 undefined o -n input line 18788. +LaTeX Warning: Hyper reference `cell/word_reg:reg._adff' on page 263 undefined +on input line 18776. -[261] +LaTeX Warning: Hyper reference `cell/word_reg:reg._dff' on page 263 undefined o +n input line 18777. -LaTeX Warning: Hyper reference `cell/word_reg:reg._adff' on page 262 undefined -on input line 18804. +LaTeX Warning: Hyper reference `cmd/proc:cmd-proc' on page 263 undefined on inp +ut line 18793. -LaTeX Warning: Hyper reference `cell/word_reg:reg._sdff' on page 262 undefined -on input line 18804. +LaTeX Warning: Hyper reference `cell/word_reg:reg._sdff' on page 263 undefined +on input line 18797. -LaTeX Warning: Hyper reference `cell/word_reg:reg._aldff' on page 262 undefined - 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on input line 18830. +LaTeX Warning: Hyper reference `cell/word_reg:reg._sdffe' on page 264 undefined + on input line 18839. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dffsr' on page 262 undefined - on input line 18830. +LaTeX Warning: Hyper reference `cell/word_reg:reg._sdffce' on page 264 undefine +d on input line 18839. -LaTeX Warning: Hyper reference `cell/word_reg:reg._sdff' on page 262 undefined -on input line 18830. +LaTeX Warning: Hyper reference `cell/word_reg:reg._dff' on page 264 undefined o +n input line 18839. -LaTeX Warning: Hyper reference `cell/word_reg:reg._sdff' on page 262 undefined -on input line 18830. +LaTeX Warning: Hyper reference `cell/word_reg:reg._adff' on page 264 undefined +on input line 18840. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dlatch' on page 262 undefine -d on input line 18843. +LaTeX Warning: Hyper reference `cell/word_reg:reg._aldff' on page 264 undefined + on input line 18840. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dlatch' on page 262 undefine -d on input line 18845. +LaTeX Warning: Hyper reference `cell/word_reg:reg._dffsr' on page 264 undefined + on input line 18840. -LaTeX Warning: Hyper reference `cell/word_reg:reg._adlatch' on page 262 undefin -ed on input line 18862. +LaTeX Warning: Hyper reference `cell/word_reg:reg._sdff' on page 264 undefined +on input line 18840. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dlatch' on page 262 undefine -d on input line 18863. +LaTeX Warning: Hyper reference `cell/word_reg:reg._sdff' on page 264 undefined +on input line 18840. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dlatchsr' on page 262 undefi -ned on input line 18878. +LaTeX Warning: Hyper reference `cell/word_reg:reg._dlatch' on page 264 undefine +d on input line 18853. -LaTeX Warning: Hyper reference `cell/word_reg:reg._dlatch' on page 262 undefine -d on input line 18879. +LaTeX Warning: Hyper reference `cell/word_reg:reg._dlatch' on page 264 undefine +d on input line 18855. -LaTeX Warning: Hyper reference `cell/word_reg:reg._sr' on page 262 undefined on - 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LaTeX Warning: Hyper reference `cell/gate_reg_ff:reg_ff.__DFFSRE_PPNP_' on page - 324 undefined on input line 25193. + 326 undefined on input line 25203. LaTeX Warning: Hyper reference `cell/gate_reg_ff:reg_ff.__DFFSRE_PPPN_' on page - 324 undefined on input line 25193. + 326 undefined on input line 25203. LaTeX Warning: Hyper reference `cell/gate_reg_ff:reg_ff.__DFFSRE_PPPP_' on page - 324 undefined on input line 25193. + 326 undefined on input line 25203. -[324] -[325] [326] [327] [328] @@ -49001,197 +48440,197 @@ [372] [373] [374] +[375] +[376] LaTeX Warning: Hyper reference `cell/gate_reg_latch:reg_latch.__DLATCH_N_' on p -age 375 undefined on input line 30183. +age 377 undefined on input line 30193. LaTeX Warning: Hyper reference `cell/gate_reg_latch:reg_latch.__DLATCH_P_' on p -age 375 undefined on input line 30183. +age 377 undefined on input line 30193. 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-LaTeX Warning: Hyper reference `cmd/show:cmd-show' on page 390 undefined on inp -ut line 31804. - +[391] -LaTeX Warning: Hyper reference `cmd/viz:cmd-viz' on page 390 undefined on input - line 31804. +LaTeX Warning: Hyper reference `cmd/show:cmd-show' on page 392 undefined on inp +ut line 31814. -[390] -[391] -Underfull \vbox (badness 10000) detected at line 32041 +LaTeX Warning: Hyper reference `cmd/viz:cmd-viz' on page 392 undefined on input + line 31814. -Overfull \vbox (0.56999pt too high) detected at line 32041 [392] -Underfull \vbox (badness 10000) detected at line 32041 - -Overfull \vbox (0.56999pt too high) detected at line 32041 - [393] -Overfull \vbox (2.84741pt too high) detected at line 32199 +Underfull \vbox (badness 10000) detected at line 32051 + +Overfull \vbox (0.56999pt too high) detected at line 32051 [394] -Underfull \vbox (badness 10000) detected at line 32199 +Underfull \vbox (badness 10000) detected at line 32051 -Overfull \vbox (0.56999pt too high) detected at line 32199 +Overfull \vbox (0.56999pt too high) detected at line 32051 [395] -Underfull \vbox (badness 10000) detected at line 32199 - -Overfull \vbox (0.56999pt too high) detected at line 32199 +Overfull \vbox (2.84741pt too high) detected at line 32209 [396] +Underfull \vbox (badness 10000) detected at line 32209 + +Overfull \vbox (0.56999pt too high) detected at line 32209 + [397] -Underfull \vbox (badness 10000) detected at line 32305 +Underfull \vbox (badness 10000) detected at line 32209 -Underfull \vbox (badness 10000) detected at line 32305 +Overfull \vbox (0.56999pt too high) detected at line 32209 [398] -Overfull \vbox (2.84741pt too high) detected at line 32403 - [399] -Underfull \vbox (badness 10000) detected at line 32403 +Underfull \vbox (badness 10000) detected at line 32315 -Overfull \vbox (0.56999pt too high) detected at line 32403 +Underfull \vbox (badness 10000) detected at line 32315 [400] +Overfull \vbox (2.84741pt too high) detected at line 32413 + [401] -[402] -Overfull \vbox (2.84741pt too high) detected at line 32587 +Underfull \vbox (badness 10000) detected at line 32413 +Overfull \vbox (0.56999pt too high) detected at line 32413 + +[402] [403] [404] -[405] -Overfull \vbox (2.84741pt too high) detected at line 32828 +Overfull \vbox (2.84741pt too high) detected at line 32597 +[405] [406] [407] +Overfull \vbox (2.84741pt too high) detected at line 32838 + [408] [409] [410] [411] -Overfull \vbox (1.94772pt too high) detected at line 33272 - [412] -Overfull \vbox (2.84741pt too high) detected at line 33334 - [413] +Overfull \vbox (1.94772pt too high) detected at line 33282 + [414] +Overfull \vbox (2.84741pt too high) detected at line 33344 + [415] [416] -Overfull \vbox (1.94772pt too high) detected at line 33667 - [417] [418] +Overfull \vbox (1.94772pt too high) detected at line 33677 + [419] [420] [421] [422] -Overfull \vbox (1.94772pt too high) detected at line 34144 - [423] -Overfull \vbox (2.84741pt too high) detected at line 34187 - [424] +Overfull \vbox (1.94772pt too high) detected at line 34154 + [425] +Overfull \vbox (2.84741pt too high) detected at line 34197 + [426] [427] [428] @@ -49325,51 +48764,51 @@ [430] [431] [432] -Overfull \vbox (1.94772pt too high) detected at line 34893 - [433] -Overfull \vbox (2.84741pt too high) detected at line 34993 - [434] +Overfull \vbox (1.94772pt too high) detected at line 34903 + [435] +Overfull \vbox (2.84741pt too high) detected at line 35003 + [436] [437] -Overfull \vbox (2.84741pt too high) detected at line 35231 - [438] [439] -Overfull \vbox (1.94772pt too high) detected at line 35378 +Overfull \vbox (2.84741pt too high) detected at line 35241 [440] [441] -Overfull \vbox (1.94772pt too high) detected at line 35511 +Overfull \vbox (1.94772pt too high) detected at line 35388 [442] [443] +Overfull \vbox (1.94772pt too high) detected at line 35521 + [444] [445] [446] -Underfull \vbox (badness 10000) detected at line 35893 - -Overfull \vbox (0.56999pt too high) detected at line 35893 - [447] [448] -Underfull \vbox (badness 10000) detected at line 36040 +Underfull \vbox (badness 10000) detected at line 35903 -Overfull \vbox (0.56999pt too high) detected at line 36040 +Overfull \vbox (0.56999pt too high) detected at line 35903 [449] [450] +Underfull \vbox (badness 10000) detected at line 36050 + +Overfull \vbox (0.56999pt too high) detected at line 36050 + [451] [452] [453] [454] [455] -Overfull \vbox (1.94772pt too high) detected at line 36628 - [456] [457] +Overfull \vbox (1.94772pt too high) detected at line 36638 + [458] [459] [460] @@ -49377,15 +48816,15 @@ [462] [463] [464] -Overfull \vbox (2.84741pt too high) detected at line 37362 - [465] -Underfull \vbox (badness 10000) detected at line 37362 - -Overfull \vbox (0.56999pt too high) detected at line 37362 - [466] +Overfull \vbox (2.84741pt too high) detected at line 37372 + [467] +Underfull \vbox (badness 10000) detected at line 37372 + +Overfull \vbox (0.56999pt too high) detected at line 37372 + [468] [469] [470] @@ -49397,4175 +48836,4177 @@ [476] [477] [478] -Overfull \vbox (1.94772pt too high) detected at line 38409 - [479] [480] +Overfull \vbox (1.94772pt too high) detected at line 38419 + [481] [482] [483] [484] -Overfull \vbox (2.84741pt too high) detected at line 38933 - [485] [486] +Overfull \vbox (2.84741pt too high) detected at line 38943 + [487] [488] -Underfull \vbox (badness 10000) detected at line 39254 - -Overfull \vbox (0.56999pt too high) detected at line 39254 - [489] -Underfull \vbox (badness 10000) detected at line 39254 +[490] +Underfull \vbox (badness 10000) detected at line 39264 -Overfull \vbox (0.56999pt too high) detected at line 39254 +Overfull \vbox (0.56999pt too high) detected at line 39264 -[490] [491] -[492] -[493] -Underfull \vbox (badness 10000) detected at line 39617 +Underfull \vbox (badness 10000) detected at line 39264 -Overfull \vbox (0.56999pt too high) detected at line 39617 +Overfull \vbox (0.56999pt too high) detected at line 39264 +[492] +[493] [494] -Underfull \vbox (badness 10000) detected at line 39617 +[495] +Underfull \vbox (badness 10000) detected at line 39627 -Overfull \vbox (0.56999pt too high) detected at line 39617 +Overfull \vbox (0.56999pt too high) detected at line 39627 -[495] [496] -[497] -Overfull \vbox (1.94772pt too high) detected at line 39779 +Underfull \vbox (badness 10000) detected at line 39627 -[498] -Overfull \vbox (2.84741pt too high) detected at line 40027 +Overfull \vbox (0.56999pt too high) detected at line 39627 +[497] +[498] [499] -Underfull \vbox (badness 10000) detected at line 40027 - -Overfull \vbox (0.56999pt too high) detected at line 40027 +Overfull \vbox (1.94772pt too high) detected at line 39789 [500] -Underfull \vbox (badness 10000) detected at line 40027 - -Overfull \vbox (0.56999pt too high) detected at line 40027 +Overfull \vbox (2.84741pt too high) detected at line 40037 [501] -Underfull \vbox (badness 10000) detected at line 40027 +Underfull \vbox (badness 10000) detected at line 40037 -Overfull \vbox (0.56999pt too high) detected at line 40027 +Overfull \vbox (0.56999pt too high) detected at line 40037 [502] +Underfull \vbox (badness 10000) detected at line 40037 + +Overfull \vbox (0.56999pt too high) detected at line 40037 + [503] +Underfull \vbox (badness 10000) detected at line 40037 + +Overfull \vbox (0.56999pt too high) detected at line 40037 + [504] [505] [506] -Underfull \vbox (badness 10000) detected at line 40349 - -Overfull \vbox (0.56999pt too high) detected at line 40349 - [507] -Overfull \vbox (2.84741pt too high) detected at line 40419 - [508] -Overfull \vbox (2.84741pt too high) detected at line 40548 +Underfull \vbox (badness 10000) detected at line 40359 -[509] -Underfull \vbox (badness 10000) detected at line 40548 +Overfull \vbox (0.56999pt too high) detected at line 40359 -Overfull \vbox (0.56999pt too high) detected at line 40548 +[509] +Overfull \vbox (2.84741pt too high) detected at line 40429 [510] +Overfull \vbox (2.84741pt too high) detected at line 40558 + [511] -Overfull \vbox (1.94772pt too high) detected at line 40660 +Underfull \vbox (badness 10000) detected at line 40558 + +Overfull \vbox (0.56999pt too high) detected at line 40558 [512] [513] -[514] -Overfull \vbox (1.94772pt too high) detected at line 40946 +Overfull \vbox (1.94772pt too high) detected at line 40670 +[514] [515] -Underfull \vbox (badness 10000) detected at line 40946 - -Overfull \vbox (0.56999pt too high) detected at line 40946 - [516] -Overfull \vbox (2.84741pt too high) detected at line 41031 +Overfull \vbox (1.94772pt too high) detected at line 40956 [517] -Overfull \vbox (2.84741pt too high) detected at line 41140 +Underfull \vbox (badness 10000) detected at line 40956 -[518] -Underfull \vbox (badness 10000) detected at line 41140 +Overfull \vbox (0.56999pt too high) detected at line 40956 -Overfull \vbox (0.56999pt too high) detected at line 41140 +[518] +Overfull \vbox (2.84741pt too high) detected at line 41041 [519] -Overfull \vbox (2.84741pt too high) detected at line 41240 +Overfull \vbox (2.84741pt too high) detected at line 41150 [520] -Underfull \vbox (badness 10000) detected at line 41240 +Underfull \vbox (badness 10000) detected at line 41150 -Overfull \vbox (0.56999pt too high) detected at line 41240 +Overfull \vbox (0.56999pt too high) detected at line 41150 [521] -Overfull \vbox (2.84741pt too high) detected at line 41320 +Overfull \vbox (2.84741pt too high) detected at line 41250 [522] -Overfull \vbox (2.84741pt too high) detected at line 41498 +Underfull \vbox (badness 10000) detected at line 41250 -[523] -Underfull \vbox (badness 10000) detected at line 41498 +Overfull \vbox (0.56999pt too high) detected at line 41250 -Overfull \vbox (0.56999pt too high) detected at line 41498 +[523] +Overfull \vbox (2.84741pt too high) detected at line 41330 [524] -Underfull \vbox (badness 10000) detected at line 41498 - -Overfull \vbox (0.56999pt too high) detected at line 41498 +Overfull \vbox (2.84741pt too high) detected at line 41508 [525] -[526] -[527] -Overfull \vbox (2.84741pt too high) detected at line 41784 +Underfull \vbox (badness 10000) detected at line 41508 -[528] -Underfull \vbox (badness 10000) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41508 -Overfull \vbox (0.56999pt too high) detected at line 41784 +[526] +Underfull \vbox (badness 10000) detected at line 41508 -[529] -Underfull \vbox (badness 10000) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41508 -Overfull \vbox (0.56999pt too high) detected at line 41784 +[527] +[528] +[529] +Overfull \vbox (2.84741pt too high) detected at line 41794 [530] -Underfull \vbox (badness 10000) detected at line 41784 +Underfull \vbox (badness 10000) detected at line 41794 -Overfull \vbox (0.56999pt too high) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41794 [531] -Overfull \vbox (2.84741pt too high) detected at line 41947 +Underfull \vbox (badness 10000) detected at line 41794 + +Overfull \vbox (0.56999pt too high) detected at line 41794 [532] -Underfull \vbox (badness 10000) detected at line 41947 +Underfull \vbox (badness 10000) detected at line 41794 -Overfull \vbox (0.56999pt too high) detected at line 41947 +Overfull \vbox (0.56999pt too high) detected at line 41794 [533] -Underfull \vbox (badness 10000) detected at line 41947 - -Overfull \vbox (0.56999pt too high) detected at line 41947 +Overfull \vbox (2.84741pt too high) detected at line 41957 [534] -Overfull \vbox (2.84741pt too high) detected at line 42084 +Underfull \vbox (badness 10000) detected at line 41957 + +Overfull \vbox (0.56999pt too high) detected at line 41957 [535] -Underfull \vbox (badness 10000) detected at line 42084 +Underfull \vbox (badness 10000) detected at line 41957 -Overfull \vbox (0.56999pt too high) detected at line 42084 +Overfull \vbox (0.56999pt too high) detected at line 41957 [536] -Overfull \vbox (2.84741pt too high) detected at line 42184 +Overfull \vbox (2.84741pt too high) detected at line 42094 [537] -Underfull \vbox (badness 10000) detected at line 42184 +Underfull \vbox (badness 10000) detected at line 42094 -Overfull \vbox (0.56999pt too high) detected at line 42184 +Overfull \vbox (0.56999pt too high) detected at line 42094 [538] -Overfull \vbox (2.84741pt too high) detected at line 42380 +Overfull \vbox (2.84741pt too high) detected at line 42194 [539] -Underfull \vbox (badness 10000) detected at line 42380 +Underfull \vbox (badness 10000) detected at line 42194 -Overfull \vbox (0.56999pt too high) detected at line 42380 +Overfull \vbox (0.56999pt too high) detected at line 42194 [540] -Underfull \vbox (badness 10000) detected at line 42380 - -Overfull \vbox (0.56999pt too high) detected at line 42380 +Overfull \vbox (2.84741pt too high) detected at line 42390 [541] -Overfull \vbox (2.84741pt too high) detected at line 42524 +Underfull \vbox (badness 10000) detected at line 42390 + +Overfull \vbox (0.56999pt too high) detected at line 42390 [542] -Underfull \vbox (badness 10000) detected at line 42524 +Underfull \vbox (badness 10000) detected at line 42390 -Overfull \vbox (0.56999pt too high) detected at line 42524 +Overfull \vbox (0.56999pt too high) detected at line 42390 [543] -Underfull \vbox (badness 10000) detected at line 42524 - -Overfull \vbox (0.56999pt too high) detected at line 42524 +Overfull \vbox (2.84741pt too high) detected at line 42534 [544] +Underfull \vbox (badness 10000) detected at line 42534 + +Overfull \vbox (0.56999pt too high) detected at line 42534 + [545] -Underfull \vbox (badness 10000) detected at line 42653 +Underfull \vbox (badness 10000) detected at line 42534 -Overfull \vbox (0.56999pt too high) detected at line 42653 +Overfull \vbox (0.56999pt too high) detected at line 42534 [546] -Overfull \vbox (2.84741pt too high) detected at line 42835 - [547] -Underfull \vbox (badness 10000) detected at line 42835 +Underfull \vbox (badness 10000) detected at line 42663 -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (0.56999pt too high) detected at line 42663 [548] -Underfull \vbox (badness 10000) detected at line 42835 - -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (2.84741pt too high) detected at line 42845 [549] -Underfull \vbox (badness 10000) detected at line 42835 +Underfull \vbox (badness 10000) detected at line 42845 -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (0.56999pt too high) detected at line 42845 [550] -Overfull \vbox (2.84741pt too high) detected at line 43010 +Underfull \vbox (badness 10000) detected at line 42845 + +Overfull \vbox (0.56999pt too high) detected at line 42845 [551] -Underfull \vbox (badness 10000) detected at line 43010 +Underfull \vbox (badness 10000) detected at line 42845 -Overfull \vbox (0.56999pt too high) detected at line 43010 +Overfull \vbox (0.56999pt too high) detected at line 42845 [552] -Underfull \vbox (badness 10000) detected at line 43010 - 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-[604] -Underfull \vbox (badness 10000) detected at line 46230 +Underfull \vbox (badness 10000) detected at line 46029 -Overfull \vbox (0.56999pt too high) detected at line 46230 +Overfull \vbox (0.56999pt too high) detected at line 46029 +[604] [605] +Overfull \vbox (1.94772pt too high) detected at line 46240 + [606] +Underfull \vbox (badness 10000) detected at line 46240 + +Overfull \vbox (0.56999pt too high) detected at line 46240 + [607] [608] [609] [610] -Underfull \hbox (badness 5652) in paragraph at lines 46520--46522 +[611] +[612] +Underfull \hbox (badness 5652) in paragraph at lines 46530--46532 \T1/lmr/m/n/10 (rtl) syn-the-sis. \T1/lmr/m/it/10 IEEE Std 1076.6-2004 (Re-vi-s ion of IEEE Std 1076.6-1999)\T1/lmr/m/n/10 , 2004. -Underfull \hbox (badness 7685) in paragraph at lines 46523--46525 +Underfull \hbox (badness 7685) in paragraph at lines 46533--46535 []\T1/lmr/m/n/10 IEEE Stan-dards As-so-ci-a-tion and oth-ers. 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LaTeX Warning: Reference `cmd/opt_mem_feedback:cmd-opt_mem_feedback' on page 62 -0 undefined on input line 47078. +2 undefined on input line 47088. LaTeX Warning: Reference `cmd/opt_mem_priority:cmd-opt_mem_priority' on page 62 -0 undefined on input line 47079. +2 undefined on input line 47089. -LaTeX Warning: Reference `cmd/opt_mem_widen:cmd-opt_mem_widen' on page 620 unde -fined on input line 47080. +LaTeX Warning: Reference `cmd/opt_mem_widen:cmd-opt_mem_widen' on page 622 unde +fined on input line 47090. -LaTeX Warning: Reference `cmd/opt_merge:cmd-opt_merge' on page 620 undefined on - input line 47081. +LaTeX Warning: Reference `cmd/opt_merge:cmd-opt_merge' on page 622 undefined on + input line 47091. -LaTeX Warning: Reference `cmd/opt_muxtree:cmd-opt_muxtree' on page 620 undefine -d on input line 47082. +LaTeX Warning: Reference `cmd/opt_muxtree:cmd-opt_muxtree' on page 622 undefine +d on input line 47092. -LaTeX Warning: Reference `cmd/opt_reduce:cmd-opt_reduce' on page 620 undefined -on input line 47083. +LaTeX Warning: Reference `cmd/opt_reduce:cmd-opt_reduce' on page 622 undefined +on input line 47093. -LaTeX Warning: Reference `cmd/opt_share:cmd-opt_share' on page 620 undefined on - input line 47084. +LaTeX Warning: Reference `cmd/opt_share:cmd-opt_share' on page 622 undefined on + input line 47094. -LaTeX Warning: Reference `cmd/paramap:cmd-paramap' on page 620 undefined on inp -ut line 47085. +LaTeX Warning: Reference `cmd/paramap:cmd-paramap' on page 622 undefined on inp +ut line 47095. -LaTeX Warning: Reference `cmd/peepopt:cmd-peepopt' on page 620 undefined on inp -ut line 47086. +LaTeX Warning: Reference `cmd/peepopt:cmd-peepopt' on page 622 undefined on inp +ut line 47096. -LaTeX Warning: Reference `cmd/plugin:cmd-plugin' on page 620 undefined on input - line 47087. +LaTeX Warning: Reference `cmd/plugin:cmd-plugin' on page 622 undefined on input + line 47097. -LaTeX Warning: Reference `cmd/pmux2shiftx:cmd-pmux2shiftx' on page 620 undefine -d on input line 47088. +LaTeX Warning: Reference `cmd/pmux2shiftx:cmd-pmux2shiftx' on page 622 undefine +d on input line 47098. -LaTeX Warning: Reference `cmd/pmuxtree:cmd-pmuxtree' on page 620 undefined on i -nput line 47089. +LaTeX Warning: Reference `cmd/pmuxtree:cmd-pmuxtree' on page 622 undefined on i +nput line 47099. -LaTeX Warning: Reference `cmd/portarcs:cmd-portarcs' on page 620 undefined on i -nput line 47090. +LaTeX Warning: Reference `cmd/portarcs:cmd-portarcs' on page 622 undefined on i +nput line 47100. -LaTeX Warning: Reference `cmd/portlist:cmd-portlist' on page 620 undefined on i -nput line 47091. +LaTeX Warning: Reference `cmd/portlist:cmd-portlist' on page 622 undefined on i +nput line 47101. -LaTeX Warning: Reference `cmd/prep:cmd-prep' on page 620 undefined on input lin -e 47092. +LaTeX Warning: Reference `cmd/prep:cmd-prep' on page 622 undefined on input lin +e 47102. -LaTeX Warning: Reference `cmd/printattrs:cmd-printattrs' on page 620 undefined -on input line 47093. +LaTeX Warning: Reference `cmd/printattrs:cmd-printattrs' on page 622 undefined +on input line 47103. -LaTeX Warning: Reference `cmd/proc:cmd-proc' on page 620 undefined on input lin -e 47094. +LaTeX Warning: Reference `cmd/proc:cmd-proc' on page 622 undefined on input lin +e 47104. -LaTeX Warning: Reference `cmd/proc_arst:cmd-proc_arst' on page 620 undefined on - input line 47095. +LaTeX Warning: Reference `cmd/proc_arst:cmd-proc_arst' on page 622 undefined on + input line 47105. -LaTeX Warning: Reference `cmd/proc_clean:cmd-proc_clean' on page 620 undefined -on input line 47096. +LaTeX Warning: Reference `cmd/proc_clean:cmd-proc_clean' on page 622 undefined +on input line 47106. -LaTeX Warning: Reference `cmd/proc_dff:cmd-proc_dff' on page 620 undefined on i -nput line 47097. +LaTeX Warning: Reference `cmd/proc_dff:cmd-proc_dff' on page 622 undefined on i +nput line 47107. -LaTeX Warning: Reference `cmd/proc_dlatch:cmd-proc_dlatch' on page 620 undefine -d on input line 47098. +LaTeX Warning: Reference `cmd/proc_dlatch:cmd-proc_dlatch' on page 622 undefine +d on input line 47108. -LaTeX Warning: Reference `cmd/proc_init:cmd-proc_init' on page 620 undefined on - input line 47099. +LaTeX Warning: Reference `cmd/proc_init:cmd-proc_init' on page 622 undefined on + input line 47109. -LaTeX Warning: Reference `cmd/proc_memwr:cmd-proc_memwr' on page 620 undefined -on input line 47100. +LaTeX Warning: Reference `cmd/proc_memwr:cmd-proc_memwr' on page 622 undefined +on input line 47110. -LaTeX Warning: Reference `cmd/proc_mux:cmd-proc_mux' on page 620 undefined on i -nput line 47101. +LaTeX Warning: Reference `cmd/proc_mux:cmd-proc_mux' on page 622 undefined on i +nput line 47111. -LaTeX Warning: Reference `cmd/proc_prune:cmd-proc_prune' on page 620 undefined -on input line 47102. +LaTeX Warning: Reference `cmd/proc_prune:cmd-proc_prune' on page 622 undefined +on input line 47112. -LaTeX Warning: Reference `cmd/proc_rmdead:cmd-proc_rmdead' on page 620 undefine -d on input line 47103. +LaTeX Warning: Reference `cmd/proc_rmdead:cmd-proc_rmdead' on page 622 undefine +d on input line 47113. -LaTeX Warning: Reference `cmd/proc_rom:cmd-proc_rom' on page 620 undefined on i -nput line 47104. +LaTeX Warning: Reference `cmd/proc_rom:cmd-proc_rom' on page 622 undefined on i +nput line 47114. -LaTeX Warning: Reference `cmd/qbfsat:cmd-qbfsat' on page 620 undefined on input - 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input line 47200. +LaTeX Warning: Reference `cmd/write_jny:cmd-write_jny' on page 623 undefined on + input line 47210. -LaTeX Warning: Reference `cmd/write_json:cmd-write_json' on page 621 undefined -on input line 47201. +LaTeX Warning: Reference `cmd/write_json:cmd-write_json' on page 623 undefined +on input line 47211. -LaTeX Warning: Reference `cmd/write_rtlil:cmd-write_rtlil' on page 621 undefine -d on input line 47202. +LaTeX Warning: Reference `cmd/write_rtlil:cmd-write_rtlil' on page 623 undefine +d on input line 47212. -LaTeX Warning: Reference `cmd/write_simplec:cmd-write_simplec' on page 621 unde -fined on input line 47203. +LaTeX Warning: Reference `cmd/write_simplec:cmd-write_simplec' on page 623 unde +fined on input line 47213. -LaTeX Warning: Reference `cmd/write_smt2:cmd-write_smt2' on page 621 undefined -on input line 47204. +LaTeX Warning: Reference `cmd/write_smt2:cmd-write_smt2' on page 623 undefined +on input line 47214. -LaTeX Warning: Reference `cmd/write_smv:cmd-write_smv' on page 621 undefined on - input line 47205. +LaTeX Warning: Reference `cmd/write_smv:cmd-write_smv' on page 623 undefined on + input line 47215. -LaTeX Warning: Reference `cmd/write_spice:cmd-write_spice' on page 621 undefine -d on input line 47206. +LaTeX Warning: Reference `cmd/write_spice:cmd-write_spice' on page 623 undefine +d on input line 47216. -LaTeX Warning: Reference `cmd/write_table:cmd-write_table' on page 621 undefine -d on input line 47207. +LaTeX Warning: Reference `cmd/write_table:cmd-write_table' on page 623 undefine +d on input line 47217. -LaTeX Warning: Reference `cmd/write_verilog:cmd-write_verilog' on page 621 unde -fined on input line 47208. +LaTeX Warning: Reference `cmd/write_verilog:cmd-write_verilog' on page 623 unde +fined on input line 47218. -LaTeX Warning: Reference `cmd/write_xaiger:cmd-write_xaiger' on page 621 undefi -ned on input line 47209. +LaTeX Warning: Reference `cmd/write_xaiger:cmd-write_xaiger' on page 623 undefi +ned on input line 47219. -LaTeX Warning: Reference `cmd/write_xaiger2:cmd-write_xaiger2' on page 621 unde -fined on input line 47210. +LaTeX Warning: Reference `cmd/write_xaiger2:cmd-write_xaiger2' on page 623 unde +fined on input line 47220. -LaTeX Warning: Reference `cmd/xilinx_dffopt:cmd-xilinx_dffopt' on page 621 unde -fined on input line 47211. +LaTeX Warning: Reference `cmd/xilinx_dffopt:cmd-xilinx_dffopt' on page 623 unde +fined on input line 47221. -LaTeX Warning: Reference `cmd/xilinx_dsp:cmd-xilinx_dsp' on page 621 undefined -on input line 47212. +LaTeX Warning: Reference `cmd/xilinx_dsp:cmd-xilinx_dsp' on page 623 undefined +on input line 47222. -LaTeX Warning: Reference `cmd/xilinx_srl:cmd-xilinx_srl' on page 621 undefined -on input line 47213. +LaTeX Warning: Reference `cmd/xilinx_srl:cmd-xilinx_srl' on page 623 undefined +on input line 47223. -LaTeX Warning: Reference `cmd/xprop:cmd-xprop' on page 621 undefined on input l -ine 47214. +LaTeX Warning: Reference `cmd/xprop:cmd-xprop' on page 623 undefined on input l +ine 47224. -LaTeX Warning: Reference `cmd/zinit:cmd-zinit' on page 621 undefined on input l -ine 47215. +LaTeX Warning: Reference `cmd/zinit:cmd-zinit' on page 623 undefined on input l +ine 47225. -[621] -[622] +[623] +[624] -LaTeX Warning: Reference `cmd/abc:cmd-abc' on page 623 undefined on input line -47221. +LaTeX Warning: Reference `cmd/abc:cmd-abc' on page 625 undefined on input line +47231. -LaTeX Warning: Reference `cmd/abc9:cmd-abc9' on page 623 undefined on input lin -e 47222. +LaTeX Warning: Reference `cmd/abc9:cmd-abc9' on page 625 undefined on input lin +e 47232. -LaTeX Warning: Reference `cmd/abc9_exe:cmd-abc9_exe' on page 623 undefined on i -nput line 47223. +LaTeX Warning: Reference `cmd/abc9_exe:cmd-abc9_exe' on page 625 undefined on i +nput line 47233. -LaTeX Warning: Reference `cmd/abc9_ops:cmd-abc9_ops' on page 623 undefined on i -nput line 47224. +LaTeX Warning: Reference `cmd/abc9_ops:cmd-abc9_ops' on page 625 undefined on i +nput line 47234. -LaTeX Warning: Reference `cmd/abc_new:cmd-abc_new' on page 623 undefined on inp -ut line 47225. +LaTeX Warning: Reference `cmd/abc_new:cmd-abc_new' on page 625 undefined on inp +ut line 47235. -LaTeX Warning: Reference `cmd/abstract:cmd-abstract' on page 623 undefined on i -nput line 47226. +LaTeX Warning: Reference `cmd/abstract:cmd-abstract' on page 625 undefined on i +nput line 47236. -LaTeX Warning: Reference `cmd/add:cmd-add' on page 623 undefined on input line -47227. +LaTeX Warning: Reference `cmd/add:cmd-add' on page 625 undefined on input line +47237. -LaTeX Warning: Reference `cmd/aigmap:cmd-aigmap' on page 623 undefined on input - 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LaTeX Warning: Reference `cmd/gatemate_foldinv:cmd-gatemate_foldinv' on page 62 -4 undefined on input line 47314. +6 undefined on input line 47324. -LaTeX Warning: Reference `cmd/glift:cmd-glift' on page 624 undefined on input l -ine 47315. +LaTeX Warning: Reference `cmd/glift:cmd-glift' on page 626 undefined on input l +ine 47325. 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line 47437. +LaTeX Warning: Reference `cmd/submod:cmd-submod' on page 627 undefined on input + line 47447. -LaTeX Warning: Reference `cmd/supercover:cmd-supercover' on page 625 undefined -on input line 47438. +LaTeX Warning: Reference `cmd/supercover:cmd-supercover' on page 627 undefined +on input line 47448. -LaTeX Warning: Reference `cmd/synth:cmd-synth' on page 625 undefined on input l -ine 47439. +LaTeX Warning: Reference `cmd/synth:cmd-synth' on page 627 undefined on input l +ine 47449. -LaTeX Warning: Reference `cmd/synth_achronix:cmd-synth_achronix' on page 625 un -defined on input line 47440. +LaTeX Warning: Reference `cmd/synth_achronix:cmd-synth_achronix' on page 627 un +defined on input line 47450. -LaTeX Warning: Reference `cmd/synth_anlogic:cmd-synth_anlogic' on page 625 unde -fined on input line 47441. +LaTeX Warning: Reference `cmd/synth_anlogic:cmd-synth_anlogic' on page 627 unde +fined on input line 47451. LaTeX Warning: Reference `cmd/synth_coolrunner2:cmd-synth_coolrunner2' on page -625 undefined on input line 47442. +627 undefined on input line 47452. -LaTeX Warning: Reference `cmd/synth_easic:cmd-synth_easic' on page 625 undefine -d on input line 47443. +LaTeX Warning: Reference `cmd/synth_easic:cmd-synth_easic' on page 627 undefine +d on input line 47453. -LaTeX Warning: Reference `cmd/synth_ecp5:cmd-synth_ecp5' on page 625 undefined -on input line 47444. +LaTeX Warning: Reference `cmd/synth_ecp5:cmd-synth_ecp5' on page 627 undefined +on input line 47454. -LaTeX Warning: Reference `cmd/synth_efinix:cmd-synth_efinix' on page 625 undefi -ned on input line 47445. +LaTeX Warning: Reference `cmd/synth_efinix:cmd-synth_efinix' on page 627 undefi +ned on input line 47455. -LaTeX Warning: Reference `cmd/synth_fabulous:cmd-synth_fabulous' on page 625 un -defined on input line 47446. +LaTeX Warning: Reference `cmd/synth_fabulous:cmd-synth_fabulous' on page 627 un +defined on input line 47456. -LaTeX Warning: Reference `cmd/synth_gatemate:cmd-synth_gatemate' on page 625 un -defined on input line 47447. +LaTeX Warning: Reference `cmd/synth_gatemate:cmd-synth_gatemate' on page 627 un +defined on input line 47457. -LaTeX Warning: Reference `cmd/synth_gowin:cmd-synth_gowin' on page 625 undefine -d on input line 47448. +LaTeX Warning: Reference `cmd/synth_gowin:cmd-synth_gowin' on page 627 undefine +d on input line 47458. -LaTeX Warning: Reference `cmd/synth_greenpak4:cmd-synth_greenpak4' on page 625 -undefined on input line 47449. +LaTeX Warning: Reference `cmd/synth_greenpak4:cmd-synth_greenpak4' on page 627 +undefined on input line 47459. -LaTeX Warning: Reference `cmd/synth_ice40:cmd-synth_ice40' on page 625 undefine -d on input line 47450. +LaTeX Warning: Reference `cmd/synth_ice40:cmd-synth_ice40' on page 627 undefine +d on input line 47460. -LaTeX Warning: Reference `cmd/synth_intel:cmd-synth_intel' on page 625 undefine -d on input line 47451. +LaTeX Warning: Reference `cmd/synth_intel:cmd-synth_intel' on page 627 undefine +d on input line 47461. -LaTeX Warning: Reference `cmd/synth_intel_alm:cmd-synth_intel_alm' on page 625 -undefined on input line 47452. +LaTeX Warning: Reference `cmd/synth_intel_alm:cmd-synth_intel_alm' on page 627 +undefined on input line 47462. -LaTeX Warning: Reference `cmd/synth_lattice:cmd-synth_lattice' on page 625 unde -fined on input line 47453. +LaTeX Warning: Reference `cmd/synth_lattice:cmd-synth_lattice' on page 627 unde +fined on input line 47463. -LaTeX Warning: Reference `cmd/synth_microchip:cmd-synth_microchip' on page 625 -undefined on input line 47454. +LaTeX Warning: Reference `cmd/synth_microchip:cmd-synth_microchip' on page 627 +undefined on input line 47464. LaTeX Warning: Reference `cmd/synth_nanoxplore:cmd-synth_nanoxplore' on page 62 -5 undefined on input line 47455. +7 undefined on input line 47465. -LaTeX Warning: Reference `cmd/synth_nexus:cmd-synth_nexus' on page 625 undefine -d on input line 47456. +LaTeX Warning: Reference `cmd/synth_nexus:cmd-synth_nexus' on page 627 undefine +d on input line 47466. LaTeX Warning: Reference `cmd/synth_quicklogic:cmd-synth_quicklogic' on page 62 -5 undefined on input line 47457. +7 undefined on input line 47467. -LaTeX Warning: Reference `cmd/synth_sf2:cmd-synth_sf2' on page 625 undefined on - input line 47458. +LaTeX Warning: Reference `cmd/synth_sf2:cmd-synth_sf2' on page 627 undefined on + input line 47468. -LaTeX Warning: Reference `cmd/synth_xilinx:cmd-synth_xilinx' on page 625 undefi -ned on input line 47459. +LaTeX Warning: Reference `cmd/synth_xilinx:cmd-synth_xilinx' on page 627 undefi +ned on input line 47469. -LaTeX Warning: Reference `cmd/synthprop:cmd-synthprop' on page 625 undefined on - input line 47460. +LaTeX Warning: Reference `cmd/synthprop:cmd-synthprop' on page 627 undefined on + input line 47470. -LaTeX Warning: Reference `cmd/tcl:cmd-tcl' on page 625 undefined on input line -47461. +LaTeX Warning: Reference `cmd/tcl:cmd-tcl' on page 627 undefined on input line +47471. -LaTeX Warning: Reference `cmd/techmap:cmd-techmap' on page 625 undefined on inp -ut line 47462. +LaTeX Warning: Reference `cmd/techmap:cmd-techmap' on page 627 undefined on inp +ut line 47472. -LaTeX Warning: Reference `cmd/tee:cmd-tee' on page 625 undefined on input line -47463. +LaTeX Warning: Reference `cmd/tee:cmd-tee' on page 627 undefined on input line +47473. -LaTeX Warning: Reference `cmd/test_abcloop:cmd-test_abcloop' on page 625 undefi -ned on input line 47464. +LaTeX Warning: Reference `cmd/test_abcloop:cmd-test_abcloop' on page 627 undefi +ned on input line 47474. -LaTeX Warning: Reference `cmd/test_autotb:cmd-test_autotb' on page 625 undefine -d on input line 47465. +LaTeX Warning: Reference `cmd/test_autotb:cmd-test_autotb' on page 627 undefine +d on input line 47475. -LaTeX Warning: Reference `cmd/test_cell:cmd-test_cell' on page 625 undefined on - input line 47466. +LaTeX Warning: Reference `cmd/test_cell:cmd-test_cell' on page 627 undefined on + input line 47476. -LaTeX Warning: Reference `cmd/test_generic:cmd-test_generic' on page 625 undefi -ned on input line 47467. +LaTeX Warning: Reference `cmd/test_generic:cmd-test_generic' on page 627 undefi +ned on input line 47477. -LaTeX Warning: Reference `cmd/test_pmgen:cmd-test_pmgen' on page 625 undefined -on input line 47468. +LaTeX Warning: Reference `cmd/test_pmgen:cmd-test_pmgen' on page 627 undefined +on input line 47478. -LaTeX Warning: Reference `cmd/torder:cmd-torder' on page 625 undefined on input - line 47469. +LaTeX Warning: Reference `cmd/torder:cmd-torder' on page 627 undefined on input + line 47479. -LaTeX Warning: Reference `cmd/trace:cmd-trace' on page 625 undefined on input l -ine 47470. +LaTeX Warning: Reference `cmd/trace:cmd-trace' on page 627 undefined on input l +ine 47480. -LaTeX Warning: Reference `cmd/tribuf:cmd-tribuf' on page 625 undefined on input - line 47471. +LaTeX Warning: Reference `cmd/tribuf:cmd-tribuf' on page 627 undefined on input + line 47481. -LaTeX Warning: Reference `cmd/uniquify:cmd-uniquify' on page 625 undefined on i -nput line 47472. +LaTeX Warning: Reference `cmd/uniquify:cmd-uniquify' on page 627 undefined on i +nput line 47482. -LaTeX Warning: Reference `cmd/verific:cmd-verific' on page 625 undefined on inp -ut line 47473. +LaTeX Warning: Reference `cmd/verific:cmd-verific' on page 627 undefined on inp +ut line 47483. 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LaTeX Warning: Reference `cmd/write_functional_cxx:cmd-write_functional_cxx' on - page 625 undefined on input line 47488. + page 627 undefined on input line 47498. LaTeX Warning: Reference `cmd/write_functional_rosette:cmd-write_functional_ros -ette' on page 625 undefined on input line 47489. +ette' on page 627 undefined on input line 47499. LaTeX Warning: Reference `cmd/write_functional_smt2:cmd-write_functional_smt2' -on page 625 undefined on input line 47490. +on page 627 undefined on input line 47500. LaTeX Warning: Reference `cmd/write_intersynth:cmd-write_intersynth' on page 62 -5 undefined on input line 47491. +7 undefined on input line 47501. -LaTeX Warning: Reference `cmd/write_jny:cmd-write_jny' on page 625 undefined on - input line 47492. +LaTeX Warning: Reference `cmd/write_jny:cmd-write_jny' on page 627 undefined on + input line 47502. -LaTeX Warning: Reference `cmd/write_json:cmd-write_json' on page 625 undefined -on input line 47493. +LaTeX Warning: Reference `cmd/write_json:cmd-write_json' on page 627 undefined +on input line 47503. -LaTeX Warning: Reference `cmd/write_rtlil:cmd-write_rtlil' on page 625 undefine -d on input line 47494. +LaTeX Warning: Reference `cmd/write_rtlil:cmd-write_rtlil' on page 627 undefine +d on input line 47504. -LaTeX Warning: Reference `cmd/write_simplec:cmd-write_simplec' on page 625 unde -fined on input line 47495. +LaTeX Warning: Reference `cmd/write_simplec:cmd-write_simplec' on page 627 unde +fined on input line 47505. -LaTeX Warning: Reference `cmd/write_smt2:cmd-write_smt2' on page 625 undefined -on input line 47496. +LaTeX Warning: Reference `cmd/write_smt2:cmd-write_smt2' on page 627 undefined +on input line 47506. -LaTeX Warning: Reference `cmd/write_smv:cmd-write_smv' on page 625 undefined on - input line 47497. +LaTeX Warning: Reference `cmd/write_smv:cmd-write_smv' on page 627 undefined on + input line 47507. -LaTeX Warning: Reference `cmd/write_spice:cmd-write_spice' on page 625 undefine -d on input line 47498. +LaTeX Warning: Reference `cmd/write_spice:cmd-write_spice' on page 627 undefine +d on input line 47508. -LaTeX Warning: Reference `cmd/write_table:cmd-write_table' on page 625 undefine -d on input line 47499. +LaTeX Warning: Reference `cmd/write_table:cmd-write_table' on page 627 undefine +d on input line 47509. -LaTeX Warning: Reference `cmd/write_verilog:cmd-write_verilog' on page 625 unde -fined on input line 47500. +LaTeX Warning: Reference `cmd/write_verilog:cmd-write_verilog' on page 627 unde +fined on input line 47510. -LaTeX Warning: Reference `cmd/write_xaiger:cmd-write_xaiger' on page 625 undefi -ned on input line 47501. +LaTeX Warning: Reference `cmd/write_xaiger:cmd-write_xaiger' on page 627 undefi +ned on input line 47511. -LaTeX Warning: Reference `cmd/write_xaiger2:cmd-write_xaiger2' on page 625 unde -fined on input line 47502. +LaTeX Warning: Reference `cmd/write_xaiger2:cmd-write_xaiger2' on page 627 unde +fined on input line 47512. -LaTeX Warning: Reference `cmd/xilinx_dffopt:cmd-xilinx_dffopt' on page 625 unde -fined on input line 47503. +LaTeX Warning: Reference `cmd/xilinx_dffopt:cmd-xilinx_dffopt' on page 627 unde +fined on input line 47513. -LaTeX Warning: Reference `cmd/xilinx_dsp:cmd-xilinx_dsp' on page 625 undefined -on input line 47504. +LaTeX Warning: Reference `cmd/xilinx_dsp:cmd-xilinx_dsp' on page 627 undefined +on input line 47514. -LaTeX Warning: Reference `cmd/xilinx_srl:cmd-xilinx_srl' on page 625 undefined -on input line 47505. +LaTeX Warning: Reference `cmd/xilinx_srl:cmd-xilinx_srl' on page 627 undefined +on input line 47515. -LaTeX Warning: Reference `cmd/xprop:cmd-xprop' on page 625 undefined on input l -ine 47506. +LaTeX Warning: Reference `cmd/xprop:cmd-xprop' on page 627 undefined on input l +ine 47516. -LaTeX Warning: Reference `cmd/zinit:cmd-zinit' on page 625 undefined on input l -ine 47507. +LaTeX Warning: Reference `cmd/zinit:cmd-zinit' on page 627 undefined on input l +ine 47517. -[625] +[627] No file yosyshqyosys.ind. Package longtable Warning: Table widths have changed. Rerun LaTeX. @@ -53602,7 +53043,7 @@ .pfb> -Output written on yosyshqyosys.pdf (629 pages, 2890867 bytes). +Output written on yosyshqyosys.pdf (631 pages, 2891892 bytes). Transcript written on yosyshqyosys.log. Latexmk: Getting log file 'yosyshqyosys.log' Latexmk: Examining 'yosyshqyosys.fls' @@ -54963,10 +54404,10 @@ [173] [174] [175] -Underfull \vbox (badness 5331) detected at line 11767 +Underfull \vbox (badness 5331) detected at line 11772 [176] -Underfull \hbox (badness 10000) in paragraph at lines 11769--11778 +Underfull \hbox (badness 10000) in paragraph at lines 11774--11783 []\T1/lmr/m/n/10 Be-cause we are us-ing the \T1/lmtt/m/n/10 Backend \T1/lmr/m/n /10 class, our \T1/lmtt/m/n/10 "functional_dummy" \T1/lmr/m/n/10 is reg-is-tere d as the @@ -54974,23 +54415,23 @@ [177] [178] [179] -Underfull \vbox (badness 1072) detected at line 12056 +Underfull \vbox (badness 1072) detected at line 12061 [180] [181] [182] [183] -Underfull \hbox (badness 10000) in paragraph at lines 12227--12227 +Underfull \hbox (badness 10000) in paragraph at lines 12232--12232 []\T1/lmr/m/n/10 Listing 4.22: |[]iterating over Func-tion-alIR nodes in [184] -Underfull \hbox (badness 10000) in paragraph at lines 12252--12252 +Underfull \hbox (badness 10000) in paragraph at lines 12257--12257 []\T1/lmr/m/n/10 Listing 4.24: |[]diff of out-put/next state han-dling [185] [186] [187] -Underfull \vbox (badness 4001) detected at line 12529 +Underfull \vbox (badness 4001) detected at line 12534 [188] [189 <./red_or3x1.pdf>] @@ -54998,15 +54439,15 @@ [191 <./mymul.pdf>] [192] [193 <./mulshift.pdf>] -Underfull \hbox (badness 5490) in paragraph at lines 12842--12845 +Underfull \hbox (badness 5490) in paragraph at lines 12847--12850 []\T1/lmr/m/n/10 Each bit of the port cor-re-lates to an \T1/lmtt/m/n/10 _TECHM AP_BITS_CONNMAP_ \T1/lmr/m/n/10 bits wide num-ber in -Underfull \hbox (badness 10000) in paragraph at lines 12847--12850 +Underfull \hbox (badness 10000) in paragraph at lines 12852--12855 []\T1/lmr/m/n/10 Each unique sig-nal bit is as-signed its own num-ber. Iden-ti- cal fields in the -Overfull \vbox (0.52754pt too high) detected at line 12902 +Overfull \vbox (0.52754pt too high) detected at line 12907 [194] [195 <./addshift.pdf>] @@ -55047,30 +54488,28 @@ [224] Chapter 8. -Overfull \vbox (1.34746pt too high) detected at line 15232 +Overfull \vbox (1.34746pt too high) detected at line 15242 [225] [226] -Underfull \vbox (badness 10000) detected at line 15467 - -Overfull \vbox (0.56999pt too high) detected at line 15467 +Underfull \vbox (badness 4954) detected at line 15477 [227] -Underfull \vbox (badness 10000) detected at line 15467 +Underfull \vbox (badness 10000) detected at line 15477 -Overfull \vbox (0.56999pt too high) detected at line 15467 +Overfull \vbox (0.56999pt too high) detected at line 15477 [228] -Underfull \vbox (badness 10000) detected at line 15467 +Underfull \vbox (badness 10000) detected at line 15477 -Overfull \vbox (0.56999pt too high) detected at line 15467 +Overfull \vbox (0.56999pt too high) detected at line 15477 [229] [230] -Chapter 9. - [231] [232] +Chapter 9. + [233] [234] [235] @@ -55093,10 +54532,10 @@ [252] [253] [254] -Overfull \vbox (2.36986pt too high) detected at line 18216 - [255] [256] +Overfull \vbox (2.36986pt too high) detected at line 18226 + [257] [258] [259] @@ -55115,69 +54554,69 @@ [272] [273] [274] -Underfull \vbox (badness 10000) detected at line 20043 - -Overfull \vbox (2.76991pt too high) detected at line 20043 - [275] [276] -Underfull \vbox (badness 10000) detected at line 20182 +Underfull \vbox (badness 10000) detected at line 20053 -Overfull \vbox (2.76991pt too high) detected at line 20182 +Overfull \vbox (2.76991pt too high) detected at line 20053 [277] -Underfull \vbox (badness 10000) detected at line 20182 +[278] +Underfull \vbox (badness 10000) detected at line 20192 -Overfull \vbox (0.56999pt too high) detected at line 20182 +Overfull \vbox (2.76991pt too high) detected at line 20192 -[278] [279] +Underfull \vbox (badness 10000) detected at line 20192 + +Overfull \vbox (0.56999pt too high) detected at line 20192 + [280] [281] [282] [283] -Underfull \vbox (badness 10000) detected at line 20597 - -Overfull \vbox (0.56999pt too high) detected at line 20597 - [284] [285] +Underfull \vbox (badness 10000) detected at line 20607 + +Overfull \vbox (0.56999pt too high) detected at line 20607 + [286] [287] [288] -Underfull \vbox (badness 10000) detected at line 21032 - -Overfull \vbox (0.56999pt too high) detected at line 21032 - [289] -Underfull \vbox (badness 10000) detected at line 21032 +[290] +Underfull \vbox (badness 10000) detected at line 21042 -Overfull \vbox (0.56999pt too high) detected at line 21032 +Overfull \vbox (0.56999pt too high) detected at line 21042 -[290] [291] -Underfull \vbox (badness 10000) detected at line 21170 +Underfull \vbox (badness 10000) detected at line 21042 -Overfull \vbox (0.56999pt too high) detected at line 21170 +Overfull \vbox (0.56999pt too high) detected at line 21042 [292] [293] -[294] -Overfull \vbox (0.94846pt too high) detected at line 21411 +Underfull \vbox (badness 10000) detected at line 21180 +Overfull \vbox (0.56999pt too high) detected at line 21180 + +[294] [295] [296] -Underfull \vbox (badness 10000) detected at line 21546 - -Overfull \vbox (0.56999pt too high) detected at line 21546 +Overfull \vbox (0.94846pt too high) detected at line 21421 [297] -Underfull \vbox (badness 10000) detected at line 21546 +[298] +Underfull \vbox (badness 10000) detected at line 21556 -Overfull \vbox (0.56999pt too high) detected at line 21546 +Overfull \vbox (0.56999pt too high) detected at line 21556 -[298] [299] +Underfull \vbox (badness 10000) detected at line 21556 + +Overfull \vbox (0.56999pt too high) detected at line 21556 + [300] [301] [302] @@ -55267,87 +54706,87 @@ [386] [387] [388] -Chapter 10. - [389] [390] -[391] -Underfull \vbox (badness 10000) detected at line 32041 - -Overfull \vbox (0.56999pt too high) detected at line 32041 +Chapter 10. +[391] [392] -Underfull \vbox (badness 10000) detected at line 32041 - -Overfull \vbox (0.56999pt too high) detected at line 32041 - [393] -Overfull \vbox (2.84741pt too high) detected at line 32199 +Underfull \vbox (badness 10000) detected at line 32051 + +Overfull \vbox (0.56999pt too high) detected at line 32051 [394] -Underfull \vbox (badness 10000) detected at line 32199 +Underfull \vbox (badness 10000) detected at line 32051 -Overfull \vbox (0.56999pt too high) detected at line 32199 +Overfull \vbox (0.56999pt too high) detected at line 32051 [395] -Underfull \vbox (badness 10000) detected at line 32199 - -Overfull \vbox (0.56999pt too high) detected at line 32199 +Overfull \vbox (2.84741pt too high) detected at line 32209 [396] +Underfull \vbox (badness 10000) detected at line 32209 + +Overfull \vbox (0.56999pt too high) detected at line 32209 + [397] -Underfull \vbox (badness 10000) detected at line 32305 +Underfull \vbox (badness 10000) detected at line 32209 -Underfull \vbox (badness 10000) detected at line 32305 +Overfull \vbox (0.56999pt too high) detected at line 32209 [398] -Overfull \vbox (2.84741pt too high) detected at line 32403 - [399] -Underfull \vbox (badness 10000) detected at line 32403 +Underfull \vbox (badness 10000) detected at line 32315 -Overfull \vbox (0.56999pt too high) detected at line 32403 +Underfull \vbox (badness 10000) detected at line 32315 [400] +Overfull \vbox (2.84741pt too high) detected at line 32413 + [401] -[402] -Overfull \vbox (2.84741pt too high) detected at line 32587 +Underfull \vbox (badness 10000) detected at line 32413 +Overfull \vbox (0.56999pt too high) detected at line 32413 + +[402] [403] [404] -[405] -Overfull \vbox (2.84741pt too high) detected at line 32828 +Overfull \vbox (2.84741pt too high) detected at line 32597 +[405] [406] [407] +Overfull \vbox (2.84741pt too high) detected at line 32838 + [408] [409] [410] [411] -Overfull \vbox (1.94772pt too high) detected at line 33272 - [412] -Overfull \vbox (2.84741pt too high) detected at line 33334 - [413] +Overfull \vbox (1.94772pt too high) detected at line 33282 + [414] +Overfull \vbox (2.84741pt too high) detected at line 33344 + [415] [416] -Overfull \vbox (1.94772pt too high) detected at line 33667 - [417] [418] +Overfull \vbox (1.94772pt too high) detected at line 33677 + [419] [420] [421] [422] -Overfull \vbox (1.94772pt too high) detected at line 34144 - [423] -Overfull \vbox (2.84741pt too high) detected at line 34187 - [424] +Overfull \vbox (1.94772pt too high) detected at line 34154 + [425] +Overfull \vbox (2.84741pt too high) detected at line 34197 + [426] [427] [428] @@ -55355,51 +54794,51 @@ [430] [431] [432] -Overfull \vbox (1.94772pt too high) detected at line 34893 - [433] -Overfull \vbox (2.84741pt too high) detected at line 34993 - [434] +Overfull \vbox (1.94772pt too high) detected at line 34903 + [435] +Overfull \vbox (2.84741pt too high) detected at line 35003 + [436] [437] -Overfull \vbox (2.84741pt too high) detected at line 35231 - [438] [439] -Overfull \vbox (1.94772pt too high) detected at line 35378 +Overfull \vbox (2.84741pt too high) detected at line 35241 [440] [441] -Overfull \vbox (1.94772pt too high) detected at line 35511 +Overfull \vbox (1.94772pt too high) detected at line 35388 [442] [443] +Overfull \vbox (1.94772pt too high) detected at line 35521 + [444] [445] [446] -Underfull \vbox (badness 10000) detected at line 35893 - -Overfull \vbox (0.56999pt too high) detected at line 35893 - [447] [448] -Underfull \vbox (badness 10000) detected at line 36040 +Underfull \vbox (badness 10000) detected at line 35903 -Overfull \vbox (0.56999pt too high) detected at line 36040 +Overfull \vbox (0.56999pt too high) detected at line 35903 [449] [450] +Underfull \vbox (badness 10000) detected at line 36050 + +Overfull \vbox (0.56999pt too high) detected at line 36050 + [451] [452] [453] [454] [455] -Overfull \vbox (1.94772pt too high) detected at line 36628 - [456] [457] +Overfull \vbox (1.94772pt too high) detected at line 36638 + [458] [459] [460] @@ -55407,15 +54846,15 @@ [462] [463] [464] -Overfull \vbox (2.84741pt too high) detected at line 37362 - [465] -Underfull \vbox (badness 10000) detected at line 37362 - -Overfull \vbox (0.56999pt too high) detected at line 37362 - [466] +Overfull \vbox (2.84741pt too high) detected at line 37372 + [467] +Underfull \vbox (badness 10000) detected at line 37372 + +Overfull \vbox (0.56999pt too high) detected at line 37372 + [468] [469] [470] @@ -55427,439 +54866,437 @@ [476] [477] [478] -Overfull \vbox (1.94772pt too high) detected at line 38409 - [479] [480] +Overfull \vbox (1.94772pt too high) detected at line 38419 + [481] [482] [483] [484] -Overfull \vbox (2.84741pt too high) detected at line 38933 - [485] [486] +Overfull \vbox (2.84741pt too high) detected at line 38943 + [487] [488] -Underfull \vbox (badness 10000) detected at line 39254 - -Overfull \vbox (0.56999pt too high) detected at line 39254 - [489] -Underfull \vbox (badness 10000) detected at line 39254 +[490] +Underfull \vbox (badness 10000) detected at line 39264 -Overfull \vbox (0.56999pt too high) detected at line 39254 +Overfull \vbox (0.56999pt too high) detected at line 39264 -[490] [491] -[492] -[493] -Underfull \vbox (badness 10000) detected at line 39617 +Underfull \vbox (badness 10000) detected at line 39264 -Overfull \vbox (0.56999pt too high) detected at line 39617 +Overfull \vbox (0.56999pt too high) detected at line 39264 +[492] +[493] [494] -Underfull \vbox (badness 10000) detected at line 39617 +[495] +Underfull \vbox (badness 10000) detected at line 39627 -Overfull \vbox (0.56999pt too high) detected at line 39617 +Overfull \vbox (0.56999pt too high) detected at line 39627 -[495] [496] -[497] -Overfull \vbox (1.94772pt too high) detected at line 39779 +Underfull \vbox (badness 10000) detected at line 39627 -[498] -Overfull \vbox (2.84741pt too high) detected at line 40027 +Overfull \vbox (0.56999pt too high) detected at line 39627 +[497] +[498] [499] -Underfull \vbox (badness 10000) detected at line 40027 - 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[508] -Overfull \vbox (2.84741pt too high) detected at line 40548 +Underfull \vbox (badness 10000) detected at line 40359 -[509] -Underfull \vbox (badness 10000) detected at line 40548 +Overfull \vbox (0.56999pt too high) detected at line 40359 -Overfull \vbox (0.56999pt too high) detected at line 40548 +[509] +Overfull \vbox (2.84741pt too high) detected at line 40429 [510] +Overfull \vbox (2.84741pt too high) detected at line 40558 + [511] -Overfull \vbox (1.94772pt too high) detected at line 40660 +Underfull \vbox (badness 10000) detected at line 40558 + +Overfull \vbox (0.56999pt too high) detected at line 40558 [512] [513] -[514] -Overfull \vbox (1.94772pt too high) detected at line 40946 +Overfull \vbox (1.94772pt too high) detected at line 40670 +[514] [515] -Underfull \vbox (badness 10000) detected at line 40946 - -Overfull \vbox (0.56999pt too high) detected at line 40946 - [516] -Overfull \vbox (2.84741pt too high) detected at line 41031 +Overfull \vbox (1.94772pt too high) detected at line 40956 [517] -Overfull \vbox (2.84741pt too high) detected at line 41140 +Underfull \vbox (badness 10000) detected at line 40956 -[518] -Underfull \vbox (badness 10000) detected at line 41140 +Overfull \vbox (0.56999pt too high) detected at line 40956 -Overfull \vbox (0.56999pt too high) detected at line 41140 +[518] +Overfull \vbox (2.84741pt too high) detected at line 41041 [519] -Overfull \vbox (2.84741pt too high) detected at line 41240 +Overfull \vbox (2.84741pt too high) detected at line 41150 [520] -Underfull \vbox (badness 10000) detected at line 41240 +Underfull \vbox (badness 10000) detected at line 41150 -Overfull \vbox (0.56999pt too high) detected at line 41240 +Overfull \vbox (0.56999pt too high) detected at line 41150 [521] -Overfull \vbox (2.84741pt too high) detected at line 41320 +Overfull \vbox (2.84741pt too high) detected at line 41250 [522] -Overfull \vbox (2.84741pt too high) detected at line 41498 +Underfull \vbox (badness 10000) detected at line 41250 -[523] -Underfull \vbox (badness 10000) detected at line 41498 +Overfull \vbox (0.56999pt too high) detected at line 41250 -Overfull \vbox (0.56999pt too high) detected at line 41498 +[523] +Overfull \vbox (2.84741pt too high) detected at line 41330 [524] -Underfull \vbox (badness 10000) detected at line 41498 - -Overfull \vbox (0.56999pt too high) detected at line 41498 +Overfull \vbox (2.84741pt too high) detected at line 41508 [525] -[526] -[527] -Overfull \vbox (2.84741pt too high) detected at line 41784 +Underfull \vbox (badness 10000) detected at line 41508 -[528] -Underfull \vbox (badness 10000) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41508 -Overfull \vbox (0.56999pt too high) detected at line 41784 +[526] +Underfull \vbox (badness 10000) detected at line 41508 -[529] -Underfull \vbox (badness 10000) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41508 -Overfull \vbox (0.56999pt too high) detected at line 41784 +[527] +[528] +[529] +Overfull \vbox (2.84741pt too high) detected at line 41794 [530] -Underfull \vbox (badness 10000) detected at line 41784 +Underfull \vbox (badness 10000) detected at line 41794 -Overfull \vbox (0.56999pt too high) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41794 [531] -Overfull \vbox (2.84741pt too high) detected at line 41947 +Underfull \vbox (badness 10000) detected at line 41794 + +Overfull \vbox (0.56999pt too high) detected at line 41794 [532] -Underfull \vbox (badness 10000) detected at line 41947 +Underfull \vbox (badness 10000) detected at line 41794 -Overfull \vbox (0.56999pt too high) detected at line 41947 +Overfull \vbox (0.56999pt too high) detected at line 41794 [533] -Underfull \vbox (badness 10000) detected at line 41947 - -Overfull \vbox (0.56999pt too high) detected at line 41947 +Overfull \vbox (2.84741pt too high) detected at line 41957 [534] -Overfull \vbox (2.84741pt too high) detected at line 42084 +Underfull \vbox (badness 10000) detected at line 41957 + +Overfull \vbox (0.56999pt too high) detected at line 41957 [535] -Underfull \vbox (badness 10000) detected at line 42084 +Underfull \vbox (badness 10000) detected at line 41957 -Overfull \vbox (0.56999pt too high) detected at line 42084 +Overfull \vbox (0.56999pt too high) detected at line 41957 [536] -Overfull \vbox (2.84741pt too high) detected at line 42184 +Overfull \vbox (2.84741pt too high) detected at line 42094 [537] -Underfull \vbox (badness 10000) detected at line 42184 +Underfull \vbox (badness 10000) detected at line 42094 -Overfull \vbox (0.56999pt too high) detected at line 42184 +Overfull \vbox (0.56999pt too high) detected at line 42094 [538] -Overfull \vbox (2.84741pt too high) detected at line 42380 +Overfull \vbox (2.84741pt too high) detected at line 42194 [539] -Underfull \vbox (badness 10000) detected at line 42380 +Underfull \vbox (badness 10000) detected at line 42194 -Overfull \vbox (0.56999pt too high) detected at line 42380 +Overfull \vbox (0.56999pt too high) detected at line 42194 [540] -Underfull \vbox (badness 10000) detected at line 42380 - -Overfull \vbox (0.56999pt too high) detected at line 42380 +Overfull \vbox (2.84741pt too high) detected at line 42390 [541] -Overfull \vbox (2.84741pt too high) detected at line 42524 +Underfull \vbox (badness 10000) detected at line 42390 + +Overfull \vbox (0.56999pt too high) detected at line 42390 [542] -Underfull \vbox (badness 10000) detected at line 42524 +Underfull \vbox (badness 10000) detected at line 42390 -Overfull \vbox (0.56999pt too high) detected at line 42524 +Overfull \vbox (0.56999pt too high) detected at line 42390 [543] -Underfull \vbox (badness 10000) detected at line 42524 - -Overfull \vbox (0.56999pt too high) detected at line 42524 +Overfull \vbox (2.84741pt too high) detected at line 42534 [544] +Underfull \vbox (badness 10000) detected at line 42534 + +Overfull \vbox (0.56999pt too high) detected at line 42534 + [545] -Underfull \vbox (badness 10000) detected at line 42653 +Underfull \vbox (badness 10000) detected at line 42534 -Overfull \vbox (0.56999pt too high) detected at line 42653 +Overfull \vbox (0.56999pt too high) detected at line 42534 [546] -Overfull \vbox (2.84741pt too high) detected at line 42835 - [547] -Underfull \vbox (badness 10000) detected at line 42835 +Underfull \vbox (badness 10000) detected at line 42663 -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (0.56999pt too high) detected at line 42663 [548] -Underfull \vbox (badness 10000) detected at line 42835 - -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (2.84741pt too high) detected at line 42845 [549] -Underfull \vbox (badness 10000) detected at line 42835 +Underfull \vbox (badness 10000) detected at line 42845 -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (0.56999pt too high) detected at line 42845 [550] -Overfull \vbox (2.84741pt too high) detected at line 43010 +Underfull \vbox (badness 10000) detected at line 42845 + +Overfull \vbox (0.56999pt too high) detected at line 42845 [551] -Underfull \vbox (badness 10000) detected at line 43010 +Underfull \vbox (badness 10000) detected at line 42845 -Overfull \vbox (0.56999pt too high) detected at line 43010 +Overfull \vbox (0.56999pt too high) detected at line 42845 [552] -Underfull \vbox (badness 10000) detected at line 43010 - -Overfull \vbox (0.56999pt too high) detected at line 43010 +Overfull \vbox (2.84741pt too high) detected at line 43020 [553] -Overfull \vbox (2.84741pt too high) detected at line 43160 +Underfull \vbox (badness 10000) detected at line 43020 + +Overfull \vbox (0.56999pt too high) detected at line 43020 [554] -Underfull \vbox (badness 10000) detected at line 43160 +Underfull \vbox (badness 10000) detected at line 43020 -Overfull \vbox (0.56999pt too high) detected at line 43160 +Overfull \vbox (0.56999pt too high) detected at line 43020 [555] -Underfull \vbox (badness 10000) detected at line 43160 - -Overfull \vbox (0.56999pt too high) detected at line 43160 +Overfull \vbox (2.84741pt too high) detected at line 43170 [556] -Overfull \vbox (2.84741pt too high) detected at line 43319 +Underfull \vbox (badness 10000) detected at line 43170 + +Overfull \vbox (0.56999pt too high) detected at line 43170 [557] -Underfull \vbox (badness 10000) detected at line 43319 +Underfull \vbox (badness 10000) detected at line 43170 -Overfull \vbox (0.56999pt too high) detected at line 43319 +Overfull \vbox (0.56999pt too high) detected at line 43170 [558] +Overfull \vbox (2.84741pt too high) detected at line 43329 + [559] -[560] -Underfull \vbox (badness 10000) detected at line 43487 +Underfull \vbox (badness 10000) detected at line 43329 -Overfull \vbox (0.56999pt too high) detected at line 43487 +Overfull \vbox (0.56999pt too high) detected at line 43329 +[560] [561] -Underfull \vbox (badness 10000) detected at line 43487 - -Overfull \vbox (0.56999pt too high) detected at line 43487 - [562] -Overfull \vbox (2.84741pt too high) detected at line 43602 +Underfull \vbox (badness 10000) detected at line 43497 + +Overfull \vbox (0.56999pt too high) detected at line 43497 [563] -Underfull \vbox (badness 10000) detected at line 43602 +Underfull \vbox (badness 10000) detected at line 43497 -Overfull \vbox (0.56999pt too high) detected at line 43602 +Overfull \vbox (0.56999pt too high) detected at line 43497 [564] -Overfull \vbox (2.84741pt too high) detected at line 43817 +Overfull \vbox (2.84741pt too high) detected at line 43612 [565] -Underfull \vbox (badness 10000) detected at line 43817 +Underfull \vbox (badness 10000) detected at line 43612 -Overfull \vbox (0.56999pt too high) detected at line 43817 +Overfull \vbox (0.56999pt too high) detected at line 43612 [566] -Underfull \vbox (badness 10000) detected at line 43817 - -Overfull \vbox (0.56999pt too high) detected at line 43817 +Overfull \vbox (2.84741pt too high) detected at line 43827 [567] -Underfull \vbox (badness 10000) detected at line 43817 +Underfull \vbox (badness 10000) detected at line 43827 -Overfull \vbox (0.56999pt too high) detected at line 43817 +Overfull \vbox (0.56999pt too high) detected at line 43827 [568] -[569] -Overfull \vbox (2.84741pt too high) detected at line 44076 +Underfull \vbox (badness 10000) detected at line 43827 -[570] -Underfull \vbox (badness 10000) detected at line 44076 +Overfull \vbox (0.56999pt too high) detected at line 43827 -Overfull \vbox (0.56999pt too high) detected at line 44076 +[569] +Underfull \vbox (badness 10000) detected at line 43827 -[571] -Underfull \vbox (badness 10000) detected at line 44076 +Overfull \vbox (0.56999pt too high) detected at line 43827 -Overfull \vbox (0.56999pt too high) detected at line 44076 +[570] +[571] +Overfull \vbox (2.84741pt too high) detected at line 44086 [572] +Underfull \vbox (badness 10000) detected at line 44086 + +Overfull \vbox (0.56999pt too high) detected at line 44086 + [573] -[574] -Underfull \vbox (badness 10000) detected at line 44265 +Underfull \vbox (badness 10000) detected at line 44086 -Overfull \vbox (0.56999pt too high) detected at line 44265 +Overfull \vbox (0.56999pt too high) detected at line 44086 +[574] [575] [576] -[577] -[578] -Underfull \vbox (badness 10000) detected at line 44561 +Underfull \vbox (badness 10000) detected at line 44275 -Overfull \vbox (0.56999pt too high) detected at line 44561 +Overfull \vbox (0.56999pt too high) detected at line 44275 +[577] +[578] [579] [580] +Underfull \vbox (badness 10000) detected at line 44571 + +Overfull \vbox (0.56999pt too high) detected at line 44571 + [581] [582] -Overfull \vbox (1.94772pt too high) detected at line 44863 - [583] [584] -Underfull \vbox (badness 10000) detected at line 44985 - -Overfull \vbox (0.56999pt too high) detected at line 44985 +Overfull \vbox (1.94772pt too high) detected at line 44873 [585] [586] -Underfull \vbox (badness 10000) detected at line 45279 +Underfull \vbox (badness 10000) detected at line 44995 -Overfull \vbox (0.56999pt too high) detected at line 45279 +Overfull \vbox (0.56999pt too high) detected at line 44995 [587] -Underfull \vbox (badness 10000) detected at line 45279 - -Overfull \vbox (0.56999pt too high) detected at line 45279 - [588] -Underfull \vbox (badness 10000) detected at line 45279 +Underfull \vbox (badness 10000) detected at line 45289 -Overfull \vbox (0.56999pt too high) detected at line 45279 +Overfull \vbox (0.56999pt too high) detected at line 45289 [589] -Underfull \vbox (badness 10000) detected at line 45279 +Underfull \vbox (badness 10000) detected at line 45289 -Overfull \vbox (0.56999pt too high) detected at line 45279 +Overfull \vbox (0.56999pt too high) detected at line 45289 [590] -Overfull \vbox (2.84741pt too high) detected at line 45330 +Underfull \vbox (badness 10000) detected at line 45289 + +Overfull \vbox (0.56999pt too high) detected at line 45289 [591] -[592] -[593] -Overfull \vbox (2.84741pt too high) detected at line 45791 +Underfull \vbox (badness 10000) detected at line 45289 -[594] -Underfull \vbox (badness 10000) detected at line 45791 +Overfull \vbox (0.56999pt too high) detected at line 45289 -Overfull \vbox (0.56999pt too high) detected at line 45791 +[592] +Overfull \vbox (2.84741pt too high) detected at line 45340 +[593] +[594] [595] -Underfull \vbox (badness 10000) detected at line 45791 - -Overfull \vbox (0.56999pt too high) detected at line 45791 +Overfull \vbox (2.84741pt too high) detected at line 45801 [596] -Underfull \vbox (badness 10000) detected at line 45791 +Underfull \vbox (badness 10000) detected at line 45801 -Overfull \vbox (0.56999pt too high) detected at line 45791 +Overfull \vbox (0.56999pt too high) detected at line 45801 [597] -Underfull \vbox (badness 10000) detected at line 45791 +Underfull \vbox (badness 10000) detected at line 45801 -Overfull \vbox (0.56999pt too high) detected at line 45791 +Overfull \vbox (0.56999pt too high) detected at line 45801 [598] +Underfull \vbox (badness 10000) detected at line 45801 + +Overfull \vbox (0.56999pt too high) detected at line 45801 + [599] -[600] -Underfull \vbox (badness 10000) detected at line 46019 +Underfull \vbox (badness 10000) detected at line 45801 -Overfull \vbox (0.56999pt too high) detected at line 46019 +Overfull \vbox (0.56999pt too high) detected at line 45801 +[600] [601] -Underfull \vbox (badness 10000) detected at line 46019 +[602] +Underfull \vbox (badness 10000) detected at line 46029 -Overfull \vbox (0.56999pt too high) detected at line 46019 +Overfull \vbox (0.56999pt too high) detected at line 46029 -[602] [603] -Overfull \vbox (1.94772pt too high) detected at line 46230 - -[604] -Underfull \vbox (badness 10000) detected at line 46230 +Underfull \vbox (badness 10000) detected at line 46029 -Overfull \vbox (0.56999pt too high) detected at line 46230 +Overfull \vbox (0.56999pt too high) detected at line 46029 +[604] [605] +Overfull \vbox (1.94772pt too high) detected at line 46240 + [606] +Underfull \vbox (badness 10000) detected at line 46240 + +Overfull \vbox (0.56999pt too high) detected at line 46240 + [607] [608] [609] [610] -Underfull \hbox (badness 5652) in paragraph at lines 46520--46522 +[611] +[612] +Underfull \hbox (badness 5652) in paragraph at lines 46530--46532 \T1/lmr/m/n/10 (rtl) syn-the-sis. \T1/lmr/m/it/10 IEEE Std 1076.6-2004 (Re-vi-s ion of IEEE Std 1076.6-1999)\T1/lmr/m/n/10 , 2004. -Underfull \hbox (badness 7685) in paragraph at lines 46523--46525 +Underfull \hbox (badness 7685) in paragraph at lines 46533--46535 []\T1/lmr/m/n/10 IEEE Stan-dards As-so-ci-a-tion and oth-ers. Ieee stan-dard fo r ver-ilog hard-ware de- -Underfull \hbox (badness 5022) in paragraph at lines 46523--46525 +Underfull \hbox (badness 5022) in paragraph at lines 46533--46535 \T1/lmr/m/n/10 scrip-tion lan-guage. \T1/lmr/m/it/10 IEEE Std 1364-2005 (Re-vi- sion of IEEE Std 1364-2001)\T1/lmr/m/n/10 , 2006. -[611] -[612] - [613] - [614] [615] @@ -55867,32 +55304,36 @@ [616] [617] + [618] [619] +[620] + +[621] -Underfull \hbox (badness 10000) in paragraph at lines 47119--47120 +Underfull \hbox (badness 10000) in paragraph at lines 47129--47130 []\T1/lmtt/m/n/10 read_verilog_file_list -[620] +[622] -Underfull \hbox (badness 10000) in paragraph at lines 47196--47197 +Underfull \hbox (badness 10000) in paragraph at lines 47206--47207 []\T1/lmtt/m/n/10 write_functional_cxx -Underfull \hbox (badness 10000) in paragraph at lines 47197--47198 +Underfull \hbox (badness 10000) in paragraph at lines 47207--47208 []\T1/lmtt/m/n/10 write_functional_rosette -Underfull \hbox (badness 10000) in paragraph at lines 47198--47199 +Underfull \hbox (badness 10000) in paragraph at lines 47208--47209 []\T1/lmtt/m/n/10 write_functional_smt2 -[621] -[622] - [623] - [624] -[625] (./yosyshqyosys.ind) (./yosyshqyosys.aux) ) +[625] + +[626] + +[627] (./yosyshqyosys.ind) (./yosyshqyosys.aux) ) (see the transcript file for additional information) -Output written on yosyshqyosys.pdf (637 pages, 3059166 bytes). +Output written on yosyshqyosys.pdf (639 pages, 3059886 bytes). Transcript written on yosyshqyosys.log. Latexmk: Getting log file 'yosyshqyosys.log' Latexmk: Examining 'yosyshqyosys.fls' @@ -57247,10 +56688,10 @@ [173] [174] [175] -Underfull \vbox (badness 5331) detected at line 11767 +Underfull \vbox (badness 5331) detected at line 11772 [176] -Underfull \hbox (badness 10000) in paragraph at lines 11769--11778 +Underfull \hbox (badness 10000) in paragraph at lines 11774--11783 []\T1/lmr/m/n/10 Be-cause we are us-ing the \T1/lmtt/m/n/10 Backend \T1/lmr/m/n /10 class, our \T1/lmtt/m/n/10 "functional_dummy" \T1/lmr/m/n/10 is reg-is-tere d as the @@ -57258,23 +56699,23 @@ [177] [178] [179] -Underfull \vbox (badness 1072) detected at line 12056 +Underfull \vbox (badness 1072) detected at line 12061 [180] [181] [182] [183] -Underfull \hbox (badness 10000) in paragraph at lines 12227--12227 +Underfull \hbox (badness 10000) in paragraph at lines 12232--12232 []\T1/lmr/m/n/10 Listing 4.22: |[]iterating over Func-tion-alIR nodes in [184] -Underfull \hbox (badness 10000) in paragraph at lines 12252--12252 +Underfull \hbox (badness 10000) in paragraph at lines 12257--12257 []\T1/lmr/m/n/10 Listing 4.24: |[]diff of out-put/next state han-dling [185] [186] [187] -Underfull \vbox (badness 4001) detected at line 12529 +Underfull \vbox (badness 4001) detected at line 12534 [188] [189 <./red_or3x1.pdf>] @@ -57282,15 +56723,15 @@ [191 <./mymul.pdf>] [192] [193 <./mulshift.pdf>] -Underfull \hbox (badness 5490) in paragraph at lines 12842--12845 +Underfull \hbox (badness 5490) in paragraph at lines 12847--12850 []\T1/lmr/m/n/10 Each bit of the port cor-re-lates to an \T1/lmtt/m/n/10 _TECHM AP_BITS_CONNMAP_ \T1/lmr/m/n/10 bits wide num-ber in -Underfull \hbox (badness 10000) in paragraph at lines 12847--12850 +Underfull \hbox (badness 10000) in paragraph at lines 12852--12855 []\T1/lmr/m/n/10 Each unique sig-nal bit is as-signed its own num-ber. Iden-ti- cal fields in the -Overfull \vbox (0.52754pt too high) detected at line 12902 +Overfull \vbox (0.52754pt too high) detected at line 12907 [194] [195 <./addshift.pdf>] @@ -57331,30 +56772,28 @@ [224] Chapter 8. -Overfull \vbox (1.34746pt too high) detected at line 15232 +Overfull \vbox (1.34746pt too high) detected at line 15242 [225] [226] -Underfull \vbox (badness 10000) detected at line 15467 - -Overfull \vbox (0.56999pt too high) detected at line 15467 +Underfull \vbox (badness 4954) detected at line 15477 [227] -Underfull \vbox (badness 10000) detected at line 15467 +Underfull \vbox (badness 10000) detected at line 15477 -Overfull \vbox (0.56999pt too high) detected at line 15467 +Overfull \vbox (0.56999pt too high) detected at line 15477 [228] -Underfull \vbox (badness 10000) detected at line 15467 +Underfull \vbox (badness 10000) detected at line 15477 -Overfull \vbox (0.56999pt too high) detected at line 15467 +Overfull \vbox (0.56999pt too high) detected at line 15477 [229] [230] -Chapter 9. - [231] [232] +Chapter 9. + [233] [234] [235] @@ -57377,10 +56816,10 @@ [252] [253] [254] -Overfull \vbox (2.36986pt too high) detected at line 18216 - [255] [256] +Overfull \vbox (2.36986pt too high) detected at line 18226 + [257] [258] [259] @@ -57399,69 +56838,69 @@ [272] [273] [274] -Underfull \vbox (badness 10000) detected at line 20043 - -Overfull \vbox (2.76991pt too high) detected at line 20043 - [275] [276] -Underfull \vbox (badness 10000) detected at line 20182 +Underfull \vbox (badness 10000) detected at line 20053 -Overfull \vbox (2.76991pt too high) detected at line 20182 +Overfull \vbox (2.76991pt too high) detected at line 20053 [277] -Underfull \vbox (badness 10000) detected at line 20182 +[278] +Underfull \vbox (badness 10000) detected at line 20192 -Overfull \vbox (0.56999pt too high) detected at line 20182 +Overfull \vbox (2.76991pt too high) detected at line 20192 -[278] [279] +Underfull \vbox (badness 10000) detected at line 20192 + +Overfull \vbox (0.56999pt too high) detected at line 20192 + [280] [281] [282] [283] -Underfull \vbox (badness 10000) detected at line 20597 - -Overfull \vbox (0.56999pt too high) detected at line 20597 - [284] [285] +Underfull \vbox (badness 10000) detected at line 20607 + +Overfull \vbox (0.56999pt too high) detected at line 20607 + [286] [287] [288] -Underfull \vbox (badness 10000) detected at line 21032 - -Overfull \vbox (0.56999pt too high) detected at line 21032 - [289] -Underfull \vbox (badness 10000) detected at line 21032 +[290] +Underfull \vbox (badness 10000) detected at line 21042 -Overfull \vbox (0.56999pt too high) detected at line 21032 +Overfull \vbox (0.56999pt too high) detected at line 21042 -[290] [291] -Underfull \vbox (badness 10000) detected at line 21170 +Underfull \vbox (badness 10000) detected at line 21042 -Overfull \vbox (0.56999pt too high) detected at line 21170 +Overfull \vbox (0.56999pt too high) detected at line 21042 [292] [293] -[294] -Overfull \vbox (0.94846pt too high) detected at line 21411 +Underfull \vbox (badness 10000) detected at line 21180 +Overfull \vbox (0.56999pt too high) detected at line 21180 + +[294] [295] [296] -Underfull \vbox (badness 10000) detected at line 21546 - -Overfull \vbox (0.56999pt too high) detected at line 21546 +Overfull \vbox (0.94846pt too high) detected at line 21421 [297] -Underfull \vbox (badness 10000) detected at line 21546 +[298] +Underfull \vbox (badness 10000) detected at line 21556 -Overfull \vbox (0.56999pt too high) detected at line 21546 +Overfull \vbox (0.56999pt too high) detected at line 21556 -[298] [299] +Underfull \vbox (badness 10000) detected at line 21556 + +Overfull \vbox (0.56999pt too high) detected at line 21556 + [300] [301] [302] @@ -57551,87 +56990,87 @@ [386] [387] [388] -Chapter 10. - [389] [390] -[391] -Underfull \vbox (badness 10000) detected at line 32041 - -Overfull \vbox (0.56999pt too high) detected at line 32041 +Chapter 10. +[391] [392] -Underfull \vbox (badness 10000) detected at line 32041 - -Overfull \vbox (0.56999pt too high) detected at line 32041 - [393] -Overfull \vbox (2.84741pt too high) detected at line 32199 +Underfull \vbox (badness 10000) detected at line 32051 + +Overfull \vbox (0.56999pt too high) detected at line 32051 [394] -Underfull \vbox (badness 10000) detected at line 32199 +Underfull \vbox (badness 10000) detected at line 32051 -Overfull \vbox (0.56999pt too high) detected at line 32199 +Overfull \vbox (0.56999pt too high) detected at line 32051 [395] -Underfull \vbox (badness 10000) detected at line 32199 - -Overfull \vbox (0.56999pt too high) detected at line 32199 +Overfull \vbox (2.84741pt too high) detected at line 32209 [396] +Underfull \vbox (badness 10000) detected at line 32209 + +Overfull \vbox (0.56999pt too high) detected at line 32209 + [397] -Underfull \vbox (badness 10000) detected at line 32305 +Underfull \vbox (badness 10000) detected at line 32209 -Underfull \vbox (badness 10000) detected at line 32305 +Overfull \vbox (0.56999pt too high) detected at line 32209 [398] -Overfull \vbox (2.84741pt too high) detected at line 32403 - [399] -Underfull \vbox (badness 10000) detected at line 32403 +Underfull \vbox (badness 10000) detected at line 32315 -Overfull \vbox (0.56999pt too high) detected at line 32403 +Underfull \vbox (badness 10000) detected at line 32315 [400] +Overfull \vbox (2.84741pt too high) detected at line 32413 + [401] -[402] -Overfull \vbox (2.84741pt too high) detected at line 32587 +Underfull \vbox (badness 10000) detected at line 32413 +Overfull \vbox (0.56999pt too high) detected at line 32413 + +[402] [403] [404] -[405] -Overfull \vbox (2.84741pt too high) detected at line 32828 +Overfull \vbox (2.84741pt too high) detected at line 32597 +[405] [406] [407] +Overfull \vbox (2.84741pt too high) detected at line 32838 + [408] [409] [410] [411] -Overfull \vbox (1.94772pt too high) detected at line 33272 - [412] -Overfull \vbox (2.84741pt too high) detected at line 33334 - [413] +Overfull \vbox (1.94772pt too high) detected at line 33282 + [414] +Overfull \vbox (2.84741pt too high) detected at line 33344 + [415] [416] -Overfull \vbox (1.94772pt too high) detected at line 33667 - [417] [418] +Overfull \vbox (1.94772pt too high) detected at line 33677 + [419] [420] [421] [422] -Overfull \vbox (1.94772pt too high) detected at line 34144 - [423] -Overfull \vbox (2.84741pt too high) detected at line 34187 - [424] +Overfull \vbox (1.94772pt too high) detected at line 34154 + [425] +Overfull \vbox (2.84741pt too high) detected at line 34197 + [426] [427] [428] @@ -57639,51 +57078,51 @@ [430] [431] [432] -Overfull \vbox (1.94772pt too high) detected at line 34893 - [433] -Overfull \vbox (2.84741pt too high) detected at line 34993 - [434] +Overfull \vbox (1.94772pt too high) detected at line 34903 + [435] +Overfull \vbox (2.84741pt too high) detected at line 35003 + [436] [437] -Overfull \vbox (2.84741pt too high) detected at line 35231 - [438] [439] -Overfull \vbox (1.94772pt too high) detected at line 35378 +Overfull \vbox (2.84741pt too high) detected at line 35241 [440] [441] -Overfull \vbox (1.94772pt too high) detected at line 35511 +Overfull \vbox (1.94772pt too high) detected at line 35388 [442] [443] +Overfull \vbox (1.94772pt too high) detected at line 35521 + [444] [445] [446] -Underfull \vbox (badness 10000) detected at line 35893 - -Overfull \vbox (0.56999pt too high) detected at line 35893 - [447] [448] -Underfull \vbox (badness 10000) detected at line 36040 +Underfull \vbox (badness 10000) detected at line 35903 -Overfull \vbox (0.56999pt too high) detected at line 36040 +Overfull \vbox (0.56999pt too high) detected at line 35903 [449] [450] +Underfull \vbox (badness 10000) detected at line 36050 + +Overfull \vbox (0.56999pt too high) detected at line 36050 + [451] [452] [453] [454] [455] -Overfull \vbox (1.94772pt too high) detected at line 36628 - [456] [457] +Overfull \vbox (1.94772pt too high) detected at line 36638 + [458] [459] [460] @@ -57691,15 +57130,15 @@ [462] [463] [464] -Overfull \vbox (2.84741pt too high) detected at line 37362 - [465] -Underfull \vbox (badness 10000) detected at line 37362 - -Overfull \vbox (0.56999pt too high) detected at line 37362 - [466] +Overfull \vbox (2.84741pt too high) detected at line 37372 + [467] +Underfull \vbox (badness 10000) detected at line 37372 + +Overfull \vbox (0.56999pt too high) detected at line 37372 + [468] [469] [470] @@ -57711,439 +57150,437 @@ [476] [477] [478] -Overfull \vbox (1.94772pt too high) detected at line 38409 - [479] [480] +Overfull \vbox (1.94772pt too high) detected at line 38419 + [481] [482] [483] [484] -Overfull \vbox (2.84741pt too high) detected at line 38933 - [485] [486] +Overfull \vbox (2.84741pt too high) detected at line 38943 + [487] [488] -Underfull \vbox (badness 10000) detected at line 39254 - -Overfull \vbox (0.56999pt too high) detected at line 39254 - [489] -Underfull \vbox (badness 10000) detected at line 39254 +[490] +Underfull \vbox (badness 10000) detected at line 39264 -Overfull \vbox (0.56999pt too high) detected at line 39254 +Overfull \vbox (0.56999pt too high) detected at line 39264 -[490] [491] -[492] -[493] -Underfull \vbox (badness 10000) detected at line 39617 +Underfull \vbox (badness 10000) detected at line 39264 -Overfull \vbox (0.56999pt too high) detected at line 39617 +Overfull \vbox (0.56999pt too high) detected at line 39264 +[492] +[493] [494] -Underfull \vbox (badness 10000) detected at line 39617 +[495] +Underfull \vbox (badness 10000) detected at line 39627 -Overfull \vbox (0.56999pt too high) detected at line 39617 +Overfull \vbox (0.56999pt too high) detected at line 39627 -[495] [496] -[497] -Overfull \vbox (1.94772pt too high) detected at line 39779 +Underfull \vbox (badness 10000) detected at line 39627 -[498] -Overfull \vbox (2.84741pt too high) detected at line 40027 +Overfull \vbox (0.56999pt too high) detected at line 39627 +[497] +[498] [499] -Underfull \vbox (badness 10000) detected at line 40027 - -Overfull \vbox (0.56999pt too high) detected at line 40027 +Overfull \vbox (1.94772pt too high) detected at line 39789 [500] -Underfull \vbox (badness 10000) detected at line 40027 - -Overfull \vbox (0.56999pt too high) detected at line 40027 +Overfull \vbox (2.84741pt too high) detected at line 40037 [501] -Underfull \vbox (badness 10000) detected at line 40027 +Underfull \vbox (badness 10000) detected at line 40037 -Overfull \vbox (0.56999pt too high) detected at line 40027 +Overfull \vbox (0.56999pt too high) detected at line 40037 [502] +Underfull \vbox (badness 10000) detected at line 40037 + +Overfull \vbox (0.56999pt too high) detected at line 40037 + [503] +Underfull \vbox (badness 10000) detected at line 40037 + +Overfull \vbox (0.56999pt too high) detected at line 40037 + [504] [505] [506] -Underfull \vbox (badness 10000) detected at line 40349 - -Overfull \vbox (0.56999pt too high) detected at line 40349 - [507] -Overfull \vbox (2.84741pt too high) detected at line 40419 - [508] -Overfull \vbox (2.84741pt too high) detected at line 40548 +Underfull \vbox (badness 10000) detected at line 40359 -[509] -Underfull \vbox (badness 10000) detected at line 40548 +Overfull \vbox (0.56999pt too high) detected at line 40359 -Overfull \vbox (0.56999pt too high) detected at line 40548 +[509] +Overfull \vbox (2.84741pt too high) detected at line 40429 [510] +Overfull \vbox (2.84741pt too high) detected at line 40558 + [511] -Overfull \vbox (1.94772pt too high) detected at line 40660 +Underfull \vbox (badness 10000) detected at line 40558 + +Overfull \vbox (0.56999pt too high) detected at line 40558 [512] [513] -[514] -Overfull \vbox (1.94772pt too high) detected at line 40946 +Overfull \vbox (1.94772pt too high) detected at line 40670 +[514] [515] -Underfull \vbox (badness 10000) detected at line 40946 - -Overfull \vbox (0.56999pt too high) detected at line 40946 - [516] -Overfull \vbox (2.84741pt too high) detected at line 41031 +Overfull \vbox (1.94772pt too high) detected at line 40956 [517] -Overfull \vbox (2.84741pt too high) detected at line 41140 +Underfull \vbox (badness 10000) detected at line 40956 -[518] -Underfull \vbox (badness 10000) detected at line 41140 +Overfull \vbox (0.56999pt too high) detected at line 40956 -Overfull \vbox (0.56999pt too high) detected at line 41140 +[518] +Overfull \vbox (2.84741pt too high) detected at line 41041 [519] -Overfull \vbox (2.84741pt too high) detected at line 41240 +Overfull \vbox (2.84741pt too high) detected at line 41150 [520] -Underfull \vbox (badness 10000) detected at line 41240 +Underfull \vbox (badness 10000) detected at line 41150 -Overfull \vbox (0.56999pt too high) detected at line 41240 +Overfull \vbox (0.56999pt too high) detected at line 41150 [521] -Overfull \vbox (2.84741pt too high) detected at line 41320 +Overfull \vbox (2.84741pt too high) detected at line 41250 [522] -Overfull \vbox (2.84741pt too high) detected at line 41498 +Underfull \vbox (badness 10000) detected at line 41250 -[523] -Underfull \vbox (badness 10000) detected at line 41498 +Overfull \vbox (0.56999pt too high) detected at line 41250 -Overfull \vbox (0.56999pt too high) detected at line 41498 +[523] +Overfull \vbox (2.84741pt too high) detected at line 41330 [524] -Underfull \vbox (badness 10000) detected at line 41498 - -Overfull \vbox (0.56999pt too high) detected at line 41498 +Overfull \vbox (2.84741pt too high) detected at line 41508 [525] -[526] -[527] -Overfull \vbox (2.84741pt too high) detected at line 41784 +Underfull \vbox (badness 10000) detected at line 41508 -[528] -Underfull \vbox (badness 10000) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41508 -Overfull \vbox (0.56999pt too high) detected at line 41784 +[526] +Underfull \vbox (badness 10000) detected at line 41508 -[529] -Underfull \vbox (badness 10000) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41508 -Overfull \vbox (0.56999pt too high) detected at line 41784 +[527] +[528] +[529] +Overfull \vbox (2.84741pt too high) detected at line 41794 [530] -Underfull \vbox (badness 10000) detected at line 41784 +Underfull \vbox (badness 10000) detected at line 41794 -Overfull \vbox (0.56999pt too high) detected at line 41784 +Overfull \vbox (0.56999pt too high) detected at line 41794 [531] -Overfull \vbox (2.84741pt too high) detected at line 41947 +Underfull \vbox (badness 10000) detected at line 41794 + +Overfull \vbox (0.56999pt too high) detected at line 41794 [532] -Underfull \vbox (badness 10000) detected at line 41947 +Underfull \vbox (badness 10000) detected at line 41794 -Overfull \vbox (0.56999pt too high) detected at line 41947 +Overfull \vbox (0.56999pt too high) detected at line 41794 [533] -Underfull \vbox (badness 10000) detected at line 41947 - -Overfull \vbox (0.56999pt too high) detected at line 41947 +Overfull \vbox (2.84741pt too high) detected at line 41957 [534] -Overfull \vbox (2.84741pt too high) detected at line 42084 +Underfull \vbox (badness 10000) detected at line 41957 + +Overfull \vbox (0.56999pt too high) detected at line 41957 [535] -Underfull \vbox (badness 10000) detected at line 42084 +Underfull \vbox (badness 10000) detected at line 41957 -Overfull \vbox (0.56999pt too high) detected at line 42084 +Overfull \vbox (0.56999pt too high) detected at line 41957 [536] -Overfull \vbox (2.84741pt too high) detected at line 42184 +Overfull \vbox (2.84741pt too high) detected at line 42094 [537] -Underfull \vbox (badness 10000) detected at line 42184 +Underfull \vbox (badness 10000) detected at line 42094 -Overfull \vbox (0.56999pt too high) detected at line 42184 +Overfull \vbox (0.56999pt too high) detected at line 42094 [538] -Overfull \vbox (2.84741pt too high) detected at line 42380 +Overfull \vbox (2.84741pt too high) detected at line 42194 [539] -Underfull \vbox (badness 10000) detected at line 42380 +Underfull \vbox (badness 10000) detected at line 42194 -Overfull \vbox (0.56999pt too high) detected at line 42380 +Overfull \vbox (0.56999pt too high) detected at line 42194 [540] -Underfull \vbox (badness 10000) detected at line 42380 - -Overfull \vbox (0.56999pt too high) detected at line 42380 +Overfull \vbox (2.84741pt too high) detected at line 42390 [541] -Overfull \vbox (2.84741pt too high) detected at line 42524 +Underfull \vbox (badness 10000) detected at line 42390 + +Overfull \vbox (0.56999pt too high) detected at line 42390 [542] -Underfull \vbox (badness 10000) detected at line 42524 +Underfull \vbox (badness 10000) detected at line 42390 -Overfull \vbox (0.56999pt too high) detected at line 42524 +Overfull \vbox (0.56999pt too high) detected at line 42390 [543] -Underfull \vbox (badness 10000) detected at line 42524 - -Overfull \vbox (0.56999pt too high) detected at line 42524 +Overfull \vbox (2.84741pt too high) detected at line 42534 [544] +Underfull \vbox (badness 10000) detected at line 42534 + +Overfull \vbox (0.56999pt too high) detected at line 42534 + [545] -Underfull \vbox (badness 10000) detected at line 42653 +Underfull \vbox (badness 10000) detected at line 42534 -Overfull \vbox (0.56999pt too high) detected at line 42653 +Overfull \vbox (0.56999pt too high) detected at line 42534 [546] -Overfull \vbox (2.84741pt too high) detected at line 42835 - [547] -Underfull \vbox (badness 10000) detected at line 42835 +Underfull \vbox (badness 10000) detected at line 42663 -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (0.56999pt too high) detected at line 42663 [548] -Underfull \vbox (badness 10000) detected at line 42835 - -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (2.84741pt too high) detected at line 42845 [549] -Underfull \vbox (badness 10000) detected at line 42835 +Underfull \vbox (badness 10000) detected at line 42845 -Overfull \vbox (0.56999pt too high) detected at line 42835 +Overfull \vbox (0.56999pt too high) detected at line 42845 [550] -Overfull \vbox (2.84741pt too high) detected at line 43010 +Underfull \vbox (badness 10000) detected at line 42845 + +Overfull \vbox (0.56999pt too high) detected at line 42845 [551] -Underfull \vbox (badness 10000) detected at line 43010 +Underfull \vbox (badness 10000) detected at line 42845 -Overfull \vbox (0.56999pt too high) detected at line 43010 +Overfull \vbox (0.56999pt too high) detected at line 42845 [552] -Underfull \vbox (badness 10000) detected at line 43010 - -Overfull \vbox (0.56999pt too high) detected at line 43010 +Overfull \vbox (2.84741pt too high) detected at line 43020 [553] -Overfull \vbox (2.84741pt too high) detected at line 43160 +Underfull \vbox (badness 10000) detected at line 43020 + +Overfull \vbox (0.56999pt too high) detected at line 43020 [554] -Underfull \vbox (badness 10000) detected at line 43160 +Underfull \vbox (badness 10000) detected at line 43020 -Overfull \vbox (0.56999pt too high) detected at line 43160 +Overfull \vbox (0.56999pt too high) detected at line 43020 [555] -Underfull \vbox (badness 10000) detected at line 43160 - -Overfull \vbox (0.56999pt too high) detected at line 43160 +Overfull \vbox (2.84741pt too high) detected at line 43170 [556] -Overfull \vbox (2.84741pt too high) detected at line 43319 +Underfull \vbox (badness 10000) detected at line 43170 + +Overfull \vbox (0.56999pt too high) detected at line 43170 [557] -Underfull \vbox (badness 10000) detected at line 43319 +Underfull \vbox (badness 10000) detected at line 43170 -Overfull \vbox (0.56999pt too high) detected at line 43319 +Overfull \vbox (0.56999pt too high) detected at line 43170 [558] +Overfull \vbox (2.84741pt too high) detected at line 43329 + [559] -[560] -Underfull \vbox (badness 10000) detected at line 43487 +Underfull \vbox (badness 10000) detected at line 43329 -Overfull \vbox (0.56999pt too high) detected at line 43487 +Overfull \vbox (0.56999pt too high) detected at line 43329 +[560] [561] -Underfull \vbox (badness 10000) detected at line 43487 - -Overfull \vbox (0.56999pt too high) detected at line 43487 - [562] -Overfull \vbox (2.84741pt too high) detected at line 43602 +Underfull \vbox (badness 10000) detected at line 43497 + +Overfull \vbox (0.56999pt too high) detected at line 43497 [563] -Underfull \vbox (badness 10000) detected at line 43602 +Underfull \vbox (badness 10000) detected at line 43497 -Overfull \vbox (0.56999pt too high) detected at line 43602 +Overfull \vbox (0.56999pt too high) detected at line 43497 [564] -Overfull \vbox (2.84741pt too high) detected at line 43817 +Overfull \vbox (2.84741pt too high) detected at line 43612 [565] -Underfull \vbox (badness 10000) detected at line 43817 +Underfull \vbox (badness 10000) detected at line 43612 -Overfull \vbox (0.56999pt too high) detected at line 43817 +Overfull \vbox (0.56999pt too high) detected at line 43612 [566] -Underfull \vbox (badness 10000) detected at line 43817 - -Overfull \vbox (0.56999pt too high) detected at line 43817 +Overfull \vbox (2.84741pt too high) detected at line 43827 [567] -Underfull \vbox (badness 10000) detected at line 43817 +Underfull \vbox (badness 10000) detected at line 43827 -Overfull \vbox (0.56999pt too high) detected at line 43817 +Overfull \vbox (0.56999pt too high) detected at line 43827 [568] -[569] -Overfull \vbox (2.84741pt too high) detected at line 44076 +Underfull \vbox (badness 10000) detected at line 43827 -[570] -Underfull \vbox (badness 10000) detected at line 44076 +Overfull \vbox (0.56999pt too high) detected at line 43827 + +[569] +Underfull \vbox (badness 10000) detected at line 43827 -Overfull \vbox (0.56999pt too high) detected at line 44076 +Overfull \vbox (0.56999pt too high) detected at line 43827 +[570] [571] -Underfull \vbox (badness 10000) detected at line 44076 - -Overfull \vbox (0.56999pt too high) detected at line 44076 +Overfull \vbox (2.84741pt too high) detected at line 44086 [572] +Underfull \vbox (badness 10000) detected at line 44086 + +Overfull \vbox (0.56999pt too high) detected at line 44086 + [573] -[574] -Underfull \vbox (badness 10000) detected at line 44265 +Underfull \vbox (badness 10000) detected at line 44086 -Overfull \vbox (0.56999pt too high) detected at line 44265 +Overfull \vbox (0.56999pt too high) detected at line 44086 +[574] [575] [576] -[577] -[578] -Underfull \vbox (badness 10000) detected at line 44561 +Underfull \vbox (badness 10000) detected at line 44275 -Overfull \vbox (0.56999pt too high) detected at line 44561 +Overfull \vbox (0.56999pt too high) detected at line 44275 +[577] +[578] [579] [580] +Underfull \vbox (badness 10000) detected at line 44571 + +Overfull \vbox (0.56999pt too high) detected at line 44571 + [581] [582] -Overfull \vbox (1.94772pt too high) detected at line 44863 - [583] [584] -Underfull \vbox (badness 10000) detected at line 44985 - -Overfull \vbox (0.56999pt too high) detected at line 44985 +Overfull \vbox (1.94772pt too high) detected at line 44873 [585] [586] -Underfull \vbox (badness 10000) detected at line 45279 +Underfull \vbox (badness 10000) detected at line 44995 -Overfull \vbox (0.56999pt too high) detected at line 45279 +Overfull \vbox (0.56999pt too high) detected at line 44995 [587] -Underfull \vbox (badness 10000) detected at line 45279 - -Overfull \vbox (0.56999pt too high) detected at line 45279 - [588] -Underfull \vbox (badness 10000) detected at line 45279 +Underfull \vbox (badness 10000) detected at line 45289 -Overfull \vbox (0.56999pt too high) detected at line 45279 +Overfull \vbox (0.56999pt too high) detected at line 45289 [589] -Underfull \vbox (badness 10000) detected at line 45279 +Underfull \vbox (badness 10000) detected at line 45289 -Overfull \vbox (0.56999pt too high) detected at line 45279 +Overfull \vbox (0.56999pt too high) detected at line 45289 [590] -Overfull \vbox (2.84741pt too high) detected at line 45330 +Underfull \vbox (badness 10000) detected at line 45289 + +Overfull \vbox (0.56999pt too high) detected at line 45289 [591] -[592] -[593] -Overfull \vbox (2.84741pt too high) detected at line 45791 +Underfull \vbox (badness 10000) detected at line 45289 -[594] -Underfull \vbox (badness 10000) detected at line 45791 +Overfull \vbox (0.56999pt too high) detected at line 45289 -Overfull \vbox (0.56999pt too high) detected at line 45791 +[592] +Overfull \vbox (2.84741pt too high) detected at line 45340 +[593] +[594] [595] -Underfull \vbox (badness 10000) detected at line 45791 - -Overfull \vbox (0.56999pt too high) detected at line 45791 +Overfull \vbox (2.84741pt too high) detected at line 45801 [596] -Underfull \vbox (badness 10000) detected at line 45791 +Underfull \vbox (badness 10000) detected at line 45801 -Overfull \vbox (0.56999pt too high) detected at line 45791 +Overfull \vbox (0.56999pt too high) detected at line 45801 [597] -Underfull \vbox (badness 10000) detected at line 45791 +Underfull \vbox (badness 10000) detected at line 45801 -Overfull \vbox (0.56999pt too high) detected at line 45791 +Overfull \vbox (0.56999pt too high) detected at line 45801 [598] +Underfull \vbox (badness 10000) detected at line 45801 + +Overfull \vbox (0.56999pt too high) detected at line 45801 + [599] -[600] -Underfull \vbox (badness 10000) detected at line 46019 +Underfull \vbox (badness 10000) detected at line 45801 -Overfull \vbox (0.56999pt too high) detected at line 46019 +Overfull \vbox (0.56999pt too high) detected at line 45801 +[600] [601] -Underfull \vbox (badness 10000) detected at line 46019 +[602] +Underfull \vbox (badness 10000) detected at line 46029 -Overfull \vbox (0.56999pt too high) detected at line 46019 +Overfull \vbox (0.56999pt too high) detected at line 46029 -[602] [603] -Overfull \vbox (1.94772pt too high) detected at line 46230 - -[604] -Underfull \vbox (badness 10000) detected at line 46230 +Underfull \vbox (badness 10000) detected at line 46029 -Overfull \vbox (0.56999pt too high) detected at line 46230 +Overfull \vbox (0.56999pt too high) detected at line 46029 +[604] [605] +Overfull \vbox (1.94772pt too high) detected at line 46240 + [606] +Underfull \vbox (badness 10000) detected at line 46240 + +Overfull \vbox (0.56999pt too high) detected at line 46240 + [607] [608] [609] [610] -Underfull \hbox (badness 5652) in paragraph at lines 46520--46522 +[611] +[612] +Underfull \hbox (badness 5652) in paragraph at lines 46530--46532 \T1/lmr/m/n/10 (rtl) syn-the-sis. \T1/lmr/m/it/10 IEEE Std 1076.6-2004 (Re-vi-s ion of IEEE Std 1076.6-1999)\T1/lmr/m/n/10 , 2004. -Underfull \hbox (badness 7685) in paragraph at lines 46523--46525 +Underfull \hbox (badness 7685) in paragraph at lines 46533--46535 []\T1/lmr/m/n/10 IEEE Stan-dards As-so-ci-a-tion and oth-ers. Ieee stan-dard fo r ver-ilog hard-ware de- -Underfull \hbox (badness 5022) in paragraph at lines 46523--46525 +Underfull \hbox (badness 5022) in paragraph at lines 46533--46535 \T1/lmr/m/n/10 scrip-tion lan-guage. \T1/lmr/m/it/10 IEEE Std 1364-2005 (Re-vi- sion of IEEE Std 1364-2001)\T1/lmr/m/n/10 , 2006. -[611] -[612] - [613] - [614] [615] @@ -58151,32 +57588,36 @@ [616] [617] + [618] [619] +[620] + +[621] -Underfull \hbox (badness 10000) in paragraph at lines 47119--47120 +Underfull \hbox (badness 10000) in paragraph at lines 47129--47130 []\T1/lmtt/m/n/10 read_verilog_file_list -[620] +[622] -Underfull \hbox (badness 10000) in paragraph at lines 47196--47197 +Underfull \hbox (badness 10000) in paragraph at lines 47206--47207 []\T1/lmtt/m/n/10 write_functional_cxx -Underfull \hbox (badness 10000) in paragraph at lines 47197--47198 +Underfull \hbox (badness 10000) in paragraph at lines 47207--47208 []\T1/lmtt/m/n/10 write_functional_rosette -Underfull \hbox (badness 10000) in paragraph at lines 47198--47199 +Underfull \hbox (badness 10000) in paragraph at lines 47208--47209 []\T1/lmtt/m/n/10 write_functional_smt2 -[621] -[622] - [623] - [624] -[625] (./yosyshqyosys.ind) (./yosyshqyosys.aux) ) +[625] + +[626] + +[627] (./yosyshqyosys.ind) (./yosyshqyosys.aux) ) (see the transcript file for additional information) -Output written on yosyshqyosys.pdf (637 pages, 3059166 bytes). +Output written on yosyshqyosys.pdf (639 pages, 3059886 bytes). Transcript written on yosyshqyosys.log. Latexmk: Getting log file 'yosyshqyosys.log' Latexmk: Examining 'yosyshqyosys.fls' @@ -58215,24 +57656,42 @@ debian/rules override_dh_auto_test-arch make[1]: Entering directory '/build/reproducible-path/yosys-0.52' dh_auto_test -- PATH="$PWD:$PATH" - make -j3 test PATH=/build/reproducible-path/yosys-0.52:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games + make -j4 test PATH=/build/reproducible-path/yosys-0.52:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/i/capture/the/path make[2]: Entering directory '/build/reproducible-path/yosys-0.52' [Makefile.conf] CONFIG := gcc [Makefile.conf] STRIP=: make -C tests/arch/anlogic -f run-test.mk make -C tests/arch/ecp5 -f run-test.mk make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/arch/anlogic' +make -C tests/arch/efinix -f run-test.mk make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/arch/ecp5' +make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/arch/efinix' +Passed efinix-add_sub.ys +Passed efinix-adffs.ys Passed anlogic-add_sub.ys +Passed efinix-counter.ys Passed ecp5-add_sub.ys +Passed efinix-dffs.ys Passed anlogic-counter.ys +Passed efinix-fsm.ys +Passed efinix-latches.ys +Passed efinix-logic.ys +Passed efinix-lutram.ys Passed anlogic-dffs.ys +Passed efinix-mux.ys +Passed efinix-shifter.ys +Passed efinix-tribuf.ys +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/arch/efinix' +...passed tests in tests/arch/efinix +make -C tests/arch/gatemate -f run-test.mk +make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/arch/gatemate' Passed anlogic-fsm.ys Passed ecp5-adffs.ys +Passed gatemate-add_sub.ys Passed anlogic-blockram.ys Passed ecp5-bug1459.ys -Passed anlogic-logic.ys Passed anlogic-latches.ys +Passed anlogic-logic.ys Passed ecp5-bug1598.ys Passed ecp5-bug1630.ys Warning: Literal has a width of 16 bit, but value requires 184 bit. (< DATA[1] @@ -59231,15 +58338,6 @@ cell $memrd$\mem$< DATA[0] wire \y1 [0] source: < RD_DATA[1] @@ -59317,7 +58415,6 @@ ERROR: Found 8 problems in 'check -assert'. Expected error pattern 'Found [0-9]+ problems in 'check -assert'' found !!! Passed various-check_3.ys -Passed techmap-dfflegalize_dffsr_init.ys Warning: found logic loop in module top: cell $auto$memory_dff.cc:512:handle_rd_port$62 ($logic_not) A[0] --> Y[0] @@ -59329,25 +58426,9 @@ Passed various-check_4.ys Warning: wire '\a_q' is assigned in a block at < Y[0] @@ -60246,6 +59519,8 @@ ERROR: Command stdout did have a line matching given regex "giraffe". Expected error pattern 'stdout did have a line' found !!! Passed various-exec.ys +Passed qlf_k6n10f-mux.ys +Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Passed various-fib.ys Passed various-fib_tern.ys Passed various-func_port_implied_dir.ys @@ -60256,6 +59531,7 @@ Passed various-hierarchy_defer.ys Passed various-hierarchy_generate.ys Passed various-hierarchy_param.ys +Warning: Complex async reset for dff `\Q'. Passed various-ice40_mince_abc9.ys < ok Passed various-sv_implicit_ports.sh Passed various-svalways.sh make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/various' ...passed tests in tests/various +cd tests/memories && bash run-test.sh "" "" +make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/memories' +Test: amber23_sram_byte_en -> ok +Test: firrtl_938 -> ok +Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. +Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. +Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. +Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. +Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. +Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. +Test: implicit_en -> ok +Passed verilog-dynamic_range_lhs.sh +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/verilog' +...passed tests in tests/verilog cd tests/aiger && bash run-test.sh "" "" Checking and_.aag. Checking and_to_bad_out.aag. @@ -60555,7 +59905,6 @@ Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Checking halfadder.aag. -Test: firrtl_938 -> ok Checking inverter.aag. Checking notcnt1.aag. Warning: The new network has no primary inputs. It is recommended @@ -60571,7 +59920,6 @@ Warning: The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. Checking and_.aig. -Test: implicit_en -> ok Checking and_to_bad_out.aig. Checking buffer.aig. Checking cnt1.aig. @@ -60610,52 +59958,58 @@ cd tests/simple && bash run-test.sh "" make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/simple' Test: arrays02 -> ok -Test: arrays03 -> ok Test: issue00335 -> ok +Test: arrays03 -> ok Test: issue00710 -> ok Test: no_implicit_en -> ok +Test: read_arst -> ok Test: asgn_binop -> ok Test: case_expr_extend -> ok Test: case_expr_query -> ok -Test: read_arst -> ok +Test: read_two_mux -> ok Test: defvalue -> ok Test: implicit_ports -> ok +Test: shared_ports -> ok Test: lesser_size_cast -> ok Test: local_loop_var -> ok -Test: read_two_mux -> ok +Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. +Test: simple_sram_byte_en -> ok Test: macro_arg_spaces -> ok Test: matching_end_labels -> ok Test: memwr_port_connection -> ok -Test: shared_ports -> ok Test: unnamed_block_decl -> ok +Test: trans_addr_enable -> ok Test: aes_kexp128 -> ok -Test: simple_sram_byte_en -> ok Test: always01 -> ok Test: always02 -> ok +Test: trans_sdp -> ok Test: always03 -> ok -Test: trans_addr_enable -> ok Test: arraycells -> ok +Test: trans_sp -> ok Test: arrays01 -> ok -Test: trans_sdp -> ok Test: attrib01_module -> ok +Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. +Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. +Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. +Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. +Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. +Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. Test: attrib02_port_decl -> ok +Warning: Selection "asym_ram_sdp_read_wider" did not match any module. +Test: wide_all -> ok Test: attrib03_parameter -> ok -Test: trans_sp -> ok Test: attrib04_net_var -> ok +Test: wide_read_async -> ok Test: attrib06_operator_suffix -> ok -Test: wide_all -> ok Test: attrib08_mod_inst -> ok +Test: wide_read_mixed -> ok Test: attrib09_case -> ok -Test: wide_read_async -> ok Test: carryadd -> ok Test: case_expr_const -> ok Test: case_expr_non_const -> ok -Test: wide_read_mixed -> ok -Warning: Shift register inference not yet supported for family xc3s. Test: wide_read_sync -> ok Test: wide_read_trans -> ok Test: wide_thru_priority -> ok -Passed xilinx-lutram.ys Test: wide_write -> ok make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/memories' Testing expectations for amber23_sram_byte_en.v .. ok. @@ -60682,34 +60036,44 @@ make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/simple_abc9' Test: case_large -> ok Test: const_branch_finish -> ok +Warning: Resizing cell port TB.uut.address_in_w from 11 bits to 10 bits. +Warning: Resizing cell port TB.uut.data_in from 18 bits to 36 bits. Test: const_fold_func -> ok Test: const_func_shadow -> ok Test: abc9 -> ok -Test: constmuldivmod -> ok Test: aes_kexp128 -> ok Test: always01 -> ok Test: always02 -> ok -Test: constpower -> ok Test: always03 -> ok Test: arraycells -> ok Test: arrays01 -> ok +Test: constmuldivmod -> ok Test: attrib01_module -> ok Test: attrib02_port_decl -> ok -Test: dff_different_styles -> ok +Test: constpower -> ok Test: attrib03_parameter -> ok Test: attrib04_net_var -> ok -Test: dff_init -> ok +Passed xilinx-asym_ram_sdp.ys Test: attrib06_operator_suffix -> ok Test: attrib08_mod_inst -> ok +Test: dff_different_styles -> ok Test: attrib09_case -> ok Test: carryadd -> ok Test: case_expr_const -> ok +Test: dff_init -> ok Test: case_expr_non_const -> ok +Warning: Resizing cell port TB.uut.address_in_w from 10 bits to 8 bits. +Warning: Resizing cell port TB.uut.data_in from 8 bits to 32 bits. Test: dynslice -> ok Test: fiedler-cooley -> ok Test: forgen01 -> ok +Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. +Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. +Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. +Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. +Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. +Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. Test: forgen02 -> ok -Passed xilinx-macc.ys Test: forloops -> ok Test: fsm -> ok Test: func_block -> ok @@ -60719,38 +60083,53 @@ Test: genblk_dive -> ok Test: genblk_order -> ok Test: genblk_port_shadow -> ok +Warning: Resizing cell port TB.uut.data_out from 18 bits to 36 bits. +Warning: Resizing cell port TB.uut.address_in_r from 11 bits to 10 bits. +Passed qlf_k6n10f-t_mem0.ys +Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. +Warning: Complex async reset for dff `\Q'. Test: generate -> ok Test: graphtest -> ok Test: hierarchy -> ok -/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. -/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Test: hierdefparam -> ok Test: i2c_master_tests -> ok Test: ifdef_1 -> ok Test: ifdef_2 -> ok -Passed xilinx-mul.ys -Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 Test: localparam_attr -> ok Test: loop_prefix_case -> ok +Warning: Resizing cell port TB.uut.data_out from 8 bits to 32 bits. +Warning: Resizing cell port TB.uut.address_in_r from 10 bits to 8 bits. Test: loop_var_shadow -> ok +Warning: Wire TB.\rq_b [7] is used but has no driver. +Warning: Wire TB.\rq_b [6] is used but has no driver. +Warning: Wire TB.\rq_b [5] is used but has no driver. +Warning: Wire TB.\rq_b [4] is used but has no driver. +Warning: Wire TB.\rq_b [3] is used but has no driver. +Warning: Wire TB.\rq_b [2] is used but has no driver. +Warning: Wire TB.\rq_b [1] is used but has no driver. +Warning: Wire TB.\rq_b [0] is used but has no driver. Test: loops -> ok Test: macro_arg_surrounding_spaces -> ok Test: macros -> ok -Test: mem2reg -> ok -Test: mem2reg_bounds_tern -> ok Test: case_large -> ok Test: const_branch_finish -> ok Test: const_fold_func -> ok -Test: mem_arst -> ok Test: const_func_shadow -> ok +Test: mem2reg -> ok +Test: mem2reg_bounds_tern -> ok +Test: mem_arst -> ok Test: constmuldivmod -> ok Test: constpower -> ok Test: dff_different_styles -> ok -/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. -/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Test: dff_init -> ok -Passed xilinx-mul_unsigned.ys Test: memory -> ok +Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. +Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. +Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. +Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. +Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. +Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. +Passed xilinx-attributes_test.ys Test: module_scope -> ok Test: module_scope_case -> ok Test: module_scope_func -> ok @@ -60759,22 +60138,29 @@ Test: named_genblk -> ok Test: nested_genblk_resolve -> ok Test: omsp_dbg_uart -> ok +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. Test: dynslice -> ok Test: fiedler-cooley -> ok Test: forgen01 -> ok Test: forgen02 -> ok -Test: operators -> ok Test: forloops -> ok -Test: param_attr -> ok Test: fsm -> ok Test: func_block -> ok Test: func_recurse -> ok -Test: paramods -> ok Test: func_width_scope -> ok Test: genblk_collide -> ok Test: genblk_dive -> ok +Test: operators -> ok Test: genblk_order -> ok +Test: param_attr -> ok Test: genblk_port_shadow -> ok +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. +Test: paramods -> ok Test: generate -> ok Test: graphtest -> ok Test: hierarchy -> ok @@ -60789,16 +60175,17 @@ Test: macro_arg_surrounding_spaces -> ok Test: macros -> ok Test: mem2reg -> ok -Passed xilinx-mux.ys Test: mem2reg_bounds_tern -> ok -Warning: Shift register inference not yet supported for family xc3se. Test: mem_arst -> ok Test: partsel -> ok Test: process -> ok Test: realexpr -> ok +Passed qlf_k6n10f-t_mem1.ys +Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: repwhile -> ok -Test: retime -> ok Test: memory -> ok +Warning: Complex async reset for dff `\Q'. +Test: retime -> ok Test: module_scope -> ok Test: module_scope_case -> ok Test: module_scope_func -> ok @@ -60807,18 +60194,23 @@ Test: named_genblk -> ok Test: nested_genblk_resolve -> ok Test: omsp_dbg_uart -> ok +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. +Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. Test: rotate -> ok Test: scopes -> ok -Passed xilinx-mux_lut4.ys Test: sign_part_assign -> ok Test: signed_full_slice -> ok Test: signedexpr -> ok -Test: sincos -> ok Test: operators -> ok -Test: specify -> ok Test: param_attr -> ok -Test: string_format -> ok Test: paramods -> ok +Test: sincos -> ok +Test: specify -> ok +Test: string_format -> ok Test: subbytes -> ok Test: task_func -> ok Test: undef_eqx_nex -> ok @@ -60826,9 +60218,7 @@ Test: values -> ok Test: verilog_primitives -> ok Test: vloghammer -> ok -Passed xilinx-nosrl.ys Test: wandwor -> ok -Passed xilinx-opt_lut_ins.ys Test: wreduce -> ok make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/simple' ...passed tests in tests/simple @@ -60840,110 +60230,25 @@ Test: test_simulation_always -> ok Test: test_simulation_and -> ok Test: test_simulation_buffer -> ok -Passed xilinx-pmgen_xilinx_srl.ys Test: test_simulation_decoder -> ok Test: test_simulation_inc -> ok Test: test_simulation_mux -> ok Test: test_simulation_nand -> ok Test: test_simulation_nor -> ok Test: test_simulation_or -> ok +Passed qlf_k6n10f-t_mem2.ys +Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: test_simulation_seq -> ok -Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. -Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. -Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. -Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. -Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. -Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. -Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. -Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. -Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. -Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. -Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. +Warning: Complex async reset for dff `\Q'. +Passed xilinx-blockram.ys Test: test_simulation_shifter -> ok Test: test_simulation_sop -> ok +Passed xilinx-bug1460.ys Test: test_simulation_techmap -> ok -Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. -Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. Test: test_simulation_techmap_tech -> ok Test: test_simulation_vlib -> ok Test: test_simulation_xnor -> ok +Passed xilinx-bug1462.ys Test: test_simulation_xor -> ok make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/hana' ...passed tests in tests/hana @@ -60951,220 +60256,265 @@ make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/asicworld' Test: code_hdl_models_GrayCounter -> ok Test: code_hdl_models_arbiter -> ok +Passed xilinx-bug1480.ys Test: code_hdl_models_cam -> ok Test: code_hdl_models_clk_div -> ok Test: code_hdl_models_clk_div_45 -> ok -Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. +Passed xilinx-bug1598.ys Test: code_hdl_models_d_ff_gates -> ok Test: code_hdl_models_d_latch_gates -> ok Test: code_hdl_models_decoder_2to4_gates -> ok +Warning: Wire top.\t is used but has no driver. +Warning: Wire top.\in is used but has no driver. Test: code_hdl_models_decoder_using_assign -> ok Test: code_hdl_models_decoder_using_case -> ok Test: code_hdl_models_dff_async_reset -> ok Test: code_hdl_models_dff_sync_reset -> ok +Test: partsel -> ok Test: code_hdl_models_encoder_4to2_gates -> ok +Test: process -> ok Test: code_hdl_models_encoder_using_case -> ok +Test: realexpr -> ok Test: code_hdl_models_encoder_using_if -> ok Test: code_hdl_models_full_adder_gates -> ok +Test: repwhile -> ok +Test: retime -> ok Test: code_hdl_models_full_subtracter_gates -> ok +Passed xilinx-bug1605.ys Test: code_hdl_models_gray_counter -> ok -Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. -Passed xilinx-priority_memory.ys +Passed xilinx-bug3670.ys Test: code_hdl_models_half_adder_gates -> ok Test: code_hdl_models_lfsr -> ok Test: code_hdl_models_lfsr_updown -> ok Test: code_hdl_models_mux_2to1_gates -> ok -Test: partsel -> ok Test: code_hdl_models_mux_using_assign -> ok -Test: process -> ok +Test: rotate -> ok Test: code_hdl_models_mux_using_case -> ok +Test: scopes -> ok Test: code_hdl_models_mux_using_if -> ok -Test: realexpr -> ok Test: code_hdl_models_one_hot_cnt -> ok -Test: repwhile -> ok +Test: sign_part_assign -> ok +Test: signed_full_slice -> ok Test: code_hdl_models_parallel_crc -> ok -Test: retime -> ok +Test: signedexpr -> ok Test: code_hdl_models_parity_using_assign -> ok Test: code_hdl_models_parity_using_bitwise -> ok Test: code_hdl_models_parity_using_function -> ok Test: code_hdl_models_pri_encoder_using_assign -> ok +Passed xilinx-counter.ys Test: code_hdl_models_rom_using_case -> ok -Passed xilinx-shifter.ys Test: code_hdl_models_serial_crc -> ok Test: code_hdl_models_tff_async_reset -> ok -Test: rotate -> ok Test: code_hdl_models_tff_sync_reset -> ok -Test: scopes -> ok -Test: sign_part_assign -> ok -Test: signed_full_slice -> ok -Test: signedexpr -> ok +Test: sincos -> ok +Test: string_format -> ok Test: code_hdl_models_uart -> ok +Test: subbytes -> ok Test: code_hdl_models_up_counter -> ok Test: code_hdl_models_up_counter_load -> ok +Test: task_func -> ok Test: code_hdl_models_up_down_counter -> ok +Test: undef_eqx_nex -> ok +Test: usb_phy_tests -> ok +Passed qlf_k6n10f-t_mem3.ys +Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: code_specman_switch_fabric -> ok +Test: values -> ok +Warning: Complex async reset for dff `\Q'. +Test: verilog_primitives -> ok Test: code_tidbits_asyn_reset -> ok -Passed xilinx-tribuf.ys Test: code_tidbits_blocking -> ok +Test: vloghammer -> ok Test: code_tidbits_fsm_using_always -> ok -Test: sincos -> ok Test: code_tidbits_fsm_using_function -> ok -Test: string_format -> ok -Test: subbytes -> ok +Test: wandwor -> ok Test: code_tidbits_fsm_using_single_always -> ok Test: code_tidbits_nonblocking -> ok Test: code_tidbits_reg_combo_example -> ok Test: code_tidbits_reg_seq_example -> ok -Test: task_func -> ok Test: code_tidbits_syn_reset -> ok -Test: undef_eqx_nex -> ok -Test: usb_phy_tests -> ok Test: code_tidbits_wire_example -> ok Test: code_verilog_tutorial_addbit -> ok -Passed xilinx-xilinx_dffopt.ys -Passed xilinx-xilinx_dsp.ys +Test: wreduce -> ok Test: code_verilog_tutorial_always_example -> ok -Test: values -> ok -Passed xilinx-xilinx_srl.ys -Test: verilog_primitives -> ok +Test: arrays02 -> ok Test: code_verilog_tutorial_bus_con -> ok Test: code_verilog_tutorial_comment -> ok Test: code_verilog_tutorial_counter -> ok -Test: vloghammer -> ok +Test: arrays03 -> ok Test: code_verilog_tutorial_d_ff -> ok Test: code_verilog_tutorial_decoder -> ok -Test: wandwor -> ok Test: code_verilog_tutorial_decoder_always -> ok Test: code_verilog_tutorial_escape_id -> ok Test: code_verilog_tutorial_explicit -> ok Test: code_verilog_tutorial_first_counter -> ok +Test: asgn_binop -> ok +Test: case_expr_extend -> ok Test: code_verilog_tutorial_flip_flop -> ok +Test: case_expr_query -> ok Test: code_verilog_tutorial_fsm_full -> ok +Test: defvalue -> ok Test: code_verilog_tutorial_good_code -> ok +Test: implicit_ports -> ok Test: code_verilog_tutorial_if_else -> ok -Test: wreduce -> ok +Test: lesser_size_cast -> ok Test: code_verilog_tutorial_multiply -> ok -Test: arrays02 -> ok +Test: local_loop_var -> ok Test: code_verilog_tutorial_mux_21 -> ok Test: code_verilog_tutorial_n_out_primitive -> ok Test: code_verilog_tutorial_parallel_if -> ok -Test: arrays03 -> ok Test: code_verilog_tutorial_parity -> ok Test: code_verilog_tutorial_simple_function -> ok +Test: macro_arg_spaces -> ok Test: code_verilog_tutorial_simple_if -> ok +Test: matching_end_labels -> ok Test: code_verilog_tutorial_task_global -> ok +Test: memwr_port_connection -> ok +Test: unnamed_block_decl -> ok +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/simple_abc9' +...passed tests in tests/simple_abc9 +Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Test: code_verilog_tutorial_tri_buf -> ok Test: code_verilog_tutorial_v2k_reg -> ok +Warning: Complex async reset for dff `\Q'. Test: code_verilog_tutorial_which_clock -> ok make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/asicworld' ...passed tests in tests/asicworld cd tests/share && bash run-test.sh "" generating tests.. running tests.. -[0][1][2][3][4][5][6][7][8]Test: asgn_binop -> ok -[9][10][11][12][13][14][15]Test: case_expr_extend -> ok -[16][17][18][19][20][21][22][23]Test: case_expr_query -> ok -[24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42]Test: defvalue -> ok -[43][44][45][46][47][48][49][50][51][52][53][54][55]Test: implicit_ports -> ok -[56][57][58][59][60][61][62][63][64]Test: lesser_size_cast -> ok -[65][66][67][68]Test: local_loop_var -> ok -[69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] +[0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] ...passed tests in tests/share -Test: matching_end_labels -> ok cd tests/opt_share && bash run-test.sh "" generating tests.. running tests.. make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/opt_share' -[0][1][2][3][4][5]Test: macro_arg_spaces -> ok -[6]Passed xilinx-macc.sh -[7]Test: memwr_port_connection -> ok -Test: unnamed_block_decl -> ok -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/simple_abc9' -...passed tests in tests/simple_abc9 +[0][1][2][3][4][5][6][7][8]Passed xilinx-dffs.ys +[9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76]Passed xilinx-dsp_abc9.ys +Passed qlf_k6n10f-t_mem4.ys +Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. +Warning: Complex async reset for dff `\Q'. +[77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92]/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. +/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. +Passed qlf_k6n10f-t_mem5.ys +Passed xilinx-dsp_fastfir.ys +[93][94][95][96][97][98][99]make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/opt_share' + +...passed tests in tests/opt_share cd tests/fsm && bash run-test.sh "" generating tests.. -[8]PRNG seed: 1892216158 -[9]running tests.. +PRNG seed: 1753117470 +running tests.. make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/fsm' -[0][10][11][12][13][14][15]K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +[0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Passed xilinx-dsp_simd.ys +K[1]K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[2]K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Warning: Shift register inference not yet supported for family xc3se. +K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +K[4]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -[16][17][18][19][20][21][22][23][24][25][26][27][28][29]K[4]K[5]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[5]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[6]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[7]Passed xilinx-fsm.ys +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +K[8]K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[8]Passed xilinx-tribuf.sh -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/arch/xilinx' -...passed tests in tests/arch/xilinx +K[10]Passed qlf_k6n10f-t_mem6.ys +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/arch/quicklogic/qlf_k6n10f' +...passed tests in tests/arch/quicklogic/qlf_k6n10f cd tests/memlib && bash run-test.sh "" make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/memlib' -K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Test: t_async_big -> ok +K[11]K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_async_big_block -> ok +Test: t_async_small -> ok +K[13]Test: t_async_small_block -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[10]Test: t_async_big -> ok -K[11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Test: t_sync_big -> ok +Test: t_sync_big_sdp -> ok +K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Passed xilinx-latches.ys +K[15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[13]Test: t_async_big_block -> ok -Test: t_async_small -> ok -Test: t_async_small_block -> ok -Test: t_sync_big -> ok -[30][31][32]Test: t_sync_big_sdp -> ok Test: t_sync_big_lut -> ok -[33][34][35][36][37][38]Test: t_sync_small -> ok -[39][40][41][42][43][44]Test: t_sync_small_block -> ok +Test: t_sync_small -> ok +Test: t_sync_small_block -> ok Test: t_sync_small_block_attr -> ok Test: t_init_lut_zeros_zero -> ok Test: t_init_lut_zeros_any -> ok Test: t_init_lut_val_zero -> ok Test: t_init_lut_val_any -> ok Test: t_init_lut_val_no_undef -> ok -[45][46][47]Test: t_init_lut_val2_any -> ok +Test: t_init_lut_val2_any -> ok Test: t_init_lut_val2_no_undef -> ok -T[14]Test: t_init_lut_x_none -> ok +K[16]Test: t_init_lut_x_none -> ok +K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_init_lut_x_zero -> ok -Test: t_init_lut_x_any -> ok -K[15]Test: t_init_lut_x_no_undef -> ok +K[18]Test: t_init_lut_x_any -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_init_lut_x_no_undef -> ok Test: t_ram_18b2B -> ok Test: t_ram_9b1B -> ok Test: t_ram_4b1B -> ok Test: t_ram_2b1B -> ok +Passed xilinx-logic.ys Test: t_ram_1b1B -> ok Test: t_init_9b1B_zeros_zero -> ok Test: t_init_9b1B_zeros_any -> ok Test: t_init_9b1B_val_zero -> ok Test: t_init_9b1B_val_any -> ok -[48]Test: t_init_9b1B_val_no_undef -> ok -[49][50][51][52][53][54]Test: t_init_13b2B_val_any -> ok -[55][56][57][58][59][60][61]Test: t_init_18b2B_val_any -> ok -[62][63][64][65][66][67][68]Test: t_init_18b2B_val_no_undef -> ok -[69][70][71][72][73][74][75]Test: t_init_4b1B_x_none -> ok -[76][77]Test: t_init_4b1B_x_zero -> ok +K[19]Passed xilinx-dsp_cascade.ys +Test: t_init_9b1B_val_no_undef -> ok +Test: t_init_13b2B_val_any -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_init_18b2B_val_any -> ok +Test: t_init_18b2B_val_no_undef -> ok +Test: t_init_4b1B_x_none -> ok +Test: t_init_4b1B_x_zero -> ok Test: t_init_4b1B_x_any -> ok Test: t_init_4b1B_x_no_undef -> ok Test: t_clock_a4_wANYrANYsFalse -> ok -K[16]Test: t_clock_a4_wANYrNEGsFalse -> ok +Test: t_clock_a4_wANYrNEGsFalse -> ok Test: t_clock_a4_wANYrPOSsFalse -> ok Test: t_clock_a4_wNEGrANYsFalse -> ok Test: t_clock_a4_wNEGrPOSsFalse -> ok Test: t_clock_a4_wNEGrNEGsFalse -> ok Test: t_clock_a4_wPOSrANYsFalse -> ok -K[17]Test: t_clock_a4_wPOSrNEGsFalse -> ok +Test: t_clock_a4_wPOSrNEGsFalse -> ok Test: t_clock_a4_wPOSrPOSsFalse -> ok +K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_clock_a4_wANYrANYsTrue -> ok -K[18]Test: t_clock_a4_wNEGrPOSsTrue -> ok -[78][79]Test: t_clock_a4_wNEGrNEGsTrue -> ok +Test: t_clock_a4_wNEGrPOSsTrue -> ok +Test: t_clock_a4_wNEGrNEGsTrue -> ok Test: t_clock_a4_wPOSrNEGsTrue -> ok Test: t_clock_a4_wPOSrPOSsTrue -> ok Test: t_unmixed -> ok @@ -61172,727 +60522,617 @@ Test: t_mixed_18_9 -> ok Test: t_mixed_36_9 -> ok Test: t_mixed_4_2 -> ok -K[19]Test: t_tdp -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_tdp -> ok Test: t_sync_2clk -> ok Test: t_sync_shared -> ok -K[20]Test: t_sync_2clk_shared -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_sync_2clk_shared -> ok Test: t_sync_trans_old_old -> ok Test: t_sync_trans_old_new -> ok Test: t_sync_trans_old_none -> ok Test: t_sync_trans_new_old -> ok -[80]Test: t_sync_trans_new_new -> ok -[81][82][83][84][85]K[21][86]Test: t_sync_trans_new_none -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_sync_trans_new_new -> ok +Test: t_sync_trans_new_none -> ok Test: t_sp_nc_none -> ok -K[22]Test: t_sp_new_none -> ok +Test: t_sp_new_none -> ok Test: t_sp_old_none -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_nc_nc -> ok Test: t_sp_new_nc -> ok Test: t_sp_old_nc -> ok Test: t_sp_nc_new -> ok -[87]Test: t_sp_new_new -> ok -[88][89][90][91][92][93]Test: t_sp_old_new -> ok -[94][95][96][97][98][99]Test: t_sp_nc_old -> ok -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/opt_share' - -...passed tests in tests/opt_share +Test: t_sp_new_new -> ok +Test: t_sp_old_new -> ok +Test: t_sp_nc_old -> ok Test: t_sp_new_old -> ok -cd tests/bram && bash run-test.sh "" -generating tests.. Test: t_sp_old_old -> ok -PRNG seed: 866838 Test: t_sp_nc_new_only -> ok -running tests.. -make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/bram' Test: t_sp_new_new_only -> ok Test: t_sp_old_new_only -> ok -K[23]Test: t_sp_nc_new_only_be -> ok -Passed memory_bram test 00_01. +Test: t_sp_nc_new_only_be -> ok Test: t_sp_new_new_only_be -> ok -K[24]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Passed xilinx-macc.ys Test: t_sp_old_new_only_be -> ok Test: t_sp_nc_new_be -> ok Test: t_sp_new_new_be -> ok Test: t_sp_old_new_be -> ok +T[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_nc_old_be -> ok Test: t_sp_new_old_be -> ok -K[25]Test: t_sp_old_old_be -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Test: t_sp_old_old_be -> ok +Test: t_sp_nc_nc_be -> ok +K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -Test: t_sp_nc_nc_be -> ok Test: t_sp_new_nc_be -> ok Test: t_sp_old_nc_be -> ok -Passed memory_bram test 00_02. -Test: t_sp_nc_auto -> ok +K[23]Test: t_sp_nc_auto -> ok Test: t_sp_new_auto -> ok Test: t_sp_old_auto -> ok Test: t_sp_nc_auto_be -> ok Test: t_sp_new_auto_be -> ok -Passed memory_bram test 00_03. Test: t_sp_old_auto_be -> ok -Test: t_sp_init_x_x -> ok +K[24]Test: t_sp_init_x_x -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_init_x_x_re -> ok Test: t_sp_init_x_x_ce -> ok Test: t_sp_init_0_x -> ok -Passed memory_bram test 00_04. Test: t_sp_init_0_x_re -> ok Test: t_sp_init_0_0 -> ok Test: t_sp_init_0_0_re -> ok Test: t_sp_init_0_any -> ok -Passed memory_bram test 01_00. Test: t_sp_init_0_any_re -> ok Test: t_sp_init_v_x -> ok Test: t_sp_init_v_x_re -> ok -K[26]Test: t_sp_init_v_0 -> ok -Passed memory_bram test 01_02. +K[25]Test: t_sp_init_v_0 -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_init_v_0_re -> ok Test: t_sp_init_v_any -> ok Test: t_sp_init_v_any_re -> ok -Passed memory_bram test 01_03. Test: t_sp_arst_x_x -> ok -Test: t_sp_arst_x_x_re -> ok +K[26]Test: t_sp_arst_x_x_re -> ok Test: t_sp_arst_0_x -> ok -Passed memory_bram test 01_04. -Test: t_sp_arst_0_x_re -> ok +K[27]Test: t_sp_arst_0_x_re -> ok Test: t_sp_arst_0_0 -> ok Test: t_sp_arst_0_0_re -> ok Test: t_sp_arst_0_any -> ok -Passed memory_bram test 02_00. Test: t_sp_arst_0_any_re -> ok Test: t_sp_arst_0_init -> ok +/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. +/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Test: t_sp_arst_0_init_re -> ok Test: t_sp_arst_v_x -> ok -K[27]Passed memory_bram test 02_01. Test: t_sp_arst_v_x_re -> ok Test: t_sp_arst_v_0 -> ok Test: t_sp_arst_v_0_re -> ok -KTest: t_sp_arst_v_any -> ok -[28]Passed memory_bram test 02_03. -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_sp_arst_v_any -> ok +Passed xilinx-mul.ys +Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 Test: t_sp_arst_v_any_re -> ok Test: t_sp_arst_v_init -> ok Test: t_sp_arst_v_init_re -> ok -K[29]Test: t_sp_arst_e_x -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -Passed memory_bram test 02_04. +Test: t_sp_arst_e_x -> ok Test: t_sp_arst_e_x_re -> ok Test: t_sp_arst_e_0 -> ok -Test: t_sp_arst_e_0_re -> ok +K[28]Test: t_sp_arst_e_0_re -> ok Test: t_sp_arst_e_any -> ok -Passed memory_bram test 03_00. Test: t_sp_arst_e_any_re -> ok Test: t_sp_arst_e_init -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_arst_e_init_re -> ok -Passed memory_bram test 03_01. Test: t_sp_arst_n_x -> ok -K[30]Test: t_sp_arst_n_x_re -> ok +Test: t_sp_arst_n_x_re -> ok Test: t_sp_arst_n_0 -> ok Test: t_sp_arst_n_0_re -> ok Test: t_sp_arst_n_any -> ok Test: t_sp_arst_n_any_re -> ok Test: t_sp_arst_n_init -> ok -K[31]Test: t_sp_arst_n_init_re -> ok -Passed memory_bram test 03_02. +Test: t_sp_arst_n_init_re -> ok Test: t_sp_srst_x_x -> ok Test: t_sp_srst_x_x_re -> ok Test: t_sp_srst_0_x -> ok -Passed memory_bram test 03_04. Test: t_sp_srst_0_x_re -> ok Test: t_sp_srst_0_0 -> ok Test: t_sp_srst_0_0_re -> ok -Test: t_sp_srst_0_any -> ok +K[29]Test: t_sp_srst_0_any -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_srst_0_any_re -> ok -Test: t_sp_srst_0_init -> ok +K[30]Test: t_sp_srst_0_init -> ok Test: t_sp_srst_0_init_re -> ok Test: t_sp_srst_v_x -> ok -K[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -Passed memory_bram test 04_00. Test: t_sp_srst_v_x_re -> ok -K[33]Test: t_sp_srst_v_0 -> ok +K[31]Test: t_sp_srst_v_0 -> ok Test: t_sp_srst_v_0_re -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_srst_v_any -> ok Test: t_sp_srst_v_any_re -> ok -Passed memory_bram test 04_01. Test: t_sp_srst_v_any_re_gated -> ok Test: t_sp_srst_v_any_ce -> ok -Test: t_sp_srst_v_any_ce_gated -> ok +K[32]Test: t_sp_srst_v_any_ce_gated -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_srst_v_init -> ok Test: t_sp_srst_v_init_re -> ok Test: t_sp_srst_e_x -> ok Test: t_sp_srst_e_x_re -> ok -Passed memory_bram test 04_02. Test: t_sp_srst_e_0 -> ok Test: t_sp_srst_e_0_re -> ok Test: t_sp_srst_e_any -> ok Test: t_sp_srst_e_any_re -> ok +/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. +/build/reproducible-path/yosys-0.52/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Test: t_sp_srst_e_init -> ok Test: t_sp_srst_e_init_re -> ok -K[34]Test: t_sp_srst_n_x -> ok +K[33]Test: t_sp_srst_n_x -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_srst_n_x_re -> ok -Passed memory_bram test 04_03. -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/bram' -...passed tests in tests/bram Test: t_sp_srst_n_0 -> ok -cd tests/svinterfaces && bash run-test.sh "" -Test: svinterface1 -> Test: t_sp_srst_n_0_re -> ok +K[34]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_sp_srst_n_0_re -> ok Test: t_sp_srst_n_any -> ok K[35]Test: t_sp_srst_n_any_re -> ok -svinterface1_tb.v:50: $finish called at 420000 (10ps) -svinterface1_tb.v:50: $finish called at 420000 (10ps) -ok -Test: svinterface_at_top -> Test: t_sp_srst_n_init -> ok +Test: t_sp_srst_n_init -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_sp_srst_n_init_re -> ok Test: t_sp_srst_gv_x -> ok Test: t_sp_srst_gv_x_re -> ok -svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) -svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) -ERROR! -Test: load_and_derive ->ok -Test: resolve_types ->ok -...passed tests in tests/svinterfaces Test: t_sp_srst_gv_0 -> ok -cd tests/xprop && bash run-test.sh "" -xprop PRNG seed: 2861791647 Test: t_sp_srst_gv_0_re -> ok -make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/xprop' Test: t_sp_srst_gv_any -> ok Test: t_sp_srst_gv_any_re -> ok +Passed xilinx-mul_unsigned.ys Test: t_sp_srst_gv_any_re_gated -> ok -xprop_not_3s_5: ok -xprop_not_3s_5: ok Test: t_sp_srst_gv_any_ce -> ok Test: t_sp_srst_gv_any_ce_gated -> ok -xprop_pos_3s_5: ok -xprop_pos_3s_5: ok -K[36]Test: t_sp_srst_gv_init -> ok +Test: t_sp_srst_gv_init -> ok Test: t_sp_srst_gv_init_re -> ok -Test: t_wren_a4d4_NO_BYTE -> ok +K[36]Test: t_wren_a4d4_NO_BYTE -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_wren_a5d4_NO_BYTE -> ok -xprop_neg_3s_5: ok -xprop_neg_3s_5: ok Test: t_wren_a6d4_NO_BYTE -> ok Test: t_wren_a3d8_NO_BYTE -> ok -K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_wren_a4d8_NO_BYTE -> ok -xprop_and_1u1_1: ok -xprop_and_1u1_1: ok -Test: t_wren_a4d4_W4_B4 -> ok +K[37]Test: t_wren_a4d4_W4_B4 -> ok Test: t_wren_a4d8_W4_B4_separate -> ok -K[38]xprop_and_1s1_2: ok -xprop_and_1s1_2: ok Test: t_wren_a4d8_W8_B4 -> ok +Test: t_wren_a4d8_W8_B4_separate -> ok Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -Test: t_wren_a4d8_W8_B4_separate -> ok Test: t_wren_a4d8_W8_B8 -> ok Test: t_wren_a4d8_W8_B8_separate -> ok -xprop_and_2u2_2: ok -xprop_and_2u2_2: ok Test: t_wren_a4d2w8_W16_B4 -> ok -K[39]Test: t_wren_a4d2w8_W16_B4_separate -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -xprop_or_1u1_1: ok -xprop_or_1u1_1: ok +Test: t_wren_a4d2w8_W16_B4_separate -> ok +Warning: Shift register inference not yet supported for family xc3s. Test: t_wren_a4d4w4_W16_B4 -> ok Test: t_wren_a4d4w4_W16_B4_separate -> ok Test: t_wren_a5d4w2_W16_B4 -> ok -xprop_or_1s1_2: ok -xprop_or_1s1_2: ok Test: t_wren_a5d4w2_W16_B4_separate -> ok Test: t_wren_a5d4w4_W16_B4 -> ok -xprop_or_2u2_2: ok -xprop_or_2u2_2: ok Test: t_wren_a5d4w4_W16_B4_separate -> ok Test: t_wren_a4d8w2_W16_B4 -> ok Test: t_wren_a4d8w2_W16_B4_separate -> ok -xprop_xor_1u1_1: ok -xprop_xor_1u1_1: ok Test: t_wren_a5d8w1_W16_B4 -> ok Test: t_wren_a5d8w1_W16_B4_separate -> ok -K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -Test: t_wren_a5d8w2_W16_B4 -> ok -xprop_xor_1s1_2: ok -xprop_xor_1s1_2: ok +K[38]Test: t_wren_a5d8w2_W16_B4 -> ok Test: t_wren_a5d8w2_W16_B4_separate -> ok -K[41]Test: t_wren_a4d16w1_W16_B4 -> ok -xprop_xor_2u2_2: ok -xprop_xor_2u2_2: ok +Test: t_wren_a4d16w1_W16_B4 -> ok Test: t_wren_a4d16w1_W16_B4_separate -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Passed xilinx-lutram.ys +Warning: Shift register inference not yet supported for family xc3se. Test: t_wren_a4d4w2_W8_B8 -> ok -K[42]Test: t_wren_a4d4w2_W8_B8_separate -> ok -xprop_xnor_1u1_1: ok -xprop_xnor_1u1_1: ok +Test: t_wren_a4d4w2_W8_B8_separate -> ok Test: t_wren_a4d4w1_W8_B8 -> ok Test: t_wren_a4d4w1_W8_B8_separate -> ok Test: t_wren_a4d8w2_W8_B8 -> ok -xprop_xnor_1s1_2: ok -xprop_xnor_1s1_2: ok Test: t_wren_a4d8w2_W8_B8_separate -> ok Test: t_wren_a3d8w2_W8_B8 -> ok Test: t_wren_a3d8w2_W8_B8_separate -> ok -xprop_xnor_2u2_2: ok -xprop_xnor_2u2_2: ok Test: t_wren_a4d4w2_W8_B4 -> ok -K[43]Test: t_wren_a4d4w2_W8_B4_separate -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_wren_a4d4w2_W8_B4_separate -> ok Test: t_wren_a4d2w4_W8_B4 -> ok -xprop_add_5u3_3: ok -xprop_add_5u3_3: ok -Test: t_wren_a4d2w4_W8_B4_separate -> ok +K[39]Test: t_wren_a4d2w4_W8_B4_separate -> ok Test: t_wren_a4d4w4_W8_B4 -> ok Test: t_wren_a4d4w4_W8_B4_separate -> ok -xprop_add_5s3_3: ok -xprop_add_5s3_3: ok Test: t_wren_a4d4w4_W4_B4 -> ok Test: t_wren_a4d4w4_W4_B4_separate -> ok Test: t_wren_a4d4w5_W4_B4 -> ok -xprop_sub_5u3_3: ok -xprop_sub_5u3_3: ok Test: t_wren_a4d4w5_W4_B4_separate -> ok Test: t_geom_a4d64_wren -> ok Test: t_geom_a5d32_wren -> ok -K[44]Test: t_geom_a5d64_wren -> ok -xprop_sub_5s3_3: ok -xprop_sub_5s3_3: ok +Test: t_geom_a5d64_wren -> ok Test: t_geom_a6d16_wren -> ok -Test: t_geom_a6d30_wren -> ok +K[40]Test: t_geom_a6d30_wren -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_geom_a6d64_wren -> ok -xprop_mul_5u3_3: ok -xprop_mul_5u3_3: ok Test: t_geom_a7d4_wren -> ok -K[45]Test: t_geom_a7d6_wren -> ok +Test: t_geom_a7d6_wren -> ok Test: t_geom_a7d8_wren -> ok Test: t_geom_a7d17_wren -> ok -xprop_mul_5s3_3: ok -xprop_mul_5s3_3: ok Test: t_geom_a8d4_wren -> ok +K[41]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_geom_a8d6_wren -> ok Test: t_geom_a9d4_wren -> ok -xprop_div_5u3_3: ok -xprop_div_5u3_3: ok Test: t_geom_a9d8_wren -> ok -Test: t_geom_a9d5_wren -> ok +K[42]Test: t_geom_a9d5_wren -> ok Test: t_geom_a9d6_wren -> ok Test: t_geom_a3d18_9b1B -> ok -xprop_div_5s3_3: ok -xprop_div_5s3_3: ok Test: t_geom_a4d4_9b1B -> ok -K[46]Test: t_geom_a4d18_9b1B -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Test: t_geom_a4d18_9b1B -> ok Test: t_geom_a5d32_9b1B -> ok Test: t_geom_a6d4_9b1B -> ok -xprop_mod_5u3_3: ok -xprop_mod_5u3_3: ok Test: t_geom_a7d11_9b1B -> ok Test: t_geom_a7d18_9b1B -> ok Test: t_geom_a11d1_9b1B -> ok -xprop_mod_5s3_3: ok -xprop_mod_5s3_3: ok +K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_wide_sdp_a6r1w1b1x1 -> ok -Test: t_wide_sdp_a7r1w1b1x1 -> ok +K[44]Test: t_wide_sdp_a7r1w1b1x1 -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_wide_sdp_a8r1w1b1x1 -> ok Test: t_wide_sdp_a6r0w0b0x0 -> ok -xprop_divfloor_5u3_3: ok -xprop_divfloor_5u3_3: ok Test: t_wide_sdp_a6r1w0b0x0 -> ok Test: t_wide_sdp_a6r2w0b0x0 -> ok Test: t_wide_sdp_a6r3w0b0x0 -> ok -xprop_divfloor_5s3_3: ok -xprop_divfloor_5s3_3: ok Test: t_wide_sdp_a6r4w0b0x0 -> ok Test: t_wide_sdp_a6r5w0b0x0 -> ok -K[47]Test: t_wide_sdp_a6r0w1b0x0 -> ok -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Passed xilinx-mux_lut4.ys +Test: t_wide_sdp_a6r0w1b0x0 -> ok +Passed xilinx-mux.ys Test: t_wide_sdp_a6r0w1b1x0 -> ok -xprop_modfloor_5u3_3: ok -xprop_modfloor_5u3_3: ok +Passed xilinx-opt_lut_ins.ys Test: t_wide_sdp_a6r0w2b0x0 -> ok -K[48]Test: t_wide_sdp_a6r0w2b2x0 -> ok +Test: t_wide_sdp_a6r0w2b2x0 -> ok Test: t_wide_sdp_a6r0w3b2x0 -> ok -xprop_modfloor_5s3_3: ok -xprop_modfloor_5s3_3: ok Test: t_wide_sdp_a6r0w4b2x0 -> ok Test: t_wide_sdp_a6r0w5b2x0 -> ok -xprop_lt_5u3_2: ok -xprop_lt_5u3_2: ok Test: t_wide_sdp_a7r0w0b0x0 -> ok Test: t_wide_sdp_a7r1w0b0x0 -> ok Test: t_wide_sdp_a7r2w0b0x0 -> ok -xprop_lt_5s3_2: ok -xprop_lt_5s3_2: ok Test: t_wide_sdp_a7r3w0b0x0 -> ok Test: t_wide_sdp_a7r4w0b0x0 -> ok Test: t_wide_sdp_a7r5w0b0x0 -> ok -xprop_le_5u3_2: ok -xprop_le_5u3_2: ok Test: t_wide_sdp_a7r0w1b0x0 -> ok -K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: - Users of state reg look like FSM recoding might result in larger circuit. - Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_wide_sdp_a7r0w1b1x0 -> ok Test: t_wide_sdp_a7r0w2b0x0 -> ok -xprop_le_5s3_2: ok -xprop_le_5s3_2: ok Test: t_wide_sdp_a7r0w2b2x0 -> ok Test: t_wide_sdp_a7r0w3b2x0 -> ok -K -make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/fsm' -...passed tests in tests/fsm -xprop_eq_5u3_2: ok -xprop_eq_5u3_2: ok Test: t_wide_sdp_a7r0w4b2x0 -> ok Test: t_wide_sdp_a7r0w5b2x0 -> ok Test: t_wide_sp_mix_a6r1w1b1 -> ok -Test: t_wide_sp_mix_a7r1w1b1 -> ok -xprop_eq_5s3_2: ok -xprop_eq_5s3_2: ok -xprop_ne_5u3_2: ok -xprop_ne_5u3_2: ok +T[45]Test: t_wide_sp_mix_a7r1w1b1 -> ok +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_wide_sp_mix_a8r1w1b1 -> ok Test: t_wide_sp_mix_a6r0w0b0 -> ok +K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Test: t_wide_sp_mix_a6r1w0b0 -> ok -xprop_eqx_5u3_2: ok -xprop_eqx_5u3_2: ok -xprop_ne_5s3_2: ok -xprop_ne_5s3_2: ok Test: t_wide_sp_mix_a6r2w0b0 -> ok Test: t_wide_sp_mix_a6r3w0b0 -> ok Test: t_wide_sp_mix_a6r4w0b0 -> ok -xprop_eqx_5s3_2: ok -xprop_eqx_5s3_2: ok Test: t_wide_sp_mix_a6r5w0b0 -> ok -xprop_nex_5u3_2: ok -xprop_nex_5u3_2: ok Test: t_wide_sp_mix_a6r0w1b0 -> ok Test: t_wide_sp_mix_a6r0w1b1 -> ok -xprop_nex_5s3_2: ok -xprop_nex_5s3_2: ok Test: t_wide_sp_mix_a6r0w2b0 -> ok -xprop_ge_5u3_2: ok -xprop_ge_5u3_2: ok -Test: t_wide_sp_mix_a6r0w2b2 -> ok +K[47]Test: t_wide_sp_mix_a6r0w2b2 -> ok Test: t_wide_sp_mix_a6r0w3b2 -> ok Test: t_wide_sp_mix_a6r0w4b2 -> ok -xprop_ge_5s3_2: ok -xprop_ge_5s3_2: ok +Passed xilinx-nosrl.ys Test: t_wide_sp_mix_a6r0w5b2 -> ok -xprop_gt_5u3_2: ok -xprop_gt_5u3_2: ok Test: t_wide_sp_mix_a7r0w0b0 -> ok -xprop_gt_5s3_2: ok -xprop_gt_5s3_2: ok -Test: t_wide_sp_mix_a7r1w0b0 -> ok -xprop_reduce_and_3u_3: ok -xprop_reduce_and_3u_3: ok +K[48]Test: t_wide_sp_mix_a7r1w0b0 -> ok Test: t_wide_sp_mix_a7r2w0b0 -> ok Test: t_wide_sp_mix_a7r3w0b0 -> ok -xprop_reduce_and_3s_3: ok -xprop_reduce_and_3s_3: ok Test: t_wide_sp_mix_a7r4w0b0 -> ok -xprop_reduce_or_3u_3: ok -xprop_reduce_or_3u_3: ok Test: t_wide_sp_mix_a7r5w0b0 -> ok Test: t_wide_sp_mix_a7r0w1b0 -> ok -xprop_reduce_or_3s_3: ok -xprop_reduce_or_3s_3: ok -xprop_reduce_xor_3u_3: ok -xprop_reduce_xor_3u_3: ok -Test: t_wide_sp_mix_a7r0w1b1 -> ok +Passed xilinx-pmgen_xilinx_srl.ys +K[49]Test: t_wide_sp_mix_a7r0w1b1 -> ok Test: t_wide_sp_mix_a7r0w2b0 -> ok -xprop_reduce_xor_3s_3: ok -xprop_reduce_xor_3s_3: ok Test: t_wide_sp_mix_a7r0w2b2 -> ok -xprop_reduce_xnor_3u_3: ok -xprop_reduce_xnor_3u_3: ok Test: t_wide_sp_mix_a7r0w3b2 -> ok -xprop_reduce_xnor_3s_3: ok Test: t_wide_sp_mix_a7r0w4b2 -> ok -xprop_reduce_xnor_3s_3: ok -xprop_reduce_bool_1u_1: ok -xprop_reduce_bool_1u_1: ok +K +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/fsm' +...passed tests in tests/fsm +cd tests/bram && bash run-test.sh "" +generating tests.. +PRNG seed: 862516 +running tests.. +make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/bram' Test: t_wide_sp_mix_a7r0w5b2 -> ok Test: t_wide_sp_tied_a6r1w1b1 -> ok -xprop_reduce_bool_3u_3: ok -xprop_reduce_bool_3u_3: ok -xprop_reduce_bool_3s_3: ok -xprop_reduce_bool_3s_3: ok Test: t_wide_sp_tied_a7r1w1b1 -> ok Test: t_wide_sp_tied_a8r1w1b1 -> ok Test: t_wide_sp_tied_a6r0w0b0 -> ok +Passed memory_bram test 00_01. Test: t_wide_sp_tied_a6r1w0b0 -> ok -xprop_reduce_bool_3s_1: ok -xprop_reduce_bool_3s_1: ok -xprop_logic_not_1u_1: ok -xprop_logic_not_1u_1: ok Test: t_wide_sp_tied_a6r2w0b0 -> ok Test: t_wide_sp_tied_a6r3w0b0 -> ok -xprop_logic_not_3u_3: ok -xprop_logic_not_3u_3: ok -xprop_logic_not_3s_3: ok -xprop_logic_not_3s_3: ok +Passed memory_bram test 00_02. +Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. +Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. Test: t_wide_sp_tied_a6r4w0b0 -> ok +Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. +Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. +Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. +Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. +Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. +Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. +Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. +Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. +Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. Test: t_wide_sp_tied_a6r5w0b0 -> ok -xprop_logic_not_3s_1: ok -xprop_logic_not_3s_1: ok -xprop_logic_and_1u1_1: ok -xprop_logic_and_1u1_1: ok Test: t_wide_sp_tied_a6r0w1b0 -> ok +Passed memory_bram test 00_03. Test: t_wide_sp_tied_a6r0w1b1 -> ok +Passed xilinx-shifter.ys Test: t_wide_sp_tied_a6r0w2b0 -> ok -xprop_logic_and_3u3_3: ok -xprop_logic_and_3u3_3: ok -xprop_logic_and_3s3_3: ok -xprop_logic_and_3s3_3: ok Test: t_wide_sp_tied_a6r0w2b2 -> ok Test: t_wide_sp_tied_a6r0w3b2 -> ok Test: t_wide_sp_tied_a6r0w4b2 -> ok -xprop_logic_and_3s3_1: ok -xprop_logic_and_3s3_1: ok -xprop_logic_or_1u1_1: ok -xprop_logic_or_1u1_1: ok Test: t_wide_sp_tied_a6r0w5b2 -> ok Test: t_wide_sp_tied_a7r0w0b0 -> ok Test: t_wide_sp_tied_a7r1w0b0 -> ok Test: t_wide_sp_tied_a7r2w0b0 -> ok -xprop_logic_or_3u3_3: ok -xprop_logic_or_3u3_3: ok -xprop_logic_or_3s3_3: ok -xprop_logic_or_3s3_3: ok +Passed memory_bram test 00_04. Test: t_wide_sp_tied_a7r3w0b0 -> ok Test: t_wide_sp_tied_a7r4w0b0 -> ok -xprop_logic_or_3s3_1: ok -xprop_logic_or_3s3_1: ok +Passed memory_bram test 01_00. Test: t_wide_sp_tied_a7r5w0b0 -> ok -xprop_shl_4u3u_3: ok -xprop_shl_4u3u_3: ok Test: t_wide_sp_tied_a7r0w1b0 -> ok +Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. +Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. Test: t_wide_sp_tied_a7r0w1b1 -> ok -xprop_shl_4s3u_3: ok -xprop_shl_4s3u_3: ok Test: t_wide_sp_tied_a7r0w2b0 -> ok -xprop_shr_4u3u_3: ok -xprop_shr_4u3u_3: ok +Passed memory_bram test 01_02. Test: t_wide_sp_tied_a7r0w2b2 -> ok Test: t_wide_sp_tied_a7r0w3b2 -> ok -xprop_shr_4s3u_3: ok -xprop_shr_4s3u_3: ok Test: t_wide_sp_tied_a7r0w4b2 -> ok -xprop_sshl_4u3u_3: ok -xprop_sshl_4u3u_3: ok +Passed xilinx-tribuf.ys Test: t_wide_sp_tied_a7r0w5b2 -> ok Test: t_wide_read_a6r1w1b1 -> ok -xprop_sshl_4s3u_3: ok -xprop_sshl_4s3u_3: ok +Passed memory_bram test 01_03. Test: t_wide_write_a6r1w1b1 -> ok -xprop_sshr_4u3u_3: ok -xprop_sshr_4u3u_3: ok Test: t_wide_read_a7r1w1b1 -> ok Test: t_wide_write_a7r1w1b1 -> ok -xprop_sshr_4s3u_3: ok -xprop_sshr_4s3u_3: ok +Passed memory_bram test 01_04. Test: t_wide_read_a8r1w1b1 -> ok Test: t_wide_write_a8r1w1b1 -> ok -xprop_shift_4u3u_3: ok -xprop_shift_4u3u_3: ok Test: t_wide_read_a6r0w0b0 -> ok +Passed memory_bram test 02_00. Test: t_wide_write_a6r0w0b0 -> ok -xprop_shift_4s3u_3: ok -xprop_shift_4s3u_3: ok Test: t_wide_read_a6r1w0b0 -> ok Test: t_wide_write_a6r1w0b0 -> ok -xprop_shift_4u2s_8: ok -xprop_shift_4u2s_8: ok Test: t_wide_read_a6r2w0b0 -> ok +Passed memory_bram test 02_01. Test: t_wide_write_a6r2w0b0 -> ok +Passed xilinx-xilinx_dffopt.ys Test: t_wide_read_a6r3w0b0 -> ok -xprop_shift_4s2s_8: ok -xprop_shift_4s2s_8: ok +Passed xilinx-xilinx_dsp.ys +Passed xilinx-xilinx_srl.ys Test: t_wide_write_a6r3w0b0 -> ok +Passed memory_bram test 02_03. Test: t_wide_read_a6r4w0b0 -> ok -xprop_shift_4u3s_3: ok -xprop_shift_4u3s_3: ok Test: t_wide_write_a6r4w0b0 -> ok -xprop_shift_4s3s_3: ok -xprop_shift_4s3s_3: ok Test: t_wide_read_a6r5w0b0 -> ok -xprop_shiftx_4u2s_8: ok -xprop_shiftx_4u2s_8: ok +Passed memory_bram test 02_04. Test: t_wide_write_a6r5w0b0 -> ok Test: t_wide_read_a6r0w1b0 -> ok -xprop_shiftx_4u3s_3: ok -xprop_shiftx_4u3s_3: ok -Test: t_wide_read_a6r0w1b1 -> ok +Passed memory_bram test 03_00. Test: t_wide_write_a6r0w1b0 -> ok -xprop_mux_1: ok -xprop_mux_1: ok +Test: t_wide_read_a6r0w1b1 -> ok Test: t_wide_write_a6r0w1b1 -> ok Test: t_wide_read_a6r0w2b0 -> ok Test: t_wide_write_a6r0w2b0 -> ok -xprop_mux_3: ok -xprop_mux_3: ok -xprop_bmux_1_2: ok -xprop_bmux_1_2: ok Test: t_wide_read_a6r0w2b2 -> ok Test: t_wide_write_a6r0w2b2 -> ok Test: t_wide_read_a6r0w3b2 -> ok Test: t_wide_write_a6r0w3b2 -> ok -xprop_bmux_3_1: ok -xprop_bmux_3_1: ok -xprop_bmux_2_2: ok -xprop_bmux_2_2: ok +Passed memory_bram test 03_01. Test: t_wide_read_a6r0w4b2 -> ok Test: t_wide_write_a6r0w4b2 -> ok Test: t_wide_read_a6r0w5b2 -> ok -xprop_demux_1_2: ok -xprop_demux_1_2: ok +Passed memory_bram test 03_02. Test: t_wide_write_a6r0w5b2 -> ok Test: t_wide_read_a7r0w0b0 -> ok -xprop_demux_2_2: ok -xprop_demux_2_2: ok Test: t_wide_write_a7r0w0b0 -> ok +Passed memory_bram test 03_04. Test: t_wide_read_a7r1w0b0 -> ok -xprop_demux_3_1: ok -xprop_demux_3_1: ok Test: t_wide_write_a7r1w0b0 -> ok Test: t_wide_read_a7r2w0b0 -> ok +Passed memory_bram test 04_00. Test: t_wide_write_a7r2w0b0 -> ok -xprop_pmux_1_4: ok -xprop_pmux_1_4: ok Test: t_wide_read_a7r3w0b0 -> ok Test: t_wide_write_a7r3w0b0 -> ok Test: t_wide_read_a7r4w0b0 -> ok -xprop_pmux_2_2: ok -xprop_pmux_2_2: ok -xprop_pmux_3_1: ok -xprop_pmux_3_1: ok Test: t_wide_write_a7r4w0b0 -> ok Test: t_wide_read_a7r5w0b0 -> ok -xprop_bwmux_1: ok -xprop_bwmux_1: ok +Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. Test: t_wide_write_a7r5w0b0 -> ok Test: t_wide_read_a7r0w1b0 -> ok -xprop_pmux_4_4: ok -xprop_pmux_4_4: ok Test: t_wide_write_a7r0w1b0 -> ok -xprop_bwmux_3: ok -xprop_bwmux_3: ok Test: t_wide_read_a7r0w1b1 -> ok -xprop_bweqx_1: ok -xprop_bweqx_1: ok +Passed memory_bram test 04_01. Test: t_wide_write_a7r0w1b1 -> ok -xprop_bweqx_3: ok -xprop_bweqx_3: ok Test: t_wide_read_a7r0w2b0 -> ok +Passed xilinx-macc.sh Test: t_wide_write_a7r0w2b0 -> ok -xprop_ff_1: ok -xprop_ff_1: ok Test: t_wide_read_a7r0w2b2 -> ok Test: t_wide_write_a7r0w2b2 -> ok -xprop_ff_3: ok -xprop_ff_3: ok -Test: t_wide_write_a7r0w3b2 -> ok Test: t_wide_read_a7r0w3b2 -> ok -Test: t_wide_write_a7r0w4b2 -> ok +Test: t_wide_write_a7r0w3b2 -> ok Test: t_wide_read_a7r0w4b2 -> ok -Test: t_wide_write_a7r0w5b2 -> ok -xprop_dff_1pd: ok -xprop_dff_1pd: ok +Test: t_wide_write_a7r0w4b2 -> ok Test: t_wide_read_a7r0w5b2 -> ok +Test: t_wide_write_a7r0w5b2 -> ok Test: t_quad_port_a2d2 -> ok +Passed memory_bram test 04_02. +Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. +Passed xilinx-priority_memory.ys Test: t_quad_port_a4d2 -> ok -Test: t_quad_port_a5d2 -> ok -xprop_dff_1nd: ok -xprop_dff_1nd: ok Test: t_quad_port_a4d4 -> ok -xprop_dff_3pd: ok -xprop_dff_3pd: ok -Test: t_quad_port_a6d2 -> ok +Test: t_quad_port_a5d2 -> ok Test: t_quad_port_a4d8 -> ok -Test: t_wide_quad_a4w2r1 -> ok +Test: t_quad_port_a6d2 -> ok +Passed memory_bram test 04_03. +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/bram' +...passed tests in tests/bram +cd tests/svinterfaces && bash run-test.sh "" +Test: svinterface1 -> Test: t_wide_quad_a4w2r1 -> ok Test: t_wide_oct_a4w2r1 -> ok -xprop_dffe_1pnd: ok -xprop_dffe_1pnd: ok -xprop_dff_3nd: ok -xprop_dff_3nd: ok Test: t_wide_quad_a4w2r2 -> ok Test: t_wide_oct_a4w2r2 -> ok Test: t_wide_quad_a4w2r3 -> ok Test: t_wide_oct_a4w2r3 -> ok -xprop_dffe_1nnd: ok -Test: t_wide_quad_a4w2r4 -> ok -xprop_dffe_1nnd: ok +svinterface1_tb.v:50: $finish called at 420000 (10ps) +svinterface1_tb.v:50: $finish called at 420000 (10ps) +ok +Test: svinterface_at_top -> Test: t_wide_quad_a4w2r4 -> ok Test: t_wide_oct_a4w2r4 -> ok -xprop_dffe_3pnd: ok -xprop_dffe_3pnd: ok Test: t_wide_quad_a4w2r5 -> ok Test: t_wide_oct_a4w2r5 -> ok Test: t_wide_quad_a4w2r6 -> ok Test: t_wide_oct_a4w2r6 -> ok -xprop_dffe_3nnd: ok -xprop_dffe_3nnd: ok -xprop_dffe_1ppd: ok -xprop_dffe_1ppd: ok Test: t_wide_quad_a4w2r7 -> ok +svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) Test: t_wide_oct_a4w2r7 -> ok -Test: t_wide_quad_a4w2r8 -> ok +svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) +ERROR! +Test: load_and_derive ->ok +Test: resolve_types ->ok +...passed tests in tests/svinterfaces +cd tests/xprop && bash run-test.sh "" +xprop PRNG seed: 2809417284 +make[3]: Entering directory '/build/reproducible-path/yosys-0.52/tests/xprop' Test: t_wide_oct_a4w2r8 -> ok -xprop_dffe_1npd: ok -xprop_dffe_1npd: ok +Test: t_wide_quad_a4w2r8 -> ok Test: t_wide_quad_a4w2r9 -> ok Test: t_wide_oct_a4w2r9 -> ok -xprop_dffe_3ppd: ok -xprop_dffe_3ppd: ok Test: t_wide_quad_a4w4r1 -> ok Test: t_wide_oct_a4w4r1 -> ok +xprop_not_3s_5: ok +xprop_not_3s_5: ok Test: t_wide_quad_a4w4r4 -> ok Test: t_wide_oct_a4w4r4 -> ok Test: t_wide_quad_a4w4r6 -> ok Test: t_wide_oct_a4w4r6 -> ok +xprop_pos_3s_5: ok +xprop_pos_3s_5: ok Test: t_wide_quad_a4w4r9 -> ok Test: t_wide_oct_a4w4r9 -> ok +Test: t_wide_quad_a5w2r1 -> ok cd tests/select && bash run-test.sh "" Running blackboxes.ys.. Running list_mod.ys.. Running mod-attribute.ys.. +Test: t_wide_oct_a5w2r1 -> ok Running no_warn_assert.ys.. Running no_warn_prefixed_arg_memb.ys.. Running no_warn_prefixed_empty_select_arg.ys.. @@ -61920,7 +61160,6 @@ Running proc_dff.ys.. Warning: Complex async reset for dff `\q'. Running proc_rom.ys.. -Test: t_wide_quad_a5w2r1 -> ok Warning: wire '\d' is assigned in a block at < ok Warning: wire '\d' is assigned in a block at < ok Test ../../techlibs/anlogic/cells_sim.v -> ok -Test ../../techlibs/coolrunner2/cells_sim.v ->Running rmdead.ys.. - ok -Test ../../techlibs/ecp5/cells_sim.v ->...passed tests in tests/proc -cd tests/rpc && bash run-test.sh "" -Running exec.ys.. +Test ../../techlibs/coolrunner2/cells_sim.v -> ok +Test ../../techlibs/ecp5/cells_sim.v -> ok +Test ../../techlibs/efinix/cells_sim.v ->xprop_neg_3s_5: ok +xprop_neg_3s_5: ok ok -Test ../../techlibs/efinix/cells_sim.v -> ok Test ../../techlibs/gatemate/cells_sim.v -> ok -Test ../../techlibs/gowin/cells_sim.v ->Test: t_wide_oct_a5w2r1 -> ok +Test ../../techlibs/gowin/cells_sim.v -> ok +Test ../../techlibs/greenpak4/cells_sim.v ->Test: t_wide_oct_a5w2r4 -> ok ok -Test ../../techlibs/greenpak4/cells_sim.v -> ok Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. @@ -62019,13 +61254,8 @@ ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. -...passed tests in tests/rpc -cd tests/memfile && bash run-test.sh "" -Running from the parent directory with content1.dat -Running from the parent directory with temp/content2.dat ok -Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->Running from the parent directory with memfile/temp/content2.dat -../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. +Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. @@ -62035,31 +61265,51 @@ ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. -Running from the same directory with content1.dat -Running from the same directory with temp/content2.dat ok -Test ../../techlibs/intel/cycloneive/cells_sim.v ->Running from a child directory with content1.dat - ok -Test ../../techlibs/intel/max10/cells_sim.v ->Running from a child directory with temp/content2.dat - ok -Test ../../techlibs/intel/cycloneiv/cells_sim.v ->Running from a child directory with content2.dat - ok -Test ../../techlibs/intel/cyclone10lp/cells_sim.v ->Checking a failure when zero length filename is provided +Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok +Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok +Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok +Test ../../techlibs/intel/max10/cells_sim.v -> ok +Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok +Test ../../techlibs/microchip/cells_sim.v -> ok +Test ../../techlibs/nanoxplore/cells_sim.v -> ok +Test ../../techlibs/nexus/cells_sim.v -> ok +Test ../../techlibs/quicklogic/pp3/cells_sim.v -> ok +Test ../../techlibs/quicklogic/common/cells_sim.v -> ok +Test ../../techlibs/quicklogic/qlf_k6n10f/cells_sim.v -> ok +Test ../../techlibs/sf2/cells_sim.v -> ok +Test ../../techlibs/xilinx/cells_sim.v ->Test: t_wide_quad_a5w2r9 -> ok ok +Test ../../techlibs/common/simcells.v -> ok +Test ../../techlibs/common/simlib.v -> ok +...passed tests in tests/arch +cd tests/rpc && bash run-test.sh "" +Running exec.ys.. +...passed tests in tests/rpc +cd tests/memfile && bash run-test.sh "" +Running from the parent directory with content1.dat +Running from the parent directory with temp/content2.dat +Running from the parent directory with memfile/temp/content2.dat +xprop_and_1u1_1: ok +xprop_and_1u1_1: ok +Running from the same directory with content1.dat +Running from the same directory with temp/content2.dat +Running from a child directory with content1.dat +Running from a child directory with temp/content2.dat +Running from a child directory with content2.dat +Checking a failure when zero length filename is provided memory.v:15: ERROR: Can not open file `` for \$readmemb. Execution failed, which is OK. Checking a failure when not existing filename is provided -Test ../../techlibs/intel_alm/cyclonev/cells_sim.v ->memory.v:15: ERROR: Can not open file `content3.dat` for \$readmemb. +memory.v:15: ERROR: Can not open file `content3.dat` for \$readmemb. Execution failed, which is OK. - ok ...passed tests in tests/memfile cd tests/fmt && bash run-test.sh "" -+ ../../yosys -p 'read_verilog initial_display.v' + awk '/<<>>/,/<<>>/ {print $0}' -Test ../../techlibs/microchip/cells_sim.v -> ok -Test ../../techlibs/nanoxplore/cells_sim.v ->+ iverilog -o iverilog-initial_display initial_display.v - ok -Test ../../techlibs/nexus/cells_sim.v ->+ ./iverilog-initial_display ++ ../../yosys -p 'read_verilog initial_display.v' +Test: t_wide_oct_a5w2r9 -> ok ++ iverilog -o iverilog-initial_display initial_display.v ++ ./iverilog-initial_display + diff yosys-initial_display.log iverilog-initial_display.log + test_always_display clk -DEVENT_CLK + local subtest=clk @@ -62128,9 +61378,9 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 0de35d2746, CPU: user 0.02s system 0.01s, MEM: 8.48 MB peak +End of script. Logfile hash: 0de35d2746, CPU: user 0.02s system 0.01s, MEM: 8.47 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 42% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... +Time spent: 41% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v /----------------------------------------------------------------------------\ @@ -62196,16 +61446,15 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: e35e8bb689, CPU: user 0.02s system 0.01s, MEM: 8.49 MB peak +End of script. Logfile hash: e35e8bb689, CPU: user 0.03s system 0.00s, MEM: 8.48 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 41% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... - ok +Time spent: 40% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v + test_always_display clk_rst -DEVENT_CLK_RST + local subtest=clk_rst + shift + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v -Test ../../techlibs/quicklogic/common/cells_sim.v -> + /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | @@ -62253,8 +61502,7 @@ Cleaned up 0 empty switches. 2.12. Executing OPT_EXPR pass (perform const folding). - ok -Test ../../techlibs/quicklogic/qlf_k6n10f/cells_sim.v ->Optimizing module m. +Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. @@ -62269,12 +61517,11 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: c95608ddf0, CPU: user 0.02s system 0.00s, MEM: 8.42 MB peak +End of script. Logfile hash: c95608ddf0, CPU: user 0.02s system 0.00s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 41% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... +Time spent: 42% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v - ok -Test ../../techlibs/quicklogic/pp3/cells_sim.v -> + /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | @@ -62327,7 +61574,6 @@ 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. - ok Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- @@ -62337,11 +61583,11 @@ 4.1. Executing BMUXMAP pass. 4.2. Executing DEMUXMAP pass. -Test ../../techlibs/sf2/cells_sim.v ->Dumping module `\m'. +Dumping module `\m'. End of script. Logfile hash: faf50513c3, CPU: user 0.02s system 0.01s, MEM: 8.43 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 40% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... +Time spent: 40% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v + test_always_display star -DEVENT_STAR + local subtest=star @@ -62387,7 +61633,6 @@ 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2.9. Executing PROC_DFF pass (convert process syncs to FFs). - ok 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). @@ -62399,7 +61644,7 @@ Optimizing module m. 3. Executing OPT_EXPR pass (perform const folding). -Test ../../techlibs/xilinx/cells_sim.v ->Optimizing module m. +Optimizing module m. Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- @@ -62411,11 +61656,10 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 7b2c5274a5, CPU: user 0.02s system 0.00s, MEM: 8.41 MB peak +End of script. Logfile hash: 7b2c5274a5, CPU: user 0.03s system 0.00s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 42% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v -Test: t_wide_quad_a5w2r4 -> ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -62480,9 +61724,9 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 8979c5de0b, CPU: user 0.03s system 0.00s, MEM: 8.43 MB peak +End of script. Logfile hash: 8979c5de0b, CPU: user 0.02s system 0.00s, MEM: 8.42 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 41% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... +Time spent: 42% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... + diff yosys-always_display-star-1.v yosys-always_display-star-2.v + test_always_display clk_en -DEVENT_CLK -DCOND_EN + local subtest=clk_en @@ -62615,8 +61859,7 @@ 3. Executing OPT_EXPR pass (perform const folding). Optimizing module m. - ok -Test ../../techlibs/common/simcells.v ->Removed 0 unused cells and 3 unused wires. +Removed 0 unused cells and 3 unused wires. -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- @@ -62627,9 +61870,9 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 51e7fa3902, CPU: user 0.03s system 0.00s, MEM: 8.78 MB peak +End of script. Logfile hash: 51e7fa3902, CPU: user 0.02s system 0.01s, MEM: 8.78 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 44% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... +Time spent: 45% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN + local subtest=clk_rst_en @@ -62704,7 +61947,7 @@ End of script. Logfile hash: f9b4876f33, CPU: user 0.02s system 0.01s, MEM: 8.77 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 45% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... +Time spent: 45% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v /----------------------------------------------------------------------------\ @@ -62717,8 +61960,7 @@ -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v - ok -Test ../../techlibs/common/simlib.v ->Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. +Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. Generating RTLIL representation for module `\m'. Successfully finished Verilog frontend. @@ -62774,9 +62016,9 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.03s system 0.00s, MEM: 8.78 MB peak +End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.02s, MEM: 8.78 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 45% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... +Time spent: 44% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v + test_always_display star_en -DEVENT_STAR -DCOND_EN + local subtest=star_en @@ -62849,17 +62091,10 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.01s, MEM: 8.77 MB peak +End of script. Logfile hash: d6a7335726, CPU: user 0.02s system 0.01s, MEM: 8.77 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 45% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... - ok + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v -...passed tests in tests/arch -cd tests/cxxrtl && bash run-test.sh "" -+ run_subtest value -+ local subtest=value -+ shift -+ gcc -std=c++11 -O2 -o cxxrtl-test-value -I../../backends/cxxrtl/runtime test_value.cc -lstdc++ /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -62927,9 +62162,9 @@ 4.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 18895a2046, CPU: user 0.02s system 0.00s, MEM: 8.78 MB peak +End of script. Logfile hash: 18895a2046, CPU: user 0.02s system 0.01s, MEM: 8.77 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 45% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... +Time spent: 45% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= + local subtest=dec_unsigned @@ -62995,9 +62230,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: bfb187b86d, CPU: user 0.02s system 0.00s, MEM: 8.42 MB peak +End of script. Logfile hash: bfb187b86d, CPU: user 0.02s system 0.00s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 32% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... +Time spent: 30% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v /----------------------------------------------------------------------------\ @@ -63060,7 +62295,7 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 4be9539e85, CPU: user 0.01s system 0.02s, MEM: 8.43 MB peak +End of script. Logfile hash: 4be9539e85, CPU: user 0.02s system 0.00s, MEM: 8.43 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 30% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v @@ -63071,6 +62306,7 @@ + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v + ./iverilog-roundtrip-dec_unsigned-1 + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log +Test: t_no_reset -> ok + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed + local subtest=dec_signed @@ -63138,7 +62374,7 @@ End of script. Logfile hash: bbdfa5ca92, CPU: user 0.02s system 0.00s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 31% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... +Time spent: 30% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v /----------------------------------------------------------------------------\ @@ -63201,9 +62437,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: b233de92a6, CPU: user 0.02s system 0.00s, MEM: 8.43 MB peak +End of script. Logfile hash: b233de92a6, CPU: user 0.02s system 0.01s, MEM: 8.43 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... +Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-dec_signed @@ -63277,9 +62513,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 2377f2e106, CPU: user 0.02s system 0.00s, MEM: 8.42 MB peak +End of script. Logfile hash: 2377f2e106, CPU: user 0.02s system 0.00s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 30% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... +Time spent: 30% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v /----------------------------------------------------------------------------\ @@ -63342,13 +62578,12 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 06bfea69c8, CPU: user 0.02s system 0.00s, MEM: 8.49 MB peak +End of script. Logfile hash: 06bfea69c8, CPU: user 0.02s system 0.00s, MEM: 8.43 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned -Test: t_wide_oct_a5w2r4 -> ok + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v + ./iverilog-roundtrip-hex_unsigned-1 + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v @@ -63419,9 +62654,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 824c3b1e65, CPU: user 0.02s system 0.00s, MEM: 8.41 MB peak +End of script. Logfile hash: 824c3b1e65, CPU: user 0.02s system 0.01s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 30% 1x clean (0 sec), 24% 1x opt_expr (0 sec), ... +Time spent: 29% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v /----------------------------------------------------------------------------\ @@ -63484,7 +62719,7 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: f18b3fa15b, CPU: user 0.02s system 0.00s, MEM: 8.43 MB peak +End of script. Logfile hash: f18b3fa15b, CPU: user 0.01s system 0.01s, MEM: 8.43 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v @@ -63562,7 +62797,7 @@ End of script. Logfile hash: b768358a65, CPU: user 0.02s system 0.00s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... +Time spent: 29% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v /----------------------------------------------------------------------------\ @@ -63625,9 +62860,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 762621cd95, CPU: user 0.02s system 0.00s, MEM: 8.43 MB peak +End of script. Logfile hash: 762621cd95, CPU: user 0.02s system 0.01s, MEM: 8.34 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 30% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... +Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-oct_unsigned @@ -63690,6 +62925,7 @@ 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module m. +Test: t_gclken -> ok Removed 0 unused cells and 1 unused wires. -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- @@ -63701,9 +62937,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 7ec82b15e3, CPU: user 0.01s system 0.01s, MEM: 8.42 MB peak +End of script. Logfile hash: 7ec82b15e3, CPU: user 0.02s system 0.01s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 30% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... +Time spent: 29% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v /----------------------------------------------------------------------------\ @@ -63768,11 +63004,13 @@ End of script. Logfile hash: a747b9bd4f, CPU: user 0.02s system 0.00s, MEM: 8.43 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 28% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... +Time spent: 29% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-oct_signed + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v +xprop_and_1s1_2: ok +xprop_and_1s1_2: ok + ./iverilog-roundtrip-oct_signed-1 + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v + ./iverilog-roundtrip-oct_signed-1 @@ -63842,9 +63080,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 270b564880, CPU: user 0.02s system 0.00s, MEM: 8.42 MB peak +End of script. Logfile hash: 270b564880, CPU: user 0.02s system 0.00s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 30% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... +Time spent: 30% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v /----------------------------------------------------------------------------\ @@ -63907,9 +63145,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: dc9f56cb10, CPU: user 0.01s system 0.01s, MEM: 8.43 MB peak +End of script. Logfile hash: dc9f56cb10, CPU: user 0.02s system 0.01s, MEM: 8.43 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 29% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... +Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-bin_unsigned @@ -63983,9 +63221,9 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\m'. -End of script. Logfile hash: 7709253822, CPU: user 0.02s system 0.00s, MEM: 8.42 MB peak +End of script. Logfile hash: 7709253822, CPU: user 0.00s system 0.02s, MEM: 8.41 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... +Time spent: 30% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v /----------------------------------------------------------------------------\ @@ -64050,7 +63288,7 @@ End of script. Logfile hash: 7e2d8271c4, CPU: user 0.02s system 0.00s, MEM: 8.43 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 30% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... +Time spent: 28% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-bin_signed @@ -64113,7 +63351,6 @@ 2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module always_full. -Test: t_wide_quad_a5w2r9 -> ok Removed 0 unused cells and 207 unused wires. 3. Executing CXXRTL backend. @@ -64169,36 +63406,54 @@ -End of script. Logfile hash: af8795c7c4, CPU: user 0.07s system 0.00s, MEM: 11.31 MB peak +End of script. Logfile hash: af8795c7c4, CPU: user 0.07s system 0.00s, MEM: 11.30 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 27% 2x read_verilog (0 sec), 23% 2x write_cxxrtl (0 sec), ... +Time spent: 27% 2x read_verilog (0 sec), 22% 2x write_cxxrtl (0 sec), ... + gcc -std=c++11 -o yosys-always_full -I../../backends/cxxrtl/runtime always_full_tb.cc -lstdc++ -Test: t_wide_oct_a5w2r9 -> ok +Test: t_ungated -> ok +Passed xilinx-tribuf.sh +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/arch/xilinx' +...passed tests in tests/arch/xilinx +cd tests/cxxrtl && bash run-test.sh "" ++ run_subtest value ++ local subtest=value ++ shift ++ gcc -std=c++11 -O2 -o cxxrtl-test-value -I../../backends/cxxrtl/runtime test_value.cc -lstdc++ +Test: t_gclken_ce -> ok +xprop_and_2u2_2: ok +xprop_and_2u2_2: ok +Test: t_grden -> ok +Test: t_grden_ce -> ok +xprop_or_1u1_1: ok +xprop_or_1u1_1: ok + ./cxxrtl-test-value + run_subtest value_fuzz + local subtest=value_fuzz + shift + gcc -std=c++11 -O2 -o cxxrtl-test-value_fuzz -I../../backends/cxxrtl/runtime test_value_fuzz.cc -lstdc++ -Test: t_no_reset -> ok -Test: t_gclken -> ok -Test: t_ungated -> ok -Test: t_gclken_ce -> ok -Test: t_grden -> ok -Test: t_grden_ce -> ok Test: t_exclwr -> ok Test: t_excl_rst -> ok Test: t_transwr -> ok +xprop_or_1s1_2: ok +xprop_or_1s1_2: ok Test: t_trans_rst -> ok Test: t_wr_byte -> ok +xprop_or_2u2_2: ok +xprop_or_2u2_2: ok Test: t_trans_byte -> ok -+ ./cxxrtl-test-value_fuzz Test: t_wr_rst_byte -> ok +xprop_xor_1u1_1: ok +xprop_xor_1u1_1: ok Test: t_rst_wr_byte -> ok Test: t_rdenrst_wr_byte -> ok Test: t_rom_case -> ok +xprop_xor_1s1_2: ok +xprop_xor_1s1_2: ok Test: t_rom_case_block -> ok make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/memlib' ...passed tests in tests/memlib ++ ./cxxrtl-test-value_fuzz +xprop_xnor_1u1_1: ok In file included from /usr/include/c++/14/map:62, from ../../backends/cxxrtl/runtime/cxxrtl/cxxrtl.h:37, from yosys-always_full.cc:1, @@ -64207,6 +63462,9 @@ /usr/include/c++/14/bits/stl_tree.h:1100:30: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 1100 | _M_insert_unique_(end(), *__first, __an); | ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~ +xprop_xnor_1u1_1: ok +xprop_xor_2u2_2: ok +xprop_xor_2u2_2: ok /usr/include/c++/14/bits/stl_tree.h: In member function 'std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::iterator std::_Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::_M_insert_unique_(const_iterator, _Arg&&, _NodeGen&) [with _Arg = const std::pair, cxxrtl::metadata>&; _NodeGen = std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::_Alloc_node; _Key = std::__cxx11::basic_string; _Val = std::pair, cxxrtl::metadata>; _KeyOfValue = std::_Select1st, cxxrtl::metadata> >; _Compare = std::less >; _Alloc = std::allocator, cxxrtl::metadata> >]': /usr/include/c++/14/bits/stl_tree.h:2269:7: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2269 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: @@ -64215,15 +63473,18 @@ /usr/include/c++/14/bits/stl_tree.h:2208:5: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2208 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +xprop_xnor_1s1_2: ok +xprop_xnor_1s1_2: ok + ./yosys-always_full + iverilog -o iverilog-always_full always_full.v always_full_tb.v -+ ./iverilog-always_full + grep -v '\$finish called' ++ ./iverilog-always_full + diff iverilog-always_full.log yosys-always_full.log + test_cxxrtl always_comb + local subtest=always_comb + shift + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' +xprop_xnor_2u2_2: ok /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | @@ -64261,6 +63522,7 @@ 2.5. Executing PROC_ARST pass (detect async resets in processes). 2.6. Executing PROC_ROM pass (convert switches to ROMs). +xprop_xnor_2u2_2: ok Converted 0 switches. @@ -64353,10 +63615,14 @@ -End of script. Logfile hash: a6b3c2e895, CPU: user 0.03s system 0.00s, MEM: 8.78 MB peak +End of script. Logfile hash: a6b3c2e895, CPU: user 0.02s system 0.01s, MEM: 8.78 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 32% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ... + gcc -std=c++11 -o yosys-always_comb -I../../backends/cxxrtl/runtime always_comb_tb.cc -lstdc++ +xprop_add_5u3_3: ok +xprop_add_5u3_3: ok +xprop_add_5s3_3: ok +xprop_add_5s3_3: ok In file included from /usr/include/c++/14/map:62, from ../../backends/cxxrtl/runtime/cxxrtl/cxxrtl.h:37, from yosys-always_comb.cc:1, @@ -64373,10 +63639,14 @@ /usr/include/c++/14/bits/stl_tree.h:2208:5: note: parameter passing for argument of type 'std::_Rb_tree, std::pair, cxxrtl::metadata>, std::_Select1st, cxxrtl::metadata> >, std::less >, std::allocator, cxxrtl::metadata> > >::const_iterator' changed in GCC 7.1 2208 | _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>:: | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +xprop_sub_5u3_3: ok +xprop_sub_5u3_3: ok +xprop_sub_5s3_3: ok +xprop_sub_5s3_3: ok + ./yosys-always_comb + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v -+ ./iverilog-always_comb + grep -v '\$finish called' ++ ./iverilog-always_comb + diff iverilog-always_comb.log yosys-always_comb.log + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v @@ -64529,12 +63799,12 @@ 3.2. Executing DEMUXMAP pass. Dumping module `\always_full'. -End of script. Logfile hash: 52e889d7da, CPU: user 0.15s system 0.00s, MEM: 9.39 MB peak +End of script. Logfile hash: 52e889d7da, CPU: user 0.14s system 0.01s, MEM: 9.38 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) Time spent: 22% 4x opt_clean (0 sec), 18% 1x prep (0 sec), ... + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v -+ ./iverilog-always_full-1 + grep -v '\$finish called' ++ ./iverilog-always_full-1 + diff iverilog-always_full.log iverilog-always_full-1.log + ../../yosys -p 'read_verilog display_lm.v' + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' @@ -64627,8 +63897,12 @@ End of script. Logfile hash: 15a147f3a6, CPU: user 0.02s system 0.00s, MEM: 9.35 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 39% 1x opt_expr (0 sec), 13% 2x write_cxxrtl (0 sec), ... +Time spent: 37% 1x opt_expr (0 sec), 13% 2x write_cxxrtl (0 sec), ... + gcc -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ +xprop_mul_5u3_3: ok +xprop_mul_5u3_3: ok +xprop_mul_5s3_3: ok +xprop_mul_5s3_3: ok In file included from /usr/include/c++/14/map:62, from ../../backends/cxxrtl/runtime/cxxrtl/cxxrtl.h:37, from yosys-display_lm.cc:1, @@ -64659,6 +63933,197 @@ %m: \bot %m: \bot ...passed tests in tests/fmt +xprop_div_5u3_3: ok +xprop_div_5u3_3: ok +xprop_div_5s3_3: ok +xprop_div_5s3_3: ok +xprop_mod_5u3_3: ok +xprop_mod_5u3_3: ok +xprop_mod_5s3_3: ok +xprop_mod_5s3_3: ok +xprop_divfloor_5u3_3: ok +xprop_divfloor_5u3_3: ok +xprop_divfloor_5s3_3: ok +xprop_divfloor_5s3_3: ok +xprop_modfloor_5u3_3: ok +xprop_modfloor_5u3_3: ok +xprop_modfloor_5s3_3: ok +xprop_modfloor_5s3_3: ok +xprop_lt_5u3_2: ok +xprop_lt_5u3_2: ok +xprop_lt_5s3_2: ok +xprop_lt_5s3_2: ok +xprop_le_5u3_2: ok +xprop_le_5u3_2: ok +xprop_le_5s3_2: ok +xprop_le_5s3_2: ok +xprop_eq_5u3_2: ok +xprop_eq_5u3_2: ok +xprop_eq_5s3_2: ok +xprop_eq_5s3_2: ok +xprop_ne_5u3_2: ok +xprop_ne_5u3_2: ok +xprop_ne_5s3_2: ok +xprop_ne_5s3_2: ok +xprop_eqx_5u3_2: ok +xprop_eqx_5u3_2: ok +xprop_eqx_5s3_2: ok +xprop_eqx_5s3_2: ok +xprop_nex_5u3_2: ok +xprop_nex_5u3_2: ok +xprop_nex_5s3_2: ok +xprop_nex_5s3_2: ok +xprop_ge_5u3_2: ok +xprop_ge_5u3_2: ok +xprop_ge_5s3_2: ok +xprop_ge_5s3_2: ok +xprop_gt_5u3_2: ok +xprop_gt_5u3_2: ok +xprop_gt_5s3_2: ok +xprop_gt_5s3_2: ok +xprop_reduce_and_3u_3: ok +xprop_reduce_and_3u_3: ok +xprop_reduce_and_3s_3: ok +xprop_reduce_and_3s_3: ok +xprop_reduce_or_3u_3: ok +xprop_reduce_or_3u_3: ok +xprop_reduce_or_3s_3: ok +xprop_reduce_or_3s_3: ok +xprop_reduce_xor_3u_3: ok +xprop_reduce_xor_3u_3: ok +xprop_reduce_xor_3s_3: ok +xprop_reduce_xor_3s_3: ok +xprop_reduce_xnor_3u_3: ok +xprop_reduce_xnor_3u_3: ok +xprop_reduce_xnor_3s_3: ok +xprop_reduce_xnor_3s_3: ok +xprop_reduce_bool_1u_1: ok +xprop_reduce_bool_1u_1: ok +xprop_reduce_bool_3u_3: ok +xprop_reduce_bool_3u_3: ok +xprop_reduce_bool_3s_3: ok +xprop_reduce_bool_3s_3: ok +xprop_reduce_bool_3s_1: ok +xprop_reduce_bool_3s_1: ok +xprop_logic_not_1u_1: ok +xprop_logic_not_1u_1: ok +xprop_logic_not_3u_3: ok +xprop_logic_not_3u_3: ok +xprop_logic_not_3s_3: ok +xprop_logic_not_3s_3: ok +xprop_logic_not_3s_1: ok +xprop_logic_not_3s_1: ok +xprop_logic_and_1u1_1: ok +xprop_logic_and_1u1_1: ok +xprop_logic_and_3u3_3: ok +xprop_logic_and_3u3_3: ok +xprop_logic_and_3s3_3: ok +xprop_logic_and_3s3_3: ok +xprop_logic_and_3s3_1: ok +xprop_logic_and_3s3_1: ok +xprop_logic_or_1u1_1: ok +xprop_logic_or_1u1_1: ok +xprop_logic_or_3u3_3: ok +xprop_logic_or_3u3_3: ok +xprop_logic_or_3s3_3: ok +xprop_logic_or_3s3_3: ok +xprop_logic_or_3s3_1: ok +xprop_logic_or_3s3_1: ok +xprop_shl_4u3u_3: ok +xprop_shl_4u3u_3: ok +xprop_shl_4s3u_3: ok +xprop_shl_4s3u_3: ok +xprop_shr_4u3u_3: ok +xprop_shr_4u3u_3: ok +xprop_shr_4s3u_3: ok +xprop_shr_4s3u_3: ok +xprop_sshl_4u3u_3: ok +xprop_sshl_4u3u_3: ok +xprop_sshl_4s3u_3: ok +xprop_sshl_4s3u_3: ok +xprop_sshr_4u3u_3: ok +xprop_sshr_4u3u_3: ok +xprop_sshr_4s3u_3: ok +xprop_sshr_4s3u_3: ok +xprop_shift_4u3u_3: ok +xprop_shift_4u3u_3: ok +xprop_shift_4s3u_3: ok +xprop_shift_4s3u_3: ok +xprop_shift_4u2s_8: ok +xprop_shift_4u2s_8: ok +xprop_shift_4s2s_8: ok +xprop_shift_4s2s_8: ok +xprop_shift_4u3s_3: ok +xprop_shift_4u3s_3: ok +xprop_shift_4s3s_3: ok +xprop_shift_4s3s_3: ok +xprop_shiftx_4u2s_8: ok +xprop_shiftx_4u2s_8: ok +xprop_shiftx_4u3s_3: ok +xprop_shiftx_4u3s_3: ok +xprop_mux_1: ok +xprop_mux_1: ok +xprop_mux_3: ok +xprop_mux_3: ok +xprop_bmux_1_2: ok +xprop_bmux_1_2: ok +xprop_bmux_2_2: ok +xprop_bmux_2_2: ok +xprop_bmux_3_1: ok +xprop_bmux_3_1: ok +xprop_demux_1_2: ok +xprop_demux_1_2: ok +xprop_demux_2_2: ok +xprop_demux_2_2: ok +xprop_demux_3_1: ok +xprop_demux_3_1: ok +xprop_pmux_1_4: ok +xprop_pmux_1_4: ok +xprop_pmux_2_2: ok +xprop_pmux_2_2: ok +xprop_pmux_3_1: ok +xprop_pmux_3_1: ok +xprop_bwmux_1: ok +xprop_bwmux_1: ok +xprop_pmux_4_4: ok +xprop_pmux_4_4: ok +xprop_bwmux_3: ok +xprop_bwmux_3: ok +xprop_bweqx_1: ok +xprop_bweqx_1: ok +xprop_bweqx_3: ok +xprop_bweqx_3: ok +xprop_ff_1: ok +xprop_ff_1: ok +xprop_ff_3: ok +xprop_ff_3: ok +xprop_dff_1pd: ok +xprop_dff_1pd: ok +xprop_dff_1nd: ok +xprop_dff_1nd: ok +xprop_dff_3pd: ok +xprop_dff_3pd: ok +xprop_dff_3nd: ok +xprop_dff_3nd: ok +xprop_dffe_1pnd: ok +xprop_dffe_1pnd: ok +xprop_dffe_1nnd: ok +xprop_dffe_1nnd: ok +xprop_dffe_3pnd: ok +xprop_dffe_3pnd: ok +xprop_dffe_3nnd: ok +xprop_dffe_3nnd: ok +xprop_dffe_1ppd: ok +xprop_dffe_1ppd: ok +xprop_dffe_1npd: ok +xprop_dffe_1npd: ok +xprop_dffe_3ppd: ok +xprop_dffe_3ppd: ok +xprop_dffe_3npd: ok +xprop_dffe_3npd: ok +done +make[3]: Leaving directory '/build/reproducible-path/yosys-0.52/tests/xprop' +...passed tests in tests/xprop Randomized tests for value::shl: Test passed @ Bits = 8. Test passed @ Bits = 32. @@ -64824,9 +64289,9 @@ Warnings: 2 unique messages, 2 total -End of script. Logfile hash: 91df85c4b8, CPU: user 0.02s system 0.00s, MEM: 8.44 MB peak +End of script. Logfile hash: 91df85c4b8, CPU: user 0.02s system 0.01s, MEM: 8.48 MB peak Yosys 0.52 (git sha1 fee39a3284c90249e1d9684cf6944ffbbcbb8f90) -Time spent: 35% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... +Time spent: 34% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... + gcc -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc In file included from /usr/include/c++/14/map:62, from ../../backends/cxxrtl/runtime/cxxrtl/cxxrtl.h:37, @@ -64848,7 +64313,7 @@ Passed "make test". make[2]: Leaving directory '/build/reproducible-path/yosys-0.52' - rm -fr -- /tmp/dh-xdg-rundir-JmWRXaxu + rm -fr -- /tmp/dh-xdg-rundir-6Fhgzy05 make[1]: Leaving directory '/build/reproducible-path/yosys-0.52' create-stamp debian/debhelper-build-stamp dh_prep @@ -64856,7 +64321,7 @@ rm -fr -- debian/.debhelper/generated/yosys/ debian/yosys/ debian/tmp/ debian/.debhelper/generated/yosys-dev/ debian/yosys-dev/ debian/.debhelper/generated/yosys-abc/ debian/yosys-abc/ debian/.debhelper/generated/yosys-doc/ debian/yosys-doc/ dh_auto_install install -m0755 -d /build/reproducible-path/yosys-0.52/debian/tmp - make -j3 install DESTDIR=/build/reproducible-path/yosys-0.52/debian/tmp AM_UPDATE_INFO_DIR=no "INSTALL=install --strip-program=true" + make -j4 install DESTDIR=/build/reproducible-path/yosys-0.52/debian/tmp AM_UPDATE_INFO_DIR=no "INSTALL=install --strip-program=true" make[1]: Entering directory '/build/reproducible-path/yosys-0.52' [Makefile.conf] CONFIG := gcc [Makefile.conf] STRIP=: @@ -64904,23 +64369,25 @@ install -m0755 -d debian/yosys-doc/usr/share/doc-base/ install -p -m0644 debian/yosys-doc.doc-base debian/yosys-doc/usr/share/doc-base/yosys-doc.yosys-manual dh_installchangelogs - install -m0755 -d debian/yosys/usr/share/doc/yosys - install -p -m0644 debian/.debhelper/generated/yosys/dh_installchangelogs.dch.trimmed debian/yosys/usr/share/doc/yosys/changelog.Debian - install -p -m0644 ./CHANGELOG debian/yosys/usr/share/doc/yosys/changelog install -m0755 -d debian/yosys-dev/usr/share/doc/yosys-dev install -p -m0644 debian/.debhelper/generated/yosys-dev/dh_installchangelogs.dch.trimmed debian/yosys-dev/usr/share/doc/yosys-dev/changelog.Debian install -p -m0644 ./CHANGELOG debian/yosys-dev/usr/share/doc/yosys-dev/changelog - install -m0755 -d debian/yosys-abc/usr/share/doc/yosys-abc - install -p -m0644 debian/.debhelper/generated/yosys-abc/dh_installchangelogs.dch.trimmed debian/yosys-abc/usr/share/doc/yosys-abc/changelog.Debian - install -p -m0644 ./CHANGELOG debian/yosys-abc/usr/share/doc/yosys-abc/changelog + install -m0755 -d debian/yosys/usr/share/doc/yosys + install -p -m0644 debian/.debhelper/generated/yosys/dh_installchangelogs.dch.trimmed debian/yosys/usr/share/doc/yosys/changelog.Debian + install -p -m0644 ./CHANGELOG debian/yosys/usr/share/doc/yosys/changelog install -m0755 -d debian/yosys-doc/usr/share/doc/yosys-doc install -p -m0644 debian/.debhelper/generated/yosys-doc/dh_installchangelogs.dch.trimmed debian/yosys-doc/usr/share/doc/yosys-doc/changelog.Debian install -p -m0644 ./CHANGELOG debian/yosys-doc/usr/share/doc/yosys-doc/changelog + install -m0755 -d debian/yosys-abc/usr/share/doc/yosys-abc + install -p -m0644 debian/.debhelper/generated/yosys-abc/dh_installchangelogs.dch.trimmed debian/yosys-abc/usr/share/doc/yosys-abc/changelog.Debian + install -p -m0644 ./CHANGELOG debian/yosys-abc/usr/share/doc/yosys-abc/changelog debian/rules execute_before_dh_installman make[1]: Entering directory '/build/reproducible-path/yosys-0.52' cd debian/man ; ./genmanpages.sh make[1]: Leaving directory '/build/reproducible-path/yosys-0.52' dh_installman + install -m0755 -d debian/yosys-dev/usr/share/man/man1/ + install -p -m0644 ./debian/yosys-config.1 debian/yosys-dev/usr/share/man/man1/yosys-config.1 install -m0755 -d debian/yosys-abc/usr/share/man/man1/ install -p -m0644 ./debian/man/yosys-abc.1 debian/yosys-abc/usr/share/man/man1/yosys-abc.1 install -m0755 -d debian/yosys/usr/share/man/man1/ @@ -64931,8 +64398,6 @@ install -p -m0644 ./debian/man/yosys-smtbmc.1 debian/yosys/usr/share/man/man1/yosys-smtbmc.1 install -m0755 -d debian/yosys/usr/share/man/man1/ install -p -m0644 ./debian/man/yosys-witness.1 debian/yosys/usr/share/man/man1/yosys-witness.1 - install -m0755 -d debian/yosys-dev/usr/share/man/man1/ - install -p -m0644 ./debian/yosys-config.1 debian/yosys-dev/usr/share/man/man1/yosys-config.1 man-recode --to-code UTF-8 --suffix .dh-new debian/yosys/usr/share/man/man1/yosys-filterlib.1 debian/yosys/usr/share/man/man1/yosys-smtbmc.1 man-recode --to-code UTF-8 --suffix .dh-new debian/yosys/usr/share/man/man1/yosys-witness.1 debian/yosys/usr/share/man/man1/yosys.1 man-recode --to-code UTF-8 --suffix .dh-new debian/yosys-dev/usr/share/man/man1/yosys-config.1 debian/yosys-abc/usr/share/man/man1/yosys-abc.1 @@ -64956,8 +64421,8 @@ D: dh_python3 dh_python3:205: processing package yosys... D: dh_python3 tools:101: fix_shebang (debian/yosys/usr/bin/yosys): cannot parse binary file I: dh_python3 tools:114: replacing shebang in debian/yosys/usr/bin/yosys-witness -I: dh_python3 tools:114: replacing shebang in debian/yosys/usr/bin/yosys-smtbmc D: dh_python3 tools:101: fix_shebang (debian/yosys/usr/bin/yosys-filterlib): cannot parse binary file +I: dh_python3 tools:114: replacing shebang in debian/yosys/usr/bin/yosys-smtbmc D: dh_python3 fs:338: package yosys details = {'requires.txt': set(), 'egg-info': set(), 'dist-info': set(), 'nsp.txt': set(), 'shebangs': {/usr/bin/python3, /usr/bin/python3}, 'public_vers': set(), 'private_dirs': {'/usr/share/yosys': {'compile': True}}, 'compile': False, 'ext_vers': set(), 'ext_no_version': set()} D: dh_python3 depends:103: generating dependencies for package yosys D: dh_python3 depends:253: D={'python3:any'}; R=[]; S=[]; E=[], B=[]; RT=[('/usr/share/yosys', '')] @@ -64976,45 +64441,45 @@ make[1]: Entering directory '/build/reproducible-path/yosys-0.52' dh_compress --exclude=.pdf cd debian/yosys + cd debian/yosys-dev cd debian/yosys-abc + cd debian/yosys-doc chmod a-x usr/share/doc/yosys-abc/changelog usr/share/doc/yosys-abc/changelog.Debian usr/share/man/man1/yosys-abc.1 chmod a-x usr/share/doc/yosys/README.md usr/share/doc/yosys/changelog usr/share/doc/yosys/changelog.Debian usr/share/man/man1/yosys-filterlib.1 usr/share/man/man1/yosys-smtbmc.1 usr/share/man/man1/yosys-witness.1 usr/share/man/man1/yosys.1 + chmod a-x usr/share/doc/yosys-dev/changelog usr/share/doc/yosys-dev/changelog.Debian usr/share/man/man1/yosys-config.1 + chmod a-x usr/share/doc/yosys-doc/changelog usr/share/doc/yosys-doc/changelog.Debian gzip -9nf usr/share/doc/yosys-abc/changelog usr/share/doc/yosys-abc/changelog.Debian usr/share/man/man1/yosys-abc.1 gzip -9nf usr/share/doc/yosys/README.md usr/share/doc/yosys/changelog usr/share/doc/yosys/changelog.Debian usr/share/man/man1/yosys-filterlib.1 usr/share/man/man1/yosys-smtbmc.1 usr/share/man/man1/yosys-witness.1 usr/share/man/man1/yosys.1 - cd '/build/reproducible-path/yosys-0.52' - cd '/build/reproducible-path/yosys-0.52' - cd debian/yosys-doc - cd debian/yosys-dev - chmod a-x usr/share/doc/yosys-doc/changelog usr/share/doc/yosys-doc/changelog.Debian gzip -9nf usr/share/doc/yosys-doc/changelog usr/share/doc/yosys-doc/changelog.Debian - chmod a-x usr/share/doc/yosys-dev/changelog usr/share/doc/yosys-dev/changelog.Debian usr/share/man/man1/yosys-config.1 gzip -9nf usr/share/doc/yosys-dev/changelog usr/share/doc/yosys-dev/changelog.Debian usr/share/man/man1/yosys-config.1 cd '/build/reproducible-path/yosys-0.52' cd '/build/reproducible-path/yosys-0.52' + cd '/build/reproducible-path/yosys-0.52' + cd '/build/reproducible-path/yosys-0.52' make[1]: Leaving directory '/build/reproducible-path/yosys-0.52' dh_fixperms find debian/yosys ! -type l -a -true -a -true -print0 2>/dev/null | xargs -0r chmod go=rX,u+rw,a-s + find debian/yosys-dev ! -type l -a -true -a -true -print0 2>/dev/null | xargs -0r chmod go=rX,u+rw,a-s find debian/yosys-abc ! -type l -a -true -a -true -print0 2>/dev/null | xargs -0r chmod go=rX,u+rw,a-s + find debian/yosys-doc ! -type l -a -true -a -true -print0 2>/dev/null | xargs -0r chmod go=rX,u+rw,a-s + find debian/yosys-doc/usr/share/doc -type f -a -true -a ! -regex 'debian/yosys-doc/usr/share/doc/[^/]*/examples/.*' -print0 2>/dev/null | xargs -0r chmod 0644 find debian/yosys-abc/usr/share/doc -type f -a -true -a ! -regex 'debian/yosys-abc/usr/share/doc/[^/]*/examples/.*' -print0 2>/dev/null | xargs -0r chmod 0644 + find debian/yosys-dev/usr/share/doc -type f -a -true -a ! -regex 'debian/yosys-dev/usr/share/doc/[^/]*/examples/.*' -print0 2>/dev/null | xargs -0r chmod 0644 find debian/yosys/usr/share/doc -type f -a -true -a ! -regex 'debian/yosys/usr/share/doc/[^/]*/examples/.*' -print0 2>/dev/null | xargs -0r chmod 0644 + find debian/yosys-doc/usr/share/doc -type d -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0755 + find debian/yosys-dev/usr/share/doc -type d -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0755 find debian/yosys-abc/usr/share/doc -type d -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0755 find debian/yosys/usr/share/doc -type d -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0755 + find debian/yosys-doc -type f \( -name '*.so.*' -o -name '*.so' -o -name '*.la' -o -name '*.a' -o -name '*.js' -o -name '*.css' -o -name '*.scss' -o -name '*.sass' -o -name '*.jpeg' -o -name '*.jpg' -o -name '*.png' -o -name '*.gif' -o -name '*.cmxs' -o -name '*.node' \) -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 + find debian/yosys-dev/usr/share/man -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 find debian/yosys-abc/usr/share/man -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 find debian/yosys/usr/share/man -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 + find debian/yosys-dev -type f \( -name '*.so.*' -o -name '*.so' -o -name '*.la' -o -name '*.a' -o -name '*.js' -o -name '*.css' -o -name '*.scss' -o -name '*.sass' -o -name '*.jpeg' -o -name '*.jpg' -o -name '*.png' -o -name '*.gif' -o -name '*.cmxs' -o -name '*.node' \) -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 find debian/yosys-abc -type f \( -name '*.so.*' -o -name '*.so' -o -name '*.la' -o -name '*.a' -o -name '*.js' -o -name '*.css' -o -name '*.scss' -o -name '*.sass' -o -name '*.jpeg' -o -name '*.jpg' -o -name '*.png' -o -name '*.gif' -o -name '*.cmxs' -o -name '*.node' \) -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 - find debian/yosys-abc/usr/bin -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod a+x find debian/yosys -type f \( -name '*.so.*' -o -name '*.so' -o -name '*.la' -o -name '*.a' -o -name '*.js' -o -name '*.css' -o -name '*.scss' -o -name '*.sass' -o -name '*.jpeg' -o -name '*.jpg' -o -name '*.png' -o -name '*.gif' -o -name '*.cmxs' -o -name '*.node' \) -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 - find debian/yosys-doc ! -type l -a -true -a -true -print0 2>/dev/null | xargs -0r chmod go=rX,u+rw,a-s - find debian/yosys/usr/bin -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod a+x - find debian/yosys-doc/usr/share/doc -type f -a -true -a ! -regex 'debian/yosys-doc/usr/share/doc/[^/]*/examples/.*' -print0 2>/dev/null | xargs -0r chmod 0644 - find debian/yosys-dev ! -type l -a -true -a -true -print0 2>/dev/null | xargs -0r chmod go=rX,u+rw,a-s - find debian/yosys-doc/usr/share/doc -type d -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0755 - find debian/yosys-dev/usr/share/doc -type f -a -true -a ! -regex 'debian/yosys-dev/usr/share/doc/[^/]*/examples/.*' -print0 2>/dev/null | xargs -0r chmod 0644 - find debian/yosys-doc -type f \( -name '*.so.*' -o -name '*.so' -o -name '*.la' -o -name '*.a' -o -name '*.js' -o -name '*.css' -o -name '*.scss' -o -name '*.sass' -o -name '*.jpeg' -o -name '*.jpg' -o -name '*.png' -o -name '*.gif' -o -name '*.cmxs' -o -name '*.node' \) -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 - find debian/yosys-dev/usr/share/doc -type d -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0755 - find debian/yosys-dev/usr/share/man -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 - find debian/yosys-dev -type f \( -name '*.so.*' -o -name '*.so' -o -name '*.la' -o -name '*.a' -o -name '*.js' -o -name '*.css' -o -name '*.scss' -o -name '*.sass' -o -name '*.jpeg' -o -name '*.jpg' -o -name '*.png' -o -name '*.gif' -o -name '*.cmxs' -o -name '*.node' \) -a -true -a -true -print0 2>/dev/null | xargs -0r chmod 0644 find debian/yosys-dev/usr/bin -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod a+x + find debian/yosys-abc/usr/bin -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod a+x + find debian/yosys/usr/bin -type f -a -true -a -true -print0 2>/dev/null | xargs -0r chmod a+x dh_missing dh_dwz -a dwz -- debian/yosys-abc/usr/bin/yosys-abc @@ -65057,9 +64522,6 @@ install -m0755 -d debian/yosys/DEBIAN dpkg-shlibdeps -Tdebian/yosys.substvars debian/yosys/usr/bin/yosys debian/yosys/usr/bin/yosys-filterlib dpkg-shlibdeps: warning: diversions involved - output may be incorrect - diversion by libc6 from: /lib/ld-linux-armhf.so.3 -dpkg-shlibdeps: warning: diversions involved - output may be incorrect - diversion by libc6 to: /lib/ld-linux-armhf.so.3.usr-is-merged dpkg-shlibdeps: warning: diversions involved - output may be incorrect diversion by libc6 from: /lib/ld-linux-armhf.so.3 dpkg-shlibdeps: warning: diversions involved - output may be incorrect @@ -65068,6 +64530,9 @@ diversion by libreadline8t64 from: /lib/arm-linux-gnueabihf/libreadline.so.8 dpkg-shlibdeps: warning: diversions involved - output may be incorrect diversion by libreadline8t64 to: /lib/arm-linux-gnueabihf/libreadline.so.8.usr-is-merged + diversion by libc6 from: /lib/ld-linux-armhf.so.3 +dpkg-shlibdeps: warning: diversions involved - output may be incorrect + diversion by libc6 to: /lib/ld-linux-armhf.so.3.usr-is-merged dpkg-shlibdeps: warning: debian/yosys-abc/usr/bin/yosys-abc contains an unresolvable reference to symbol __aeabi_atexit@GLIBC_2.4: it's probably a plugin dpkg-shlibdeps: warning: diversions involved - output may be incorrect diversion by libreadline8t64 from: /lib/arm-linux-gnueabihf/libreadline.so.8 @@ -65086,39 +64551,45 @@ install -m0755 -d debian/yosys-abc/DEBIAN install -m0755 -d debian/yosys-doc/DEBIAN dh_gencontrol - install -m0755 -d debian/yosys/DEBIAN - echo misc:Depends= >> debian/yosys.substvars - echo misc:Pre-Depends= >> debian/yosys.substvars - install -m0755 -d debian/.debhelper/yosys/dbgsym-root/DEBIAN - dpkg-gencontrol -pyosys -ldebian/changelog -Tdebian/yosys.substvars -cdebian/control -Pdebian/.debhelper/yosys/dbgsym-root -UPre-Depends -URecommends -USuggests -UEnhances -UProvides -UEssential -UConflicts -DPriority=optional -UHomepage -UImportant -DAuto-Built-Package=debug-symbols -UProtected -UBuilt-Using -UStatic-Built-Using -DPackage=yosys-dbgsym "-DDepends=yosys (= \${binary:Version})" "-DDescription=debug symbols for yosys" "-DBuild-Ids=390fe52e2c917a37c74fc4851a24cef4547782a2 625c041309bfc31cecaa286e9512fcf3e5f89693" -DSection=debug -UMulti-Arch -UReplaces -UBreaks + install -m0755 -d debian/yosys-dev/DEBIAN + echo misc:Depends= >> debian/yosys-dev.substvars + echo misc:Pre-Depends= >> debian/yosys-dev.substvars + dpkg-gencontrol -pyosys-dev -ldebian/changelog -Tdebian/yosys-dev.substvars -cdebian/control -Pdebian/yosys-dev install -m0755 -d debian/yosys-abc/DEBIAN echo misc:Depends= >> debian/yosys-abc.substvars echo misc:Pre-Depends= >> debian/yosys-abc.substvars install -m0755 -d debian/.debhelper/yosys-abc/dbgsym-root/DEBIAN dpkg-gencontrol -pyosys-abc -ldebian/changelog -Tdebian/yosys-abc.substvars -cdebian/control -Pdebian/.debhelper/yosys-abc/dbgsym-root -UPre-Depends -URecommends -USuggests -UEnhances -UProvides -UEssential -UConflicts -DPriority=optional -UHomepage -UImportant -DAuto-Built-Package=debug-symbols -UProtected -UBuilt-Using -UStatic-Built-Using -DPackage=yosys-abc-dbgsym "-DDepends=yosys-abc (= \${binary:Version})" "-DDescription=debug symbols for yosys-abc" -DBuild-Ids=ee68f6871aea0b0ec50a92d66710ceb195f97aea -DSection=debug -UMulti-Arch -UReplaces -UBreaks - chmod 0644 -- debian/.debhelper/yosys-abc/dbgsym-root/DEBIAN/control - dpkg-gencontrol -pyosys-abc -ldebian/changelog -Tdebian/yosys-abc.substvars -cdebian/control -Pdebian/yosys-abc - chmod 0644 -- debian/.debhelper/yosys/dbgsym-root/DEBIAN/control - dpkg-gencontrol -pyosys -ldebian/changelog -Tdebian/yosys.substvars -cdebian/control -Pdebian/yosys - chmod 0644 -- debian/yosys-abc/DEBIAN/control + install -m0755 -d debian/yosys/DEBIAN + echo misc:Depends= >> debian/yosys.substvars + echo misc:Pre-Depends= >> debian/yosys.substvars + install -m0755 -d debian/.debhelper/yosys/dbgsym-root/DEBIAN + dpkg-gencontrol -pyosys -ldebian/changelog -Tdebian/yosys.substvars -cdebian/control -Pdebian/.debhelper/yosys/dbgsym-root -UPre-Depends -URecommends -USuggests -UEnhances -UProvides -UEssential -UConflicts -DPriority=optional -UHomepage -UImportant -DAuto-Built-Package=debug-symbols -UProtected -UBuilt-Using -UStatic-Built-Using -DPackage=yosys-dbgsym "-DDepends=yosys (= \${binary:Version})" "-DDescription=debug symbols for yosys" "-DBuild-Ids=390fe52e2c917a37c74fc4851a24cef4547782a2 625c041309bfc31cecaa286e9512fcf3e5f89693" -DSection=debug -UMulti-Arch -UReplaces -UBreaks install -m0755 -d debian/yosys-doc/DEBIAN echo misc:Depends= >> debian/yosys-doc.substvars echo misc:Pre-Depends= >> debian/yosys-doc.substvars dpkg-gencontrol -pyosys-doc -ldebian/changelog -Tdebian/yosys-doc.substvars -cdebian/control -Pdebian/yosys-doc - chmod 0644 -- debian/yosys/DEBIAN/control - install -m0755 -d debian/yosys-dev/DEBIAN - echo misc:Depends= >> debian/yosys-dev.substvars - echo misc:Pre-Depends= >> debian/yosys-dev.substvars - dpkg-gencontrol -pyosys-dev -ldebian/changelog -Tdebian/yosys-dev.substvars -cdebian/control -Pdebian/yosys-dev dpkg-gencontrol: warning: Depends field of package yosys-dev: substitution variable ${shlibs:Depends} used, but is not defined dpkg-gencontrol: warning: Depends field of package yosys-dev: substitution variable ${python3:Depends} used, but is not defined + chmod 0644 -- debian/.debhelper/yosys/dbgsym-root/DEBIAN/control + dpkg-gencontrol -pyosys -ldebian/changelog -Tdebian/yosys.substvars -cdebian/control -Pdebian/yosys chmod 0644 -- debian/yosys-doc/DEBIAN/control + chmod 0644 -- debian/.debhelper/yosys-abc/dbgsym-root/DEBIAN/control + dpkg-gencontrol -pyosys-abc -ldebian/changelog -Tdebian/yosys-abc.substvars -cdebian/control -Pdebian/yosys-abc chmod 0644 -- debian/yosys-dev/DEBIAN/control + chmod 0644 -- debian/yosys/DEBIAN/control + chmod 0644 -- debian/yosys-abc/DEBIAN/control dh_md5sums - install -m0755 -d debian/yosys-abc/DEBIAN install -m0755 -d debian/yosys/DEBIAN + install -m0755 -d debian/yosys-doc/DEBIAN + install -m0755 -d debian/yosys-abc/DEBIAN + install -m0755 -d debian/yosys-dev/DEBIAN + cd debian/yosys-doc >/dev/null && xargs -r0 md5sum | perl -pe 'if (s@^\\@@) { s/\\\\/\\/g; }' > DEBIAN/md5sums cd debian/yosys-abc >/dev/null && xargs -r0 md5sum | perl -pe 'if (s@^\\@@) { s/\\\\/\\/g; }' > DEBIAN/md5sums cd debian/yosys >/dev/null && xargs -r0 md5sum | perl -pe 'if (s@^\\@@) { s/\\\\/\\/g; }' > DEBIAN/md5sums + cd debian/yosys-dev >/dev/null && xargs -r0 md5sum | perl -pe 'if (s@^\\@@) { s/\\\\/\\/g; }' > DEBIAN/md5sums + chmod 0644 -- debian/yosys-doc/DEBIAN/md5sums + chmod 0644 -- debian/yosys-dev/DEBIAN/md5sums chmod 0644 -- debian/yosys-abc/DEBIAN/md5sums install -m0755 -d debian/.debhelper/yosys-abc/dbgsym-root/DEBIAN cd debian/.debhelper/yosys-abc/dbgsym-root >/dev/null && xargs -r0 md5sum | perl -pe 'if (s@^\\@@) { s/\\\\/\\/g; }' > DEBIAN/md5sums @@ -65126,20 +64597,14 @@ install -m0755 -d debian/.debhelper/yosys/dbgsym-root/DEBIAN cd debian/.debhelper/yosys/dbgsym-root >/dev/null && xargs -r0 md5sum | perl -pe 'if (s@^\\@@) { s/\\\\/\\/g; }' > DEBIAN/md5sums chmod 0644 -- debian/.debhelper/yosys-abc/dbgsym-root/DEBIAN/md5sums - install -m0755 -d debian/yosys-doc/DEBIAN - cd debian/yosys-doc >/dev/null && xargs -r0 md5sum | perl -pe 'if (s@^\\@@) { s/\\\\/\\/g; }' > DEBIAN/md5sums - chmod 0644 -- debian/yosys-doc/DEBIAN/md5sums chmod 0644 -- debian/.debhelper/yosys/dbgsym-root/DEBIAN/md5sums - install -m0755 -d debian/yosys-dev/DEBIAN - cd debian/yosys-dev >/dev/null && xargs -r0 md5sum | perl -pe 'if (s@^\\@@) { s/\\\\/\\/g; }' > DEBIAN/md5sums - chmod 0644 -- debian/yosys-dev/DEBIAN/md5sums dh_builddeb dpkg-deb --root-owner-group --build debian/yosys .. dpkg-deb --root-owner-group --build debian/yosys-dev .. dpkg-deb --root-owner-group --build debian/.debhelper/yosys-abc/dbgsym-root .. -dpkg-deb: building package 'yosys' in '../yosys_0.52-1_armhf.deb'. dpkg-deb: building package 'yosys-dev' in '../yosys-dev_0.52-1_armhf.deb'. dpkg-deb: building package 'yosys-abc-dbgsym' in '../yosys-abc-dbgsym_0.52-1_armhf.deb'. +dpkg-deb: building package 'yosys' in '../yosys_0.52-1_armhf.deb'. dpkg-deb --root-owner-group --build debian/yosys-abc .. dpkg-deb: building package 'yosys-abc' in '../yosys-abc_0.52-1_armhf.deb'. dpkg-deb --root-owner-group --build debian/yosys-doc .. @@ -65154,12 +64619,14 @@ dpkg-buildpackage: info: binary-only upload (no source included) dpkg-genchanges: info: including full source code in upload I: copying local configuration +I: user script /srv/workspace/pbuilder/8277/tmp/hooks/B01_cleanup starting +I: user script /srv/workspace/pbuilder/8277/tmp/hooks/B01_cleanup finished I: unmounting dev/ptmx filesystem I: unmounting dev/pts filesystem I: unmounting dev/shm filesystem I: unmounting proc filesystem I: unmounting sys filesystem I: cleaning the build env -I: removing directory /srv/workspace/pbuilder/7386 and its subdirectories -I: Current time: Mon Apr 28 03:31:41 -12 2025 -I: pbuilder-time-stamp: 1745854301 +I: removing directory /srv/workspace/pbuilder/8277 and its subdirectories +I: Current time: Tue Apr 29 08:01:07 +14 2025 +I: pbuilder-time-stamp: 1745863267